1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCTargetDesc.h" 15 #include "Mips.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeMem(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeMemEVA(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 291 const void *Decoder); 292 293 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 294 unsigned Insn, 295 uint64_t Address, 296 const void *Decoder); 297 298 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 299 unsigned Insn, 300 uint64_t Address, 301 const void *Decoder); 302 303 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 304 unsigned Insn, 305 uint64_t Address, 306 const void *Decoder); 307 308 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 309 unsigned Insn, 310 uint64_t Address, 311 const void *Decoder); 312 313 static DecodeStatus DecodeSyncI(MCInst &Inst, 314 unsigned Insn, 315 uint64_t Address, 316 const void *Decoder); 317 318 static DecodeStatus DecodeSynciR6(MCInst &Inst, 319 unsigned Insn, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 324 uint64_t Address, const void *Decoder); 325 326 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 327 unsigned Insn, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 332 unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 337 unsigned Insn, 338 uint64_t Address, 339 const void *Decoder); 340 341 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 342 unsigned Insn, 343 uint64_t Address, 344 const void *Decoder); 345 346 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 347 unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 352 unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 357 unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 370 const void *Decoder); 371 372 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 378 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 383 unsigned Insn, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 398 unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset, int Scale> 403 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder); 406 407 template <unsigned Bits, int Offset> 408 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 409 uint64_t Address, 410 const void *Decoder) { 411 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 412 Decoder); 413 } 414 415 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 416 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeInsSize(MCInst &Inst, 421 unsigned Insn, 422 uint64_t Address, 423 const void *Decoder); 424 425 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 426 uint64_t Address, const void *Decoder); 427 428 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void *Decoder); 430 431 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 432 uint64_t Address, const void *Decoder); 433 434 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void *Decoder); 436 437 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 438 uint64_t Address, const void *Decoder); 439 440 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 441 /// handle. 442 template <typename InsnType> 443 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 444 const void *Decoder); 445 446 template <typename InsnType> 447 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 452 const void *Decoder); 453 454 template <typename InsnType> 455 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus 464 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 465 const void *Decoder); 466 467 template <typename InsnType> 468 static DecodeStatus 469 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 470 const void *Decoder); 471 472 template <typename InsnType> 473 static DecodeStatus 474 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 475 const void *Decoder); 476 477 template <typename InsnType> 478 static DecodeStatus 479 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 480 const void *Decoder); 481 482 template <typename InsnType> 483 static DecodeStatus 484 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 485 const void *Decoder); 486 487 template <typename InsnType> 488 static DecodeStatus 489 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 490 const void *Decoder); 491 492 template <typename InsnType> 493 static DecodeStatus 494 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 495 const void *Decoder); 496 497 template <typename InsnType> 498 static DecodeStatus 499 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 500 const void *Decoder); 501 502 template <typename InsnType> 503 static DecodeStatus 504 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 505 const void *Decoder); 506 507 template <typename InsnType> 508 static DecodeStatus 509 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 510 const void *Decoder); 511 512 template <typename InsnType> 513 static DecodeStatus 514 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 515 const void *Decoder); 516 517 template <typename InsnType> 518 static DecodeStatus 519 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 520 const void *Decoder); 521 522 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 523 uint64_t Address, 524 const void *Decoder); 525 526 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 527 uint64_t Address, 528 const void *Decoder); 529 530 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 531 uint64_t Address, 532 const void *Decoder); 533 534 namespace llvm { 535 536 Target &getTheMipselTarget(); 537 Target &getTheMipsTarget(); 538 Target &getTheMips64Target(); 539 Target &getTheMips64elTarget(); 540 541 } // end namespace llvm 542 543 static MCDisassembler *createMipsDisassembler( 544 const Target &T, 545 const MCSubtargetInfo &STI, 546 MCContext &Ctx) { 547 return new MipsDisassembler(STI, Ctx, true); 548 } 549 550 static MCDisassembler *createMipselDisassembler( 551 const Target &T, 552 const MCSubtargetInfo &STI, 553 MCContext &Ctx) { 554 return new MipsDisassembler(STI, Ctx, false); 555 } 556 557 extern "C" void LLVMInitializeMipsDisassembler() { 558 // Register the disassembler. 559 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 560 createMipsDisassembler); 561 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 562 createMipselDisassembler); 563 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 564 createMipsDisassembler); 565 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 566 createMipselDisassembler); 567 } 568 569 #include "MipsGenDisassemblerTables.inc" 570 571 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 572 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 573 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 574 return *(RegInfo->getRegClass(RC).begin() + RegNo); 575 } 576 577 template <typename InsnType> 578 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 579 const void *Decoder) { 580 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 581 582 // The size of the n field depends on the element size 583 // The register class also depends on this. 584 InsnType tmp = fieldFromInstruction(insn, 17, 5); 585 unsigned NSize = 0; 586 DecodeFN RegDecoder = nullptr; 587 if ((tmp & 0x18) == 0x00) { // INSVE_B 588 NSize = 4; 589 RegDecoder = DecodeMSA128BRegisterClass; 590 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 591 NSize = 3; 592 RegDecoder = DecodeMSA128HRegisterClass; 593 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 594 NSize = 2; 595 RegDecoder = DecodeMSA128WRegisterClass; 596 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 597 NSize = 1; 598 RegDecoder = DecodeMSA128DRegisterClass; 599 } else 600 llvm_unreachable("Invalid encoding"); 601 602 assert(NSize != 0 && RegDecoder != nullptr); 603 604 // $wd 605 tmp = fieldFromInstruction(insn, 6, 5); 606 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 607 return MCDisassembler::Fail; 608 // $wd_in 609 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 610 return MCDisassembler::Fail; 611 // $n 612 tmp = fieldFromInstruction(insn, 16, NSize); 613 MI.addOperand(MCOperand::createImm(tmp)); 614 // $ws 615 tmp = fieldFromInstruction(insn, 11, 5); 616 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 617 return MCDisassembler::Fail; 618 // $n2 619 MI.addOperand(MCOperand::createImm(0)); 620 621 return MCDisassembler::Success; 622 } 623 624 template <typename InsnType> 625 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 626 const void *Decoder) { 627 InsnType Rs = fieldFromInstruction(insn, 16, 5); 628 InsnType Imm = fieldFromInstruction(insn, 0, 16); 629 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 630 Rs))); 631 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 632 Rs))); 633 MI.addOperand(MCOperand::createImm(Imm)); 634 635 return MCDisassembler::Success; 636 } 637 638 template <typename InsnType> 639 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 640 const void *Decoder) { 641 InsnType Rs = fieldFromInstruction(insn, 21, 5); 642 InsnType Imm = fieldFromInstruction(insn, 0, 16); 643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 644 Rs))); 645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 646 Rs))); 647 MI.addOperand(MCOperand::createImm(Imm)); 648 649 return MCDisassembler::Success; 650 } 651 652 template <typename InsnType> 653 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 654 uint64_t Address, 655 const void *Decoder) { 656 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 657 // (otherwise we would have matched the ADDI instruction from the earlier 658 // ISA's instead). 659 // 660 // We have: 661 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 662 // BOVC if rs >= rt 663 // BEQZALC if rs == 0 && rt != 0 664 // BEQC if rs < rt && rs != 0 665 666 InsnType Rs = fieldFromInstruction(insn, 21, 5); 667 InsnType Rt = fieldFromInstruction(insn, 16, 5); 668 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 669 bool HasRs = false; 670 671 if (Rs >= Rt) { 672 MI.setOpcode(Mips::BOVC); 673 HasRs = true; 674 } else if (Rs != 0 && Rs < Rt) { 675 MI.setOpcode(Mips::BEQC); 676 HasRs = true; 677 } else 678 MI.setOpcode(Mips::BEQZALC); 679 680 if (HasRs) 681 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 682 Rs))); 683 684 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 685 Rt))); 686 MI.addOperand(MCOperand::createImm(Imm)); 687 688 return MCDisassembler::Success; 689 } 690 691 template <typename InsnType> 692 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 693 uint64_t Address, 694 const void *Decoder) { 695 InsnType Rt = fieldFromInstruction(insn, 21, 5); 696 InsnType Rs = fieldFromInstruction(insn, 16, 5); 697 int64_t Imm = 0; 698 699 if (Rs >= Rt) { 700 MI.setOpcode(Mips::BOVC_MMR6); 701 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 702 Rt))); 703 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 704 Rs))); 705 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 706 } else if (Rs != 0 && Rs < Rt) { 707 MI.setOpcode(Mips::BEQC_MMR6); 708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 709 Rs))); 710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 711 Rt))); 712 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 713 } else { 714 MI.setOpcode(Mips::BEQZALC_MMR6); 715 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 716 Rt))); 717 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 718 } 719 720 MI.addOperand(MCOperand::createImm(Imm)); 721 722 return MCDisassembler::Success; 723 } 724 725 template <typename InsnType> 726 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 727 uint64_t Address, 728 const void *Decoder) { 729 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 730 // (otherwise we would have matched the ADDI instruction from the earlier 731 // ISA's instead). 732 // 733 // We have: 734 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 735 // BNVC if rs >= rt 736 // BNEZALC if rs == 0 && rt != 0 737 // BNEC if rs < rt && rs != 0 738 739 InsnType Rs = fieldFromInstruction(insn, 21, 5); 740 InsnType Rt = fieldFromInstruction(insn, 16, 5); 741 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 742 bool HasRs = false; 743 744 if (Rs >= Rt) { 745 MI.setOpcode(Mips::BNVC); 746 HasRs = true; 747 } else if (Rs != 0 && Rs < Rt) { 748 MI.setOpcode(Mips::BNEC); 749 HasRs = true; 750 } else 751 MI.setOpcode(Mips::BNEZALC); 752 753 if (HasRs) 754 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 755 Rs))); 756 757 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 758 Rt))); 759 MI.addOperand(MCOperand::createImm(Imm)); 760 761 return MCDisassembler::Success; 762 } 763 764 template <typename InsnType> 765 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 766 uint64_t Address, 767 const void *Decoder) { 768 InsnType Rt = fieldFromInstruction(insn, 21, 5); 769 InsnType Rs = fieldFromInstruction(insn, 16, 5); 770 int64_t Imm = 0; 771 772 if (Rs >= Rt) { 773 MI.setOpcode(Mips::BNVC_MMR6); 774 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 775 Rt))); 776 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 777 Rs))); 778 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 779 } else if (Rs != 0 && Rs < Rt) { 780 MI.setOpcode(Mips::BNEC_MMR6); 781 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 782 Rs))); 783 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 784 Rt))); 785 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 786 } else { 787 MI.setOpcode(Mips::BNEZALC_MMR6); 788 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 789 Rt))); 790 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 791 } 792 793 MI.addOperand(MCOperand::createImm(Imm)); 794 795 return MCDisassembler::Success; 796 } 797 798 template <typename InsnType> 799 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 800 uint64_t Address, 801 const void *Decoder) { 802 // We have: 803 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 804 // Invalid if rt == 0 805 // BGTZC_MMR6 if rs == 0 && rt != 0 806 // BLTZC_MMR6 if rs == rt && rt != 0 807 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 808 809 InsnType Rt = fieldFromInstruction(insn, 21, 5); 810 InsnType Rs = fieldFromInstruction(insn, 16, 5); 811 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 812 bool HasRs = false; 813 814 if (Rt == 0) 815 return MCDisassembler::Fail; 816 else if (Rs == 0) 817 MI.setOpcode(Mips::BGTZC_MMR6); 818 else if (Rs == Rt) 819 MI.setOpcode(Mips::BLTZC_MMR6); 820 else { 821 MI.setOpcode(Mips::BLTC_MMR6); 822 HasRs = true; 823 } 824 825 if (HasRs) 826 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 827 Rs))); 828 829 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 830 Rt))); 831 832 MI.addOperand(MCOperand::createImm(Imm)); 833 834 return MCDisassembler::Success; 835 } 836 837 template <typename InsnType> 838 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 839 uint64_t Address, 840 const void *Decoder) { 841 // We have: 842 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 843 // Invalid if rt == 0 844 // BLEZC_MMR6 if rs == 0 && rt != 0 845 // BGEZC_MMR6 if rs == rt && rt != 0 846 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 847 848 InsnType Rt = fieldFromInstruction(insn, 21, 5); 849 InsnType Rs = fieldFromInstruction(insn, 16, 5); 850 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 851 bool HasRs = false; 852 853 if (Rt == 0) 854 return MCDisassembler::Fail; 855 else if (Rs == 0) 856 MI.setOpcode(Mips::BLEZC_MMR6); 857 else if (Rs == Rt) 858 MI.setOpcode(Mips::BGEZC_MMR6); 859 else { 860 HasRs = true; 861 MI.setOpcode(Mips::BGEC_MMR6); 862 } 863 864 if (HasRs) 865 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 866 Rs))); 867 868 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 869 Rt))); 870 871 MI.addOperand(MCOperand::createImm(Imm)); 872 873 return MCDisassembler::Success; 874 } 875 876 template <typename InsnType> 877 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 878 uint64_t Address, 879 const void *Decoder) { 880 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 881 // (otherwise we would have matched the BLEZL instruction from the earlier 882 // ISA's instead). 883 // 884 // We have: 885 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 886 // Invalid if rs == 0 887 // BLEZC if rs == 0 && rt != 0 888 // BGEZC if rs == rt && rt != 0 889 // BGEC if rs != rt && rs != 0 && rt != 0 890 891 InsnType Rs = fieldFromInstruction(insn, 21, 5); 892 InsnType Rt = fieldFromInstruction(insn, 16, 5); 893 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 894 bool HasRs = false; 895 896 if (Rt == 0) 897 return MCDisassembler::Fail; 898 else if (Rs == 0) 899 MI.setOpcode(Mips::BLEZC); 900 else if (Rs == Rt) 901 MI.setOpcode(Mips::BGEZC); 902 else { 903 HasRs = true; 904 MI.setOpcode(Mips::BGEC); 905 } 906 907 if (HasRs) 908 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 909 Rs))); 910 911 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 912 Rt))); 913 914 MI.addOperand(MCOperand::createImm(Imm)); 915 916 return MCDisassembler::Success; 917 } 918 919 template <typename InsnType> 920 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 921 uint64_t Address, 922 const void *Decoder) { 923 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 924 // (otherwise we would have matched the BGTZL instruction from the earlier 925 // ISA's instead). 926 // 927 // We have: 928 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 929 // Invalid if rs == 0 930 // BGTZC if rs == 0 && rt != 0 931 // BLTZC if rs == rt && rt != 0 932 // BLTC if rs != rt && rs != 0 && rt != 0 933 934 bool HasRs = false; 935 936 InsnType Rs = fieldFromInstruction(insn, 21, 5); 937 InsnType Rt = fieldFromInstruction(insn, 16, 5); 938 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 939 940 if (Rt == 0) 941 return MCDisassembler::Fail; 942 else if (Rs == 0) 943 MI.setOpcode(Mips::BGTZC); 944 else if (Rs == Rt) 945 MI.setOpcode(Mips::BLTZC); 946 else { 947 MI.setOpcode(Mips::BLTC); 948 HasRs = true; 949 } 950 951 if (HasRs) 952 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 953 Rs))); 954 955 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 956 Rt))); 957 958 MI.addOperand(MCOperand::createImm(Imm)); 959 960 return MCDisassembler::Success; 961 } 962 963 template <typename InsnType> 964 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 965 uint64_t Address, 966 const void *Decoder) { 967 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 968 // (otherwise we would have matched the BGTZ instruction from the earlier 969 // ISA's instead). 970 // 971 // We have: 972 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 973 // BGTZ if rt == 0 974 // BGTZALC if rs == 0 && rt != 0 975 // BLTZALC if rs != 0 && rs == rt 976 // BLTUC if rs != 0 && rs != rt 977 978 InsnType Rs = fieldFromInstruction(insn, 21, 5); 979 InsnType Rt = fieldFromInstruction(insn, 16, 5); 980 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 981 bool HasRs = false; 982 bool HasRt = false; 983 984 if (Rt == 0) { 985 MI.setOpcode(Mips::BGTZ); 986 HasRs = true; 987 } else if (Rs == 0) { 988 MI.setOpcode(Mips::BGTZALC); 989 HasRt = true; 990 } else if (Rs == Rt) { 991 MI.setOpcode(Mips::BLTZALC); 992 HasRs = true; 993 } else { 994 MI.setOpcode(Mips::BLTUC); 995 HasRs = true; 996 HasRt = true; 997 } 998 999 if (HasRs) 1000 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1001 Rs))); 1002 1003 if (HasRt) 1004 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1005 Rt))); 1006 1007 MI.addOperand(MCOperand::createImm(Imm)); 1008 1009 return MCDisassembler::Success; 1010 } 1011 1012 template <typename InsnType> 1013 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1014 uint64_t Address, 1015 const void *Decoder) { 1016 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1017 // (otherwise we would have matched the BLEZL instruction from the earlier 1018 // ISA's instead). 1019 // 1020 // We have: 1021 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1022 // Invalid if rs == 0 1023 // BLEZALC if rs == 0 && rt != 0 1024 // BGEZALC if rs == rt && rt != 0 1025 // BGEUC if rs != rt && rs != 0 && rt != 0 1026 1027 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1028 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1029 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1030 bool HasRs = false; 1031 1032 if (Rt == 0) 1033 return MCDisassembler::Fail; 1034 else if (Rs == 0) 1035 MI.setOpcode(Mips::BLEZALC); 1036 else if (Rs == Rt) 1037 MI.setOpcode(Mips::BGEZALC); 1038 else { 1039 HasRs = true; 1040 MI.setOpcode(Mips::BGEUC); 1041 } 1042 1043 if (HasRs) 1044 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1045 Rs))); 1046 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1047 Rt))); 1048 1049 MI.addOperand(MCOperand::createImm(Imm)); 1050 1051 return MCDisassembler::Success; 1052 } 1053 1054 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1055 /// according to the given endianness. 1056 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1057 uint64_t &Size, uint32_t &Insn, 1058 bool IsBigEndian) { 1059 // We want to read exactly 2 Bytes of data. 1060 if (Bytes.size() < 2) { 1061 Size = 0; 1062 return MCDisassembler::Fail; 1063 } 1064 1065 if (IsBigEndian) { 1066 Insn = (Bytes[0] << 8) | Bytes[1]; 1067 } else { 1068 Insn = (Bytes[1] << 8) | Bytes[0]; 1069 } 1070 1071 return MCDisassembler::Success; 1072 } 1073 1074 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1075 /// according to the given endianness. 1076 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1077 uint64_t &Size, uint32_t &Insn, 1078 bool IsBigEndian, bool IsMicroMips) { 1079 // We want to read exactly 4 Bytes of data. 1080 if (Bytes.size() < 4) { 1081 Size = 0; 1082 return MCDisassembler::Fail; 1083 } 1084 1085 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1086 // always precede the low 16 bits in the instruction stream (that is, they 1087 // are placed at lower addresses in the instruction stream). 1088 // 1089 // microMIPS byte ordering: 1090 // Big-endian: 0 | 1 | 2 | 3 1091 // Little-endian: 1 | 0 | 3 | 2 1092 1093 if (IsBigEndian) { 1094 // Encoded as a big-endian 32-bit word in the stream. 1095 Insn = 1096 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1097 } else { 1098 if (IsMicroMips) { 1099 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1100 (Bytes[1] << 24); 1101 } else { 1102 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1103 (Bytes[3] << 24); 1104 } 1105 } 1106 1107 return MCDisassembler::Success; 1108 } 1109 1110 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1111 ArrayRef<uint8_t> Bytes, 1112 uint64_t Address, 1113 raw_ostream &VStream, 1114 raw_ostream &CStream) const { 1115 uint32_t Insn; 1116 DecodeStatus Result; 1117 Size = 0; 1118 1119 if (IsMicroMips) { 1120 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1121 if (Result == MCDisassembler::Fail) 1122 return MCDisassembler::Fail; 1123 1124 if (hasMips32r6()) { 1125 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1126 // Calling the auto-generated decoder function for microMIPS32R6 1127 // (and microMIPS64R6) 16-bit instructions. 1128 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1129 Address, this, STI); 1130 if (Result != MCDisassembler::Fail) { 1131 Size = 2; 1132 return Result; 1133 } 1134 } 1135 1136 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1137 // Calling the auto-generated decoder function for microMIPS 16-bit 1138 // instructions. 1139 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1140 this, STI); 1141 if (Result != MCDisassembler::Fail) { 1142 Size = 2; 1143 return Result; 1144 } 1145 1146 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1147 if (Result == MCDisassembler::Fail) 1148 return MCDisassembler::Fail; 1149 1150 if (hasMips32r6()) { 1151 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1152 // Calling the auto-generated decoder function. 1153 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1154 this, STI); 1155 if (Result != MCDisassembler::Fail) { 1156 Size = 4; 1157 return Result; 1158 } 1159 } 1160 1161 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1162 // Calling the auto-generated decoder function. 1163 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1164 this, STI); 1165 if (Result != MCDisassembler::Fail) { 1166 Size = 4; 1167 return Result; 1168 } 1169 1170 if (hasMips32r6() && isFP64()) { 1171 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 1172 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 1173 Address, this, STI); 1174 if (Result != MCDisassembler::Fail) { 1175 Size = 4; 1176 return Result; 1177 } 1178 } 1179 1180 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1181 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1182 // could form a valid instruction. The two bytes we rejected as an 1183 // instruction could have actually beeen an inline constant pool that is 1184 // unconditionally branched over. 1185 Size = 2; 1186 return MCDisassembler::Fail; 1187 } 1188 1189 // Attempt to read the instruction so that we can attempt to decode it. If 1190 // the buffer is not 4 bytes long, let the higher level logic figure out 1191 // what to do with a size of zero and MCDisassembler::Fail. 1192 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1193 if (Result == MCDisassembler::Fail) 1194 return MCDisassembler::Fail; 1195 1196 // The only instruction size for standard encoded MIPS. 1197 Size = 4; 1198 1199 if (hasCOP3()) { 1200 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1201 Result = 1202 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1203 if (Result != MCDisassembler::Fail) 1204 return Result; 1205 } 1206 1207 if (hasMips32r6() && isGP64()) { 1208 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1209 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1210 Address, this, STI); 1211 if (Result != MCDisassembler::Fail) 1212 return Result; 1213 } 1214 1215 if (hasMips32r6() && isPTR64()) { 1216 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1217 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1218 Address, this, STI); 1219 if (Result != MCDisassembler::Fail) 1220 return Result; 1221 } 1222 1223 if (hasMips32r6()) { 1224 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1225 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1226 Address, this, STI); 1227 if (Result != MCDisassembler::Fail) 1228 return Result; 1229 } 1230 1231 if (hasMips2() && isPTR64()) { 1232 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1233 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1234 Address, this, STI); 1235 if (Result != MCDisassembler::Fail) 1236 return Result; 1237 } 1238 1239 if (hasCnMips()) { 1240 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1241 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1242 Address, this, STI); 1243 if (Result != MCDisassembler::Fail) 1244 return Result; 1245 } 1246 1247 if (isGP64()) { 1248 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1249 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1250 Address, this, STI); 1251 if (Result != MCDisassembler::Fail) 1252 return Result; 1253 } 1254 1255 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1256 // Calling the auto-generated decoder function. 1257 Result = 1258 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1259 if (Result != MCDisassembler::Fail) 1260 return Result; 1261 1262 return MCDisassembler::Fail; 1263 } 1264 1265 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1266 unsigned RegNo, 1267 uint64_t Address, 1268 const void *Decoder) { 1269 return MCDisassembler::Fail; 1270 } 1271 1272 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1273 unsigned RegNo, 1274 uint64_t Address, 1275 const void *Decoder) { 1276 if (RegNo > 31) 1277 return MCDisassembler::Fail; 1278 1279 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1280 Inst.addOperand(MCOperand::createReg(Reg)); 1281 return MCDisassembler::Success; 1282 } 1283 1284 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1285 unsigned RegNo, 1286 uint64_t Address, 1287 const void *Decoder) { 1288 if (RegNo > 7) 1289 return MCDisassembler::Fail; 1290 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1291 Inst.addOperand(MCOperand::createReg(Reg)); 1292 return MCDisassembler::Success; 1293 } 1294 1295 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1296 unsigned RegNo, 1297 uint64_t Address, 1298 const void *Decoder) { 1299 if (RegNo > 7) 1300 return MCDisassembler::Fail; 1301 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1302 Inst.addOperand(MCOperand::createReg(Reg)); 1303 return MCDisassembler::Success; 1304 } 1305 1306 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1307 unsigned RegNo, 1308 uint64_t Address, 1309 const void *Decoder) { 1310 if (RegNo > 7) 1311 return MCDisassembler::Fail; 1312 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1313 Inst.addOperand(MCOperand::createReg(Reg)); 1314 return MCDisassembler::Success; 1315 } 1316 1317 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1318 unsigned RegNo, 1319 uint64_t Address, 1320 const void *Decoder) { 1321 if (RegNo > 31) 1322 return MCDisassembler::Fail; 1323 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1324 Inst.addOperand(MCOperand::createReg(Reg)); 1325 return MCDisassembler::Success; 1326 } 1327 1328 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1329 unsigned RegNo, 1330 uint64_t Address, 1331 const void *Decoder) { 1332 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1333 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1334 1335 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1336 } 1337 1338 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1339 unsigned RegNo, 1340 uint64_t Address, 1341 const void *Decoder) { 1342 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1343 } 1344 1345 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1346 unsigned RegNo, 1347 uint64_t Address, 1348 const void *Decoder) { 1349 if (RegNo > 31) 1350 return MCDisassembler::Fail; 1351 1352 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1353 Inst.addOperand(MCOperand::createReg(Reg)); 1354 return MCDisassembler::Success; 1355 } 1356 1357 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1358 unsigned RegNo, 1359 uint64_t Address, 1360 const void *Decoder) { 1361 if (RegNo > 31) 1362 return MCDisassembler::Fail; 1363 1364 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1365 Inst.addOperand(MCOperand::createReg(Reg)); 1366 return MCDisassembler::Success; 1367 } 1368 1369 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1370 unsigned RegNo, 1371 uint64_t Address, 1372 const void *Decoder) { 1373 if (RegNo > 31) 1374 return MCDisassembler::Fail; 1375 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1376 Inst.addOperand(MCOperand::createReg(Reg)); 1377 return MCDisassembler::Success; 1378 } 1379 1380 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1381 unsigned RegNo, 1382 uint64_t Address, 1383 const void *Decoder) { 1384 if (RegNo > 7) 1385 return MCDisassembler::Fail; 1386 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1387 Inst.addOperand(MCOperand::createReg(Reg)); 1388 return MCDisassembler::Success; 1389 } 1390 1391 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1392 uint64_t Address, 1393 const void *Decoder) { 1394 if (RegNo > 31) 1395 return MCDisassembler::Fail; 1396 1397 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1398 Inst.addOperand(MCOperand::createReg(Reg)); 1399 return MCDisassembler::Success; 1400 } 1401 1402 static DecodeStatus DecodeMem(MCInst &Inst, 1403 unsigned Insn, 1404 uint64_t Address, 1405 const void *Decoder) { 1406 int Offset = SignExtend32<16>(Insn & 0xffff); 1407 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1408 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1409 1410 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1411 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1412 1413 if (Inst.getOpcode() == Mips::SC || 1414 Inst.getOpcode() == Mips::SCD) 1415 Inst.addOperand(MCOperand::createReg(Reg)); 1416 1417 Inst.addOperand(MCOperand::createReg(Reg)); 1418 Inst.addOperand(MCOperand::createReg(Base)); 1419 Inst.addOperand(MCOperand::createImm(Offset)); 1420 1421 return MCDisassembler::Success; 1422 } 1423 1424 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1425 unsigned Insn, 1426 uint64_t Address, 1427 const void *Decoder) { 1428 int Offset = SignExtend32<9>(Insn >> 7); 1429 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1430 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1431 1432 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1433 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1434 1435 if (Inst.getOpcode() == Mips::SCE) 1436 Inst.addOperand(MCOperand::createReg(Reg)); 1437 1438 Inst.addOperand(MCOperand::createReg(Reg)); 1439 Inst.addOperand(MCOperand::createReg(Base)); 1440 Inst.addOperand(MCOperand::createImm(Offset)); 1441 1442 return MCDisassembler::Success; 1443 } 1444 1445 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1446 unsigned Insn, 1447 uint64_t Address, 1448 const void *Decoder) { 1449 int Offset = SignExtend32<9>(Insn & 0x1ff); 1450 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1451 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1452 1453 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1454 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1455 1456 Inst.addOperand(MCOperand::createReg(Reg)); 1457 Inst.addOperand(MCOperand::createReg(Base)); 1458 Inst.addOperand(MCOperand::createImm(Offset)); 1459 1460 return MCDisassembler::Success; 1461 } 1462 1463 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1464 unsigned Insn, 1465 uint64_t Address, 1466 const void *Decoder) { 1467 int Offset = SignExtend32<16>(Insn & 0xffff); 1468 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1469 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1470 1471 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1472 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1473 1474 Inst.addOperand(MCOperand::createReg(Reg)); 1475 Inst.addOperand(MCOperand::createReg(Base)); 1476 Inst.addOperand(MCOperand::createImm(Offset)); 1477 1478 return MCDisassembler::Success; 1479 } 1480 1481 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1482 unsigned Insn, 1483 uint64_t Address, 1484 const void *Decoder) { 1485 int Offset = SignExtend32<16>(Insn & 0xffff); 1486 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1487 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1488 1489 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1490 1491 Inst.addOperand(MCOperand::createReg(Base)); 1492 Inst.addOperand(MCOperand::createImm(Offset)); 1493 Inst.addOperand(MCOperand::createImm(Hint)); 1494 1495 return MCDisassembler::Success; 1496 } 1497 1498 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1499 unsigned Insn, 1500 uint64_t Address, 1501 const void *Decoder) { 1502 int Offset = SignExtend32<12>(Insn & 0xfff); 1503 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1504 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1505 1506 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1507 1508 Inst.addOperand(MCOperand::createReg(Base)); 1509 Inst.addOperand(MCOperand::createImm(Offset)); 1510 Inst.addOperand(MCOperand::createImm(Hint)); 1511 1512 return MCDisassembler::Success; 1513 } 1514 1515 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1516 unsigned Insn, 1517 uint64_t Address, 1518 const void *Decoder) { 1519 int Offset = SignExtend32<9>(Insn & 0x1ff); 1520 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1521 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1522 1523 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1524 1525 Inst.addOperand(MCOperand::createReg(Base)); 1526 Inst.addOperand(MCOperand::createImm(Offset)); 1527 Inst.addOperand(MCOperand::createImm(Hint)); 1528 1529 return MCDisassembler::Success; 1530 } 1531 1532 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1533 unsigned Insn, 1534 uint64_t Address, 1535 const void *Decoder) { 1536 int Offset = SignExtend32<9>(Insn >> 7); 1537 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1538 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1539 1540 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1541 1542 Inst.addOperand(MCOperand::createReg(Base)); 1543 Inst.addOperand(MCOperand::createImm(Offset)); 1544 Inst.addOperand(MCOperand::createImm(Hint)); 1545 1546 return MCDisassembler::Success; 1547 } 1548 1549 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1550 unsigned Insn, 1551 uint64_t Address, 1552 const void *Decoder) { 1553 int Offset = SignExtend32<9>(Insn & 0x1ff); 1554 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1555 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1556 1557 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1558 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1559 1560 Inst.addOperand(MCOperand::createReg(Reg)); 1561 Inst.addOperand(MCOperand::createReg(Base)); 1562 Inst.addOperand(MCOperand::createImm(Offset)); 1563 1564 return MCDisassembler::Success; 1565 } 1566 1567 static DecodeStatus DecodeSyncI(MCInst &Inst, 1568 unsigned Insn, 1569 uint64_t Address, 1570 const void *Decoder) { 1571 int Offset = SignExtend32<16>(Insn & 0xffff); 1572 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1573 1574 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1575 1576 Inst.addOperand(MCOperand::createReg(Base)); 1577 Inst.addOperand(MCOperand::createImm(Offset)); 1578 1579 return MCDisassembler::Success; 1580 } 1581 1582 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1583 unsigned Insn, 1584 uint64_t Address, 1585 const void *Decoder) { 1586 int Immediate = SignExtend32<16>(Insn & 0xffff); 1587 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1588 1589 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1590 1591 Inst.addOperand(MCOperand::createReg(Base)); 1592 Inst.addOperand(MCOperand::createImm(Immediate)); 1593 1594 return MCDisassembler::Success; 1595 } 1596 1597 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1598 uint64_t Address, const void *Decoder) { 1599 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1600 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1601 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1602 1603 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1604 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1605 1606 Inst.addOperand(MCOperand::createReg(Reg)); 1607 Inst.addOperand(MCOperand::createReg(Base)); 1608 1609 // The immediate field of an LD/ST instruction is scaled which means it must 1610 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1611 // data format. 1612 // .b - 1 byte 1613 // .h - 2 bytes 1614 // .w - 4 bytes 1615 // .d - 8 bytes 1616 switch(Inst.getOpcode()) 1617 { 1618 default: 1619 assert(false && "Unexpected instruction"); 1620 return MCDisassembler::Fail; 1621 break; 1622 case Mips::LD_B: 1623 case Mips::ST_B: 1624 Inst.addOperand(MCOperand::createImm(Offset)); 1625 break; 1626 case Mips::LD_H: 1627 case Mips::ST_H: 1628 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1629 break; 1630 case Mips::LD_W: 1631 case Mips::ST_W: 1632 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1633 break; 1634 case Mips::LD_D: 1635 case Mips::ST_D: 1636 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1637 break; 1638 } 1639 1640 return MCDisassembler::Success; 1641 } 1642 1643 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1644 unsigned Insn, 1645 uint64_t Address, 1646 const void *Decoder) { 1647 unsigned Offset = Insn & 0xf; 1648 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1649 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1650 1651 switch (Inst.getOpcode()) { 1652 case Mips::LBU16_MM: 1653 case Mips::LHU16_MM: 1654 case Mips::LW16_MM: 1655 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1656 == MCDisassembler::Fail) 1657 return MCDisassembler::Fail; 1658 break; 1659 case Mips::SB16_MM: 1660 case Mips::SB16_MMR6: 1661 case Mips::SH16_MM: 1662 case Mips::SH16_MMR6: 1663 case Mips::SW16_MM: 1664 case Mips::SW16_MMR6: 1665 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1666 == MCDisassembler::Fail) 1667 return MCDisassembler::Fail; 1668 break; 1669 } 1670 1671 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1672 == MCDisassembler::Fail) 1673 return MCDisassembler::Fail; 1674 1675 switch (Inst.getOpcode()) { 1676 case Mips::LBU16_MM: 1677 if (Offset == 0xf) 1678 Inst.addOperand(MCOperand::createImm(-1)); 1679 else 1680 Inst.addOperand(MCOperand::createImm(Offset)); 1681 break; 1682 case Mips::SB16_MM: 1683 case Mips::SB16_MMR6: 1684 Inst.addOperand(MCOperand::createImm(Offset)); 1685 break; 1686 case Mips::LHU16_MM: 1687 case Mips::SH16_MM: 1688 case Mips::SH16_MMR6: 1689 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1690 break; 1691 case Mips::LW16_MM: 1692 case Mips::SW16_MM: 1693 case Mips::SW16_MMR6: 1694 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1695 break; 1696 } 1697 1698 return MCDisassembler::Success; 1699 } 1700 1701 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1702 unsigned Insn, 1703 uint64_t Address, 1704 const void *Decoder) { 1705 unsigned Offset = Insn & 0x1F; 1706 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1707 1708 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1709 1710 Inst.addOperand(MCOperand::createReg(Reg)); 1711 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1712 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1713 1714 return MCDisassembler::Success; 1715 } 1716 1717 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1718 unsigned Insn, 1719 uint64_t Address, 1720 const void *Decoder) { 1721 unsigned Offset = Insn & 0x7F; 1722 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1723 1724 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1725 1726 Inst.addOperand(MCOperand::createReg(Reg)); 1727 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1728 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1729 1730 return MCDisassembler::Success; 1731 } 1732 1733 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1734 unsigned Insn, 1735 uint64_t Address, 1736 const void *Decoder) { 1737 int Offset; 1738 switch (Inst.getOpcode()) { 1739 case Mips::LWM16_MMR6: 1740 case Mips::SWM16_MMR6: 1741 Offset = fieldFromInstruction(Insn, 4, 4); 1742 break; 1743 default: 1744 Offset = SignExtend32<4>(Insn & 0xf); 1745 break; 1746 } 1747 1748 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1749 == MCDisassembler::Fail) 1750 return MCDisassembler::Fail; 1751 1752 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1753 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1754 1755 return MCDisassembler::Success; 1756 } 1757 1758 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1759 unsigned Insn, 1760 uint64_t Address, 1761 const void *Decoder) { 1762 int Offset = SignExtend32<9>(Insn & 0x1ff); 1763 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1764 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1765 1766 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1767 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1768 1769 if (Inst.getOpcode() == Mips::SCE_MM) 1770 Inst.addOperand(MCOperand::createReg(Reg)); 1771 1772 Inst.addOperand(MCOperand::createReg(Reg)); 1773 Inst.addOperand(MCOperand::createReg(Base)); 1774 Inst.addOperand(MCOperand::createImm(Offset)); 1775 1776 return MCDisassembler::Success; 1777 } 1778 1779 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1780 unsigned Insn, 1781 uint64_t Address, 1782 const void *Decoder) { 1783 int Offset = SignExtend32<12>(Insn & 0x0fff); 1784 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1785 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1786 1787 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1788 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1789 1790 switch (Inst.getOpcode()) { 1791 case Mips::SWM32_MM: 1792 case Mips::LWM32_MM: 1793 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1794 == MCDisassembler::Fail) 1795 return MCDisassembler::Fail; 1796 Inst.addOperand(MCOperand::createReg(Base)); 1797 Inst.addOperand(MCOperand::createImm(Offset)); 1798 break; 1799 case Mips::SC_MM: 1800 Inst.addOperand(MCOperand::createReg(Reg)); 1801 LLVM_FALLTHROUGH; 1802 default: 1803 Inst.addOperand(MCOperand::createReg(Reg)); 1804 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1805 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1806 Inst.addOperand(MCOperand::createReg(Reg+1)); 1807 1808 Inst.addOperand(MCOperand::createReg(Base)); 1809 Inst.addOperand(MCOperand::createImm(Offset)); 1810 } 1811 1812 return MCDisassembler::Success; 1813 } 1814 1815 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1816 unsigned Insn, 1817 uint64_t Address, 1818 const void *Decoder) { 1819 int Offset = SignExtend32<16>(Insn & 0xffff); 1820 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1821 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1822 1823 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1824 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1825 1826 Inst.addOperand(MCOperand::createReg(Reg)); 1827 Inst.addOperand(MCOperand::createReg(Base)); 1828 Inst.addOperand(MCOperand::createImm(Offset)); 1829 1830 return MCDisassembler::Success; 1831 } 1832 1833 static DecodeStatus DecodeFMem(MCInst &Inst, 1834 unsigned Insn, 1835 uint64_t Address, 1836 const void *Decoder) { 1837 int Offset = SignExtend32<16>(Insn & 0xffff); 1838 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1839 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1840 1841 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1842 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1843 1844 Inst.addOperand(MCOperand::createReg(Reg)); 1845 Inst.addOperand(MCOperand::createReg(Base)); 1846 Inst.addOperand(MCOperand::createImm(Offset)); 1847 1848 return MCDisassembler::Success; 1849 } 1850 1851 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1852 uint64_t Address, const void *Decoder) { 1853 // This function is the same as DecodeFMem but with the Reg and Base fields 1854 // swapped according to microMIPS spec. 1855 int Offset = SignExtend32<16>(Insn & 0xffff); 1856 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1857 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1858 1859 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1860 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1861 1862 Inst.addOperand(MCOperand::createReg(Reg)); 1863 Inst.addOperand(MCOperand::createReg(Base)); 1864 Inst.addOperand(MCOperand::createImm(Offset)); 1865 1866 return MCDisassembler::Success; 1867 } 1868 1869 static DecodeStatus DecodeFMem2(MCInst &Inst, 1870 unsigned Insn, 1871 uint64_t Address, 1872 const void *Decoder) { 1873 int Offset = SignExtend32<16>(Insn & 0xffff); 1874 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1875 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1876 1877 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1878 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1879 1880 Inst.addOperand(MCOperand::createReg(Reg)); 1881 Inst.addOperand(MCOperand::createReg(Base)); 1882 Inst.addOperand(MCOperand::createImm(Offset)); 1883 1884 return MCDisassembler::Success; 1885 } 1886 1887 static DecodeStatus DecodeFMem3(MCInst &Inst, 1888 unsigned Insn, 1889 uint64_t Address, 1890 const void *Decoder) { 1891 int Offset = SignExtend32<16>(Insn & 0xffff); 1892 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1893 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1894 1895 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1896 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1897 1898 Inst.addOperand(MCOperand::createReg(Reg)); 1899 Inst.addOperand(MCOperand::createReg(Base)); 1900 Inst.addOperand(MCOperand::createImm(Offset)); 1901 1902 return MCDisassembler::Success; 1903 } 1904 1905 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1906 unsigned Insn, 1907 uint64_t Address, 1908 const void *Decoder) { 1909 int Offset = SignExtend32<11>(Insn & 0x07ff); 1910 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1911 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1912 1913 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1914 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1915 1916 Inst.addOperand(MCOperand::createReg(Reg)); 1917 Inst.addOperand(MCOperand::createReg(Base)); 1918 Inst.addOperand(MCOperand::createImm(Offset)); 1919 1920 return MCDisassembler::Success; 1921 } 1922 1923 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1924 uint64_t Address, const void *Decoder) { 1925 int Offset = SignExtend32<11>(Insn & 0x07ff); 1926 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1927 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1928 1929 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1930 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1931 1932 Inst.addOperand(MCOperand::createReg(Reg)); 1933 Inst.addOperand(MCOperand::createReg(Base)); 1934 Inst.addOperand(MCOperand::createImm(Offset)); 1935 1936 return MCDisassembler::Success; 1937 } 1938 1939 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1940 unsigned Insn, 1941 uint64_t Address, 1942 const void *Decoder) { 1943 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1944 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1945 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1946 1947 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1948 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1949 1950 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1951 Inst.addOperand(MCOperand::createReg(Rt)); 1952 } 1953 1954 Inst.addOperand(MCOperand::createReg(Rt)); 1955 Inst.addOperand(MCOperand::createReg(Base)); 1956 Inst.addOperand(MCOperand::createImm(Offset)); 1957 1958 return MCDisassembler::Success; 1959 } 1960 1961 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1962 unsigned RegNo, 1963 uint64_t Address, 1964 const void *Decoder) { 1965 // Currently only hardware register 29 is supported. 1966 if (RegNo != 29) 1967 return MCDisassembler::Fail; 1968 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1969 return MCDisassembler::Success; 1970 } 1971 1972 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1973 unsigned RegNo, 1974 uint64_t Address, 1975 const void *Decoder) { 1976 if (RegNo > 30 || RegNo %2) 1977 return MCDisassembler::Fail; 1978 1979 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1980 Inst.addOperand(MCOperand::createReg(Reg)); 1981 return MCDisassembler::Success; 1982 } 1983 1984 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1985 unsigned RegNo, 1986 uint64_t Address, 1987 const void *Decoder) { 1988 if (RegNo >= 4) 1989 return MCDisassembler::Fail; 1990 1991 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1992 Inst.addOperand(MCOperand::createReg(Reg)); 1993 return MCDisassembler::Success; 1994 } 1995 1996 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1997 unsigned RegNo, 1998 uint64_t Address, 1999 const void *Decoder) { 2000 if (RegNo >= 4) 2001 return MCDisassembler::Fail; 2002 2003 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2004 Inst.addOperand(MCOperand::createReg(Reg)); 2005 return MCDisassembler::Success; 2006 } 2007 2008 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2009 unsigned RegNo, 2010 uint64_t Address, 2011 const void *Decoder) { 2012 if (RegNo >= 4) 2013 return MCDisassembler::Fail; 2014 2015 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2016 Inst.addOperand(MCOperand::createReg(Reg)); 2017 return MCDisassembler::Success; 2018 } 2019 2020 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2021 unsigned RegNo, 2022 uint64_t Address, 2023 const void *Decoder) { 2024 if (RegNo > 31) 2025 return MCDisassembler::Fail; 2026 2027 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2028 Inst.addOperand(MCOperand::createReg(Reg)); 2029 return MCDisassembler::Success; 2030 } 2031 2032 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2033 unsigned RegNo, 2034 uint64_t Address, 2035 const void *Decoder) { 2036 if (RegNo > 31) 2037 return MCDisassembler::Fail; 2038 2039 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2040 Inst.addOperand(MCOperand::createReg(Reg)); 2041 return MCDisassembler::Success; 2042 } 2043 2044 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2045 unsigned RegNo, 2046 uint64_t Address, 2047 const void *Decoder) { 2048 if (RegNo > 31) 2049 return MCDisassembler::Fail; 2050 2051 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2052 Inst.addOperand(MCOperand::createReg(Reg)); 2053 return MCDisassembler::Success; 2054 } 2055 2056 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2057 unsigned RegNo, 2058 uint64_t Address, 2059 const void *Decoder) { 2060 if (RegNo > 31) 2061 return MCDisassembler::Fail; 2062 2063 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2064 Inst.addOperand(MCOperand::createReg(Reg)); 2065 return MCDisassembler::Success; 2066 } 2067 2068 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2069 unsigned RegNo, 2070 uint64_t Address, 2071 const void *Decoder) { 2072 if (RegNo > 7) 2073 return MCDisassembler::Fail; 2074 2075 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2076 Inst.addOperand(MCOperand::createReg(Reg)); 2077 return MCDisassembler::Success; 2078 } 2079 2080 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2081 unsigned RegNo, 2082 uint64_t Address, 2083 const void *Decoder) { 2084 if (RegNo > 31) 2085 return MCDisassembler::Fail; 2086 2087 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2088 Inst.addOperand(MCOperand::createReg(Reg)); 2089 return MCDisassembler::Success; 2090 } 2091 2092 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2093 unsigned RegNo, 2094 uint64_t Address, 2095 const void *Decoder) { 2096 if (RegNo > 31) 2097 return MCDisassembler::Fail; 2098 2099 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2100 Inst.addOperand(MCOperand::createReg(Reg)); 2101 return MCDisassembler::Success; 2102 } 2103 2104 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2105 unsigned Offset, 2106 uint64_t Address, 2107 const void *Decoder) { 2108 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2109 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2110 return MCDisassembler::Success; 2111 } 2112 2113 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2114 unsigned Offset, 2115 uint64_t Address, 2116 const void *Decoder) { 2117 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2118 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2119 return MCDisassembler::Success; 2120 } 2121 2122 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2123 unsigned Insn, 2124 uint64_t Address, 2125 const void *Decoder) { 2126 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2127 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2128 return MCDisassembler::Success; 2129 } 2130 2131 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2132 unsigned Offset, 2133 uint64_t Address, 2134 const void *Decoder) { 2135 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2136 2137 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2138 return MCDisassembler::Success; 2139 } 2140 2141 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2142 unsigned Offset, 2143 uint64_t Address, 2144 const void *Decoder) { 2145 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2146 2147 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2148 return MCDisassembler::Success; 2149 } 2150 2151 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2152 unsigned Offset, 2153 uint64_t Address, 2154 const void *Decoder) { 2155 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2156 2157 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2158 return MCDisassembler::Success; 2159 } 2160 2161 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2162 unsigned Offset, 2163 uint64_t Address, 2164 const void *Decoder) { 2165 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 2166 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2167 return MCDisassembler::Success; 2168 } 2169 2170 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2171 unsigned Offset, 2172 uint64_t Address, 2173 const void *Decoder) { 2174 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 2175 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2176 return MCDisassembler::Success; 2177 } 2178 2179 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2180 unsigned Offset, 2181 uint64_t Address, 2182 const void *Decoder) { 2183 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2184 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2185 return MCDisassembler::Success; 2186 } 2187 2188 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2189 unsigned Offset, 2190 uint64_t Address, 2191 const void *Decoder) { 2192 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 2193 2194 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2195 return MCDisassembler::Success; 2196 } 2197 2198 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2199 unsigned Insn, 2200 uint64_t Address, 2201 const void *Decoder) { 2202 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2203 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2204 return MCDisassembler::Success; 2205 } 2206 2207 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2208 unsigned Value, 2209 uint64_t Address, 2210 const void *Decoder) { 2211 if (Value == 0) 2212 Inst.addOperand(MCOperand::createImm(1)); 2213 else if (Value == 0x7) 2214 Inst.addOperand(MCOperand::createImm(-1)); 2215 else 2216 Inst.addOperand(MCOperand::createImm(Value << 2)); 2217 return MCDisassembler::Success; 2218 } 2219 2220 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2221 unsigned Value, 2222 uint64_t Address, 2223 const void *Decoder) { 2224 if (Value == 0x7F) 2225 Inst.addOperand(MCOperand::createImm(-1)); 2226 else 2227 Inst.addOperand(MCOperand::createImm(Value)); 2228 return MCDisassembler::Success; 2229 } 2230 2231 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2232 unsigned Value, 2233 uint64_t Address, 2234 const void *Decoder) { 2235 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2236 return MCDisassembler::Success; 2237 } 2238 2239 template <unsigned Bits, int Offset, int Scale> 2240 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2241 uint64_t Address, 2242 const void *Decoder) { 2243 Value &= ((1 << Bits) - 1); 2244 Value *= Scale; 2245 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2246 return MCDisassembler::Success; 2247 } 2248 2249 template <unsigned Bits, int Offset, int ScaleBy> 2250 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2251 uint64_t Address, 2252 const void *Decoder) { 2253 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2254 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2255 return MCDisassembler::Success; 2256 } 2257 2258 static DecodeStatus DecodeInsSize(MCInst &Inst, 2259 unsigned Insn, 2260 uint64_t Address, 2261 const void *Decoder) { 2262 // First we need to grab the pos(lsb) from MCInst. 2263 int Pos = Inst.getOperand(2).getImm(); 2264 if (Inst.getOpcode() == Mips::DINSU) 2265 Pos += 32; 2266 int Size; 2267 if (Inst.getOpcode() == Mips::DINSM || 2268 Inst.getOpcode() == Mips::DINSU) 2269 Size = (int) Insn - Pos + 33; 2270 else 2271 Size = (int) Insn - Pos + 1; 2272 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2273 return MCDisassembler::Success; 2274 } 2275 2276 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2277 uint64_t Address, const void *Decoder) { 2278 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2279 return MCDisassembler::Success; 2280 } 2281 2282 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2283 uint64_t Address, const void *Decoder) { 2284 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2285 return MCDisassembler::Success; 2286 } 2287 2288 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2289 uint64_t Address, const void *Decoder) { 2290 int32_t DecodedValue; 2291 switch (Insn) { 2292 case 0: DecodedValue = 256; break; 2293 case 1: DecodedValue = 257; break; 2294 case 510: DecodedValue = -258; break; 2295 case 511: DecodedValue = -257; break; 2296 default: DecodedValue = SignExtend32<9>(Insn); break; 2297 } 2298 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2299 return MCDisassembler::Success; 2300 } 2301 2302 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2303 uint64_t Address, const void *Decoder) { 2304 // Insn must be >= 0, since it is unsigned that condition is always true. 2305 assert(Insn < 16); 2306 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2307 255, 32768, 65535}; 2308 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2309 return MCDisassembler::Success; 2310 } 2311 2312 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2313 unsigned Insn, 2314 uint64_t Address, 2315 const void *Decoder) { 2316 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2317 Mips::S6, Mips::S7, Mips::FP}; 2318 unsigned RegNum; 2319 2320 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2321 2322 // Empty register lists are not allowed. 2323 if (RegLst == 0) 2324 return MCDisassembler::Fail; 2325 2326 RegNum = RegLst & 0xf; 2327 2328 // RegLst values 10-15, and 26-31 are reserved. 2329 if (RegNum > 9) 2330 return MCDisassembler::Fail; 2331 2332 for (unsigned i = 0; i < RegNum; i++) 2333 Inst.addOperand(MCOperand::createReg(Regs[i])); 2334 2335 if (RegLst & 0x10) 2336 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2337 2338 return MCDisassembler::Success; 2339 } 2340 2341 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2342 uint64_t Address, 2343 const void *Decoder) { 2344 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2345 unsigned RegLst; 2346 switch(Inst.getOpcode()) { 2347 default: 2348 RegLst = fieldFromInstruction(Insn, 4, 2); 2349 break; 2350 case Mips::LWM16_MMR6: 2351 case Mips::SWM16_MMR6: 2352 RegLst = fieldFromInstruction(Insn, 8, 2); 2353 break; 2354 } 2355 unsigned RegNum = RegLst & 0x3; 2356 2357 for (unsigned i = 0; i <= RegNum; i++) 2358 Inst.addOperand(MCOperand::createReg(Regs[i])); 2359 2360 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2361 2362 return MCDisassembler::Success; 2363 } 2364 2365 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2366 uint64_t Address, const void *Decoder) { 2367 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2368 2369 switch (RegPair) { 2370 default: 2371 return MCDisassembler::Fail; 2372 case 0: 2373 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2374 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2375 break; 2376 case 1: 2377 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2378 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2379 break; 2380 case 2: 2381 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2382 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2383 break; 2384 case 3: 2385 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2386 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2387 break; 2388 case 4: 2389 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2390 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2391 break; 2392 case 5: 2393 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2394 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2395 break; 2396 case 6: 2397 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2398 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2399 break; 2400 case 7: 2401 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2402 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2403 break; 2404 } 2405 2406 return MCDisassembler::Success; 2407 } 2408 2409 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2410 uint64_t Address, const void *Decoder) { 2411 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2412 return MCDisassembler::Success; 2413 } 2414 2415 template <typename InsnType> 2416 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2417 uint64_t Address, 2418 const void *Decoder) { 2419 // We have: 2420 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2421 // Invalid if rt == 0 2422 // BGTZALC_MMR6 if rs == 0 && rt != 0 2423 // BLTZALC_MMR6 if rs != 0 && rs == rt 2424 // BLTUC_MMR6 if rs != 0 && rs != rt 2425 2426 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2427 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2428 InsnType Imm = 0; 2429 bool HasRs = false; 2430 bool HasRt = false; 2431 2432 if (Rt == 0) 2433 return MCDisassembler::Fail; 2434 else if (Rs == 0) { 2435 MI.setOpcode(Mips::BGTZALC_MMR6); 2436 HasRt = true; 2437 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2438 } 2439 else if (Rs == Rt) { 2440 MI.setOpcode(Mips::BLTZALC_MMR6); 2441 HasRs = true; 2442 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2443 } 2444 else { 2445 MI.setOpcode(Mips::BLTUC_MMR6); 2446 HasRs = true; 2447 HasRt = true; 2448 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2449 } 2450 2451 if (HasRs) 2452 MI.addOperand( 2453 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2454 2455 if (HasRt) 2456 MI.addOperand( 2457 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2458 2459 MI.addOperand(MCOperand::createImm(Imm)); 2460 2461 return MCDisassembler::Success; 2462 } 2463 2464 template <typename InsnType> 2465 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2466 uint64_t Address, 2467 const void *Decoder) { 2468 // We have: 2469 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2470 // Invalid if rt == 0 2471 // BLEZALC_MMR6 if rs == 0 && rt != 0 2472 // BGEZALC_MMR6 if rs == rt && rt != 0 2473 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2474 2475 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2476 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2477 InsnType Imm = 0; 2478 bool HasRs = false; 2479 2480 if (Rt == 0) 2481 return MCDisassembler::Fail; 2482 else if (Rs == 0) { 2483 MI.setOpcode(Mips::BLEZALC_MMR6); 2484 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2485 } 2486 else if (Rs == Rt) { 2487 MI.setOpcode(Mips::BGEZALC_MMR6); 2488 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2489 } 2490 else { 2491 HasRs = true; 2492 MI.setOpcode(Mips::BGEUC_MMR6); 2493 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2494 } 2495 2496 if (HasRs) 2497 MI.addOperand( 2498 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2499 MI.addOperand( 2500 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2501 2502 MI.addOperand(MCOperand::createImm(Imm)); 2503 2504 return MCDisassembler::Success; 2505 } 2506