1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCTargetDesc.h" 15 #include "Mips.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeMem(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeMemEVA(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const void *Decoder); 287 288 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 289 unsigned Insn, 290 uint64_t Address, 291 const void *Decoder); 292 293 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 294 unsigned Insn, 295 uint64_t Address, 296 const void *Decoder); 297 298 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 299 unsigned Insn, 300 uint64_t Address, 301 const void *Decoder); 302 303 static DecodeStatus DecodeSyncI(MCInst &Inst, 304 unsigned Insn, 305 uint64_t Address, 306 const void *Decoder); 307 308 static DecodeStatus DecodeSynciR6(MCInst &Inst, 309 unsigned Insn, 310 uint64_t Address, 311 const void *Decoder); 312 313 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 316 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 317 unsigned Insn, 318 uint64_t Address, 319 const void *Decoder); 320 321 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 322 unsigned Insn, 323 uint64_t Address, 324 const void *Decoder); 325 326 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 327 unsigned Insn, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 332 unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 337 unsigned Insn, 338 uint64_t Address, 339 const void *Decoder); 340 341 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 342 unsigned Insn, 343 uint64_t Address, 344 const void *Decoder); 345 346 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 347 unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 352 uint64_t Address, 353 const void *Decoder); 354 355 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 356 uint64_t Address, 357 const void *Decoder); 358 359 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 360 const void *Decoder); 361 362 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 368 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 369 uint64_t Address, 370 const void *Decoder); 371 372 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 373 unsigned Insn, 374 uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 378 unsigned Value, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 383 unsigned Value, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 template <unsigned Bits, int Offset, int Scale> 393 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 template <unsigned Bits, int Offset> 398 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 399 uint64_t Address, 400 const void *Decoder) { 401 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 402 Decoder); 403 } 404 405 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 406 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 407 uint64_t Address, 408 const void *Decoder); 409 410 static DecodeStatus DecodeInsSize(MCInst &Inst, 411 unsigned Insn, 412 uint64_t Address, 413 const void *Decoder); 414 415 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 416 uint64_t Address, const void *Decoder); 417 418 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 419 uint64_t Address, const void *Decoder); 420 421 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void *Decoder); 423 424 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void *Decoder); 426 427 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 428 uint64_t Address, const void *Decoder); 429 430 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 431 /// handle. 432 template <typename InsnType> 433 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 434 const void *Decoder); 435 436 template <typename InsnType> 437 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 438 const void *Decoder); 439 440 template <typename InsnType> 441 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 442 const void *Decoder); 443 444 template <typename InsnType> 445 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 446 const void *Decoder); 447 448 template <typename InsnType> 449 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 450 const void *Decoder); 451 452 template <typename InsnType> 453 static DecodeStatus 454 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 455 const void *Decoder); 456 457 template <typename InsnType> 458 static DecodeStatus 459 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus 464 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 465 const void *Decoder); 466 467 template <typename InsnType> 468 static DecodeStatus 469 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 470 const void *Decoder); 471 472 template <typename InsnType> 473 static DecodeStatus 474 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 475 const void *Decoder); 476 477 template <typename InsnType> 478 static DecodeStatus 479 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 480 const void *Decoder); 481 482 template <typename InsnType> 483 static DecodeStatus 484 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 485 const void *Decoder); 486 487 template <typename InsnType> 488 static DecodeStatus 489 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 490 const void *Decoder); 491 492 template <typename InsnType> 493 static DecodeStatus 494 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 495 const void *Decoder); 496 497 template <typename InsnType> 498 static DecodeStatus 499 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 500 const void *Decoder); 501 502 template <typename InsnType> 503 static DecodeStatus 504 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 505 const void *Decoder); 506 507 template <typename InsnType> 508 static DecodeStatus 509 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 510 const void *Decoder); 511 512 template <typename InsnType> 513 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 514 const void *Decoder); 515 516 template <typename InsnType> 517 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 518 const void *Decoder); 519 520 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 521 uint64_t Address, 522 const void *Decoder); 523 524 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 525 uint64_t Address, 526 const void *Decoder); 527 528 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 529 uint64_t Address, 530 const void *Decoder); 531 532 namespace llvm { 533 534 Target &getTheMipselTarget(); 535 Target &getTheMipsTarget(); 536 Target &getTheMips64Target(); 537 Target &getTheMips64elTarget(); 538 539 } // end namespace llvm 540 541 static MCDisassembler *createMipsDisassembler( 542 const Target &T, 543 const MCSubtargetInfo &STI, 544 MCContext &Ctx) { 545 return new MipsDisassembler(STI, Ctx, true); 546 } 547 548 static MCDisassembler *createMipselDisassembler( 549 const Target &T, 550 const MCSubtargetInfo &STI, 551 MCContext &Ctx) { 552 return new MipsDisassembler(STI, Ctx, false); 553 } 554 555 extern "C" void LLVMInitializeMipsDisassembler() { 556 // Register the disassembler. 557 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 558 createMipsDisassembler); 559 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 560 createMipselDisassembler); 561 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 562 createMipsDisassembler); 563 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 564 createMipselDisassembler); 565 } 566 567 #include "MipsGenDisassemblerTables.inc" 568 569 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 570 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 571 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 572 return *(RegInfo->getRegClass(RC).begin() + RegNo); 573 } 574 575 template <typename InsnType> 576 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 577 const void *Decoder) { 578 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 579 580 // The size of the n field depends on the element size 581 // The register class also depends on this. 582 InsnType tmp = fieldFromInstruction(insn, 17, 5); 583 unsigned NSize = 0; 584 DecodeFN RegDecoder = nullptr; 585 if ((tmp & 0x18) == 0x00) { // INSVE_B 586 NSize = 4; 587 RegDecoder = DecodeMSA128BRegisterClass; 588 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 589 NSize = 3; 590 RegDecoder = DecodeMSA128HRegisterClass; 591 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 592 NSize = 2; 593 RegDecoder = DecodeMSA128WRegisterClass; 594 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 595 NSize = 1; 596 RegDecoder = DecodeMSA128DRegisterClass; 597 } else 598 llvm_unreachable("Invalid encoding"); 599 600 assert(NSize != 0 && RegDecoder != nullptr); 601 602 // $wd 603 tmp = fieldFromInstruction(insn, 6, 5); 604 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 605 return MCDisassembler::Fail; 606 // $wd_in 607 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 608 return MCDisassembler::Fail; 609 // $n 610 tmp = fieldFromInstruction(insn, 16, NSize); 611 MI.addOperand(MCOperand::createImm(tmp)); 612 // $ws 613 tmp = fieldFromInstruction(insn, 11, 5); 614 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 615 return MCDisassembler::Fail; 616 // $n2 617 MI.addOperand(MCOperand::createImm(0)); 618 619 return MCDisassembler::Success; 620 } 621 622 template <typename InsnType> 623 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 624 const void *Decoder) { 625 InsnType Rs = fieldFromInstruction(insn, 16, 5); 626 InsnType Imm = fieldFromInstruction(insn, 0, 16); 627 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 628 Rs))); 629 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 630 Rs))); 631 MI.addOperand(MCOperand::createImm(Imm)); 632 633 return MCDisassembler::Success; 634 } 635 636 template <typename InsnType> 637 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 638 const void *Decoder) { 639 InsnType Rs = fieldFromInstruction(insn, 21, 5); 640 InsnType Imm = fieldFromInstruction(insn, 0, 16); 641 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 642 Rs))); 643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 644 Rs))); 645 MI.addOperand(MCOperand::createImm(Imm)); 646 647 return MCDisassembler::Success; 648 } 649 650 template <typename InsnType> 651 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 652 uint64_t Address, 653 const void *Decoder) { 654 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 655 // (otherwise we would have matched the ADDI instruction from the earlier 656 // ISA's instead). 657 // 658 // We have: 659 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 660 // BOVC if rs >= rt 661 // BEQZALC if rs == 0 && rt != 0 662 // BEQC if rs < rt && rs != 0 663 664 InsnType Rs = fieldFromInstruction(insn, 21, 5); 665 InsnType Rt = fieldFromInstruction(insn, 16, 5); 666 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 667 bool HasRs = false; 668 669 if (Rs >= Rt) { 670 MI.setOpcode(Mips::BOVC); 671 HasRs = true; 672 } else if (Rs != 0 && Rs < Rt) { 673 MI.setOpcode(Mips::BEQC); 674 HasRs = true; 675 } else 676 MI.setOpcode(Mips::BEQZALC); 677 678 if (HasRs) 679 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 680 Rs))); 681 682 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 683 Rt))); 684 MI.addOperand(MCOperand::createImm(Imm)); 685 686 return MCDisassembler::Success; 687 } 688 689 template <typename InsnType> 690 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 691 uint64_t Address, 692 const void *Decoder) { 693 InsnType Rt = fieldFromInstruction(insn, 21, 5); 694 InsnType Rs = fieldFromInstruction(insn, 16, 5); 695 int64_t Imm = 0; 696 697 if (Rs >= Rt) { 698 MI.setOpcode(Mips::BOVC_MMR6); 699 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 700 Rt))); 701 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 702 Rs))); 703 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 704 } else if (Rs != 0 && Rs < Rt) { 705 MI.setOpcode(Mips::BEQC_MMR6); 706 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 707 Rs))); 708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 709 Rt))); 710 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 711 } else { 712 MI.setOpcode(Mips::BEQZALC_MMR6); 713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 714 Rt))); 715 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 716 } 717 718 MI.addOperand(MCOperand::createImm(Imm)); 719 720 return MCDisassembler::Success; 721 } 722 723 template <typename InsnType> 724 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 725 uint64_t Address, 726 const void *Decoder) { 727 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 728 // (otherwise we would have matched the ADDI instruction from the earlier 729 // ISA's instead). 730 // 731 // We have: 732 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 733 // BNVC if rs >= rt 734 // BNEZALC if rs == 0 && rt != 0 735 // BNEC if rs < rt && rs != 0 736 737 InsnType Rs = fieldFromInstruction(insn, 21, 5); 738 InsnType Rt = fieldFromInstruction(insn, 16, 5); 739 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 740 bool HasRs = false; 741 742 if (Rs >= Rt) { 743 MI.setOpcode(Mips::BNVC); 744 HasRs = true; 745 } else if (Rs != 0 && Rs < Rt) { 746 MI.setOpcode(Mips::BNEC); 747 HasRs = true; 748 } else 749 MI.setOpcode(Mips::BNEZALC); 750 751 if (HasRs) 752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 753 Rs))); 754 755 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 756 Rt))); 757 MI.addOperand(MCOperand::createImm(Imm)); 758 759 return MCDisassembler::Success; 760 } 761 762 template <typename InsnType> 763 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 764 uint64_t Address, 765 const void *Decoder) { 766 InsnType Rt = fieldFromInstruction(insn, 21, 5); 767 InsnType Rs = fieldFromInstruction(insn, 16, 5); 768 int64_t Imm = 0; 769 770 if (Rs >= Rt) { 771 MI.setOpcode(Mips::BNVC_MMR6); 772 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 773 Rt))); 774 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 775 Rs))); 776 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 777 } else if (Rs != 0 && Rs < Rt) { 778 MI.setOpcode(Mips::BNEC_MMR6); 779 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 780 Rs))); 781 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 782 Rt))); 783 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 784 } else { 785 MI.setOpcode(Mips::BNEZALC_MMR6); 786 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 787 Rt))); 788 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 789 } 790 791 MI.addOperand(MCOperand::createImm(Imm)); 792 793 return MCDisassembler::Success; 794 } 795 796 template <typename InsnType> 797 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 798 uint64_t Address, 799 const void *Decoder) { 800 // We have: 801 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 802 // Invalid if rt == 0 803 // BGTZC_MMR6 if rs == 0 && rt != 0 804 // BLTZC_MMR6 if rs == rt && rt != 0 805 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 806 807 InsnType Rt = fieldFromInstruction(insn, 21, 5); 808 InsnType Rs = fieldFromInstruction(insn, 16, 5); 809 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 810 bool HasRs = false; 811 812 if (Rt == 0) 813 return MCDisassembler::Fail; 814 else if (Rs == 0) 815 MI.setOpcode(Mips::BGTZC_MMR6); 816 else if (Rs == Rt) 817 MI.setOpcode(Mips::BLTZC_MMR6); 818 else { 819 MI.setOpcode(Mips::BLTC_MMR6); 820 HasRs = true; 821 } 822 823 if (HasRs) 824 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 825 Rs))); 826 827 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 828 Rt))); 829 830 MI.addOperand(MCOperand::createImm(Imm)); 831 832 return MCDisassembler::Success; 833 } 834 835 template <typename InsnType> 836 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 837 uint64_t Address, 838 const void *Decoder) { 839 // We have: 840 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 841 // Invalid if rt == 0 842 // BLEZC_MMR6 if rs == 0 && rt != 0 843 // BGEZC_MMR6 if rs == rt && rt != 0 844 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 845 846 InsnType Rt = fieldFromInstruction(insn, 21, 5); 847 InsnType Rs = fieldFromInstruction(insn, 16, 5); 848 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 849 bool HasRs = false; 850 851 if (Rt == 0) 852 return MCDisassembler::Fail; 853 else if (Rs == 0) 854 MI.setOpcode(Mips::BLEZC_MMR6); 855 else if (Rs == Rt) 856 MI.setOpcode(Mips::BGEZC_MMR6); 857 else { 858 HasRs = true; 859 MI.setOpcode(Mips::BGEC_MMR6); 860 } 861 862 if (HasRs) 863 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 864 Rs))); 865 866 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 867 Rt))); 868 869 MI.addOperand(MCOperand::createImm(Imm)); 870 871 return MCDisassembler::Success; 872 } 873 874 template <typename InsnType> 875 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 876 uint64_t Address, 877 const void *Decoder) { 878 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 879 // (otherwise we would have matched the BLEZL instruction from the earlier 880 // ISA's instead). 881 // 882 // We have: 883 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 884 // Invalid if rs == 0 885 // BLEZC if rs == 0 && rt != 0 886 // BGEZC if rs == rt && rt != 0 887 // BGEC if rs != rt && rs != 0 && rt != 0 888 889 InsnType Rs = fieldFromInstruction(insn, 21, 5); 890 InsnType Rt = fieldFromInstruction(insn, 16, 5); 891 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 892 bool HasRs = false; 893 894 if (Rt == 0) 895 return MCDisassembler::Fail; 896 else if (Rs == 0) 897 MI.setOpcode(Mips::BLEZC); 898 else if (Rs == Rt) 899 MI.setOpcode(Mips::BGEZC); 900 else { 901 HasRs = true; 902 MI.setOpcode(Mips::BGEC); 903 } 904 905 if (HasRs) 906 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 907 Rs))); 908 909 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 910 Rt))); 911 912 MI.addOperand(MCOperand::createImm(Imm)); 913 914 return MCDisassembler::Success; 915 } 916 917 template <typename InsnType> 918 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 919 uint64_t Address, 920 const void *Decoder) { 921 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 922 // (otherwise we would have matched the BGTZL instruction from the earlier 923 // ISA's instead). 924 // 925 // We have: 926 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 927 // Invalid if rs == 0 928 // BGTZC if rs == 0 && rt != 0 929 // BLTZC if rs == rt && rt != 0 930 // BLTC if rs != rt && rs != 0 && rt != 0 931 932 bool HasRs = false; 933 934 InsnType Rs = fieldFromInstruction(insn, 21, 5); 935 InsnType Rt = fieldFromInstruction(insn, 16, 5); 936 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 937 938 if (Rt == 0) 939 return MCDisassembler::Fail; 940 else if (Rs == 0) 941 MI.setOpcode(Mips::BGTZC); 942 else if (Rs == Rt) 943 MI.setOpcode(Mips::BLTZC); 944 else { 945 MI.setOpcode(Mips::BLTC); 946 HasRs = true; 947 } 948 949 if (HasRs) 950 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 951 Rs))); 952 953 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 954 Rt))); 955 956 MI.addOperand(MCOperand::createImm(Imm)); 957 958 return MCDisassembler::Success; 959 } 960 961 template <typename InsnType> 962 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 963 uint64_t Address, 964 const void *Decoder) { 965 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 966 // (otherwise we would have matched the BGTZ instruction from the earlier 967 // ISA's instead). 968 // 969 // We have: 970 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 971 // BGTZ if rt == 0 972 // BGTZALC if rs == 0 && rt != 0 973 // BLTZALC if rs != 0 && rs == rt 974 // BLTUC if rs != 0 && rs != rt 975 976 InsnType Rs = fieldFromInstruction(insn, 21, 5); 977 InsnType Rt = fieldFromInstruction(insn, 16, 5); 978 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 979 bool HasRs = false; 980 bool HasRt = false; 981 982 if (Rt == 0) { 983 MI.setOpcode(Mips::BGTZ); 984 HasRs = true; 985 } else if (Rs == 0) { 986 MI.setOpcode(Mips::BGTZALC); 987 HasRt = true; 988 } else if (Rs == Rt) { 989 MI.setOpcode(Mips::BLTZALC); 990 HasRs = true; 991 } else { 992 MI.setOpcode(Mips::BLTUC); 993 HasRs = true; 994 HasRt = true; 995 } 996 997 if (HasRs) 998 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 999 Rs))); 1000 1001 if (HasRt) 1002 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1003 Rt))); 1004 1005 MI.addOperand(MCOperand::createImm(Imm)); 1006 1007 return MCDisassembler::Success; 1008 } 1009 1010 template <typename InsnType> 1011 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1012 uint64_t Address, 1013 const void *Decoder) { 1014 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1015 // (otherwise we would have matched the BLEZL instruction from the earlier 1016 // ISA's instead). 1017 // 1018 // We have: 1019 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1020 // Invalid if rs == 0 1021 // BLEZALC if rs == 0 && rt != 0 1022 // BGEZALC if rs == rt && rt != 0 1023 // BGEUC if rs != rt && rs != 0 && rt != 0 1024 1025 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1026 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1027 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1028 bool HasRs = false; 1029 1030 if (Rt == 0) 1031 return MCDisassembler::Fail; 1032 else if (Rs == 0) 1033 MI.setOpcode(Mips::BLEZALC); 1034 else if (Rs == Rt) 1035 MI.setOpcode(Mips::BGEZALC); 1036 else { 1037 HasRs = true; 1038 MI.setOpcode(Mips::BGEUC); 1039 } 1040 1041 if (HasRs) 1042 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1043 Rs))); 1044 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1045 Rt))); 1046 1047 MI.addOperand(MCOperand::createImm(Imm)); 1048 1049 return MCDisassembler::Success; 1050 } 1051 1052 // Override the generated disassembler to produce DEXT all the time. This is 1053 // for feature / behaviour parity with binutils. 1054 template <typename InsnType> 1055 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1056 const void *Decoder) { 1057 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1058 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1059 unsigned Size = 0; 1060 unsigned Pos = 0; 1061 1062 switch (MI.getOpcode()) { 1063 case Mips::DEXT: 1064 Pos = Lsb; 1065 Size = Msbd + 1; 1066 break; 1067 case Mips::DEXTM: 1068 Pos = Lsb; 1069 Size = Msbd + 1 + 32; 1070 break; 1071 case Mips::DEXTU: 1072 Pos = Lsb + 32; 1073 Size = Msbd + 1; 1074 break; 1075 default: 1076 llvm_unreachable("Unknown DEXT instruction!"); 1077 } 1078 1079 MI.setOpcode(Mips::DEXT); 1080 1081 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1082 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1083 1084 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1085 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1086 MI.addOperand(MCOperand::createImm(Pos)); 1087 MI.addOperand(MCOperand::createImm(Size)); 1088 1089 return MCDisassembler::Success; 1090 } 1091 1092 // Override the generated disassembler to produce DINS all the time. This is 1093 // for feature / behaviour parity with binutils. 1094 template <typename InsnType> 1095 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1096 const void *Decoder) { 1097 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1098 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1099 unsigned Size = 0; 1100 unsigned Pos = 0; 1101 1102 switch (MI.getOpcode()) { 1103 case Mips::DINS: 1104 Pos = Lsb; 1105 Size = Msbd + 1 - Pos; 1106 break; 1107 case Mips::DINSM: 1108 Pos = Lsb; 1109 Size = Msbd + 33 - Pos; 1110 break; 1111 case Mips::DINSU: 1112 Pos = Lsb + 32; 1113 // mbsd = pos + size - 33 1114 // mbsd - pos + 33 = size 1115 Size = Msbd + 33 - Pos; 1116 break; 1117 default: 1118 llvm_unreachable("Unknown DINS instruction!"); 1119 } 1120 1121 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1122 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1123 1124 MI.setOpcode(Mips::DINS); 1125 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1126 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1127 MI.addOperand(MCOperand::createImm(Pos)); 1128 MI.addOperand(MCOperand::createImm(Size)); 1129 1130 return MCDisassembler::Success; 1131 } 1132 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1133 /// according to the given endianness. 1134 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1135 uint64_t &Size, uint32_t &Insn, 1136 bool IsBigEndian) { 1137 // We want to read exactly 2 Bytes of data. 1138 if (Bytes.size() < 2) { 1139 Size = 0; 1140 return MCDisassembler::Fail; 1141 } 1142 1143 if (IsBigEndian) { 1144 Insn = (Bytes[0] << 8) | Bytes[1]; 1145 } else { 1146 Insn = (Bytes[1] << 8) | Bytes[0]; 1147 } 1148 1149 return MCDisassembler::Success; 1150 } 1151 1152 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1153 /// according to the given endianness. 1154 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1155 uint64_t &Size, uint32_t &Insn, 1156 bool IsBigEndian, bool IsMicroMips) { 1157 // We want to read exactly 4 Bytes of data. 1158 if (Bytes.size() < 4) { 1159 Size = 0; 1160 return MCDisassembler::Fail; 1161 } 1162 1163 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1164 // always precede the low 16 bits in the instruction stream (that is, they 1165 // are placed at lower addresses in the instruction stream). 1166 // 1167 // microMIPS byte ordering: 1168 // Big-endian: 0 | 1 | 2 | 3 1169 // Little-endian: 1 | 0 | 3 | 2 1170 1171 if (IsBigEndian) { 1172 // Encoded as a big-endian 32-bit word in the stream. 1173 Insn = 1174 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1175 } else { 1176 if (IsMicroMips) { 1177 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1178 (Bytes[1] << 24); 1179 } else { 1180 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1181 (Bytes[3] << 24); 1182 } 1183 } 1184 1185 return MCDisassembler::Success; 1186 } 1187 1188 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1189 ArrayRef<uint8_t> Bytes, 1190 uint64_t Address, 1191 raw_ostream &VStream, 1192 raw_ostream &CStream) const { 1193 uint32_t Insn; 1194 DecodeStatus Result; 1195 Size = 0; 1196 1197 if (IsMicroMips) { 1198 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1199 if (Result == MCDisassembler::Fail) 1200 return MCDisassembler::Fail; 1201 1202 if (hasMips32r6()) { 1203 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1204 // Calling the auto-generated decoder function for microMIPS32R6 1205 // 16-bit instructions. 1206 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1207 Address, this, STI); 1208 if (Result != MCDisassembler::Fail) { 1209 Size = 2; 1210 return Result; 1211 } 1212 } 1213 1214 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1215 // Calling the auto-generated decoder function for microMIPS 16-bit 1216 // instructions. 1217 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1218 this, STI); 1219 if (Result != MCDisassembler::Fail) { 1220 Size = 2; 1221 return Result; 1222 } 1223 1224 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1225 if (Result == MCDisassembler::Fail) 1226 return MCDisassembler::Fail; 1227 1228 if (hasMips32r6()) { 1229 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1230 // Calling the auto-generated decoder function. 1231 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1232 this, STI); 1233 if (Result != MCDisassembler::Fail) { 1234 Size = 4; 1235 return Result; 1236 } 1237 } 1238 1239 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1240 // Calling the auto-generated decoder function. 1241 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1242 this, STI); 1243 if (Result != MCDisassembler::Fail) { 1244 Size = 4; 1245 return Result; 1246 } 1247 1248 if (isFP64()) { 1249 DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1250 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1251 Address, this, STI); 1252 if (Result != MCDisassembler::Fail) { 1253 Size = 4; 1254 return Result; 1255 } 1256 } 1257 1258 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1259 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1260 // could form a valid instruction. The two bytes we rejected as an 1261 // instruction could have actually beeen an inline constant pool that is 1262 // unconditionally branched over. 1263 Size = 2; 1264 return MCDisassembler::Fail; 1265 } 1266 1267 // Attempt to read the instruction so that we can attempt to decode it. If 1268 // the buffer is not 4 bytes long, let the higher level logic figure out 1269 // what to do with a size of zero and MCDisassembler::Fail. 1270 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1271 if (Result == MCDisassembler::Fail) 1272 return MCDisassembler::Fail; 1273 1274 // The only instruction size for standard encoded MIPS. 1275 Size = 4; 1276 1277 if (hasCOP3()) { 1278 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1279 Result = 1280 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1281 if (Result != MCDisassembler::Fail) 1282 return Result; 1283 } 1284 1285 if (hasMips32r6() && isGP64()) { 1286 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1287 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1288 Address, this, STI); 1289 if (Result != MCDisassembler::Fail) 1290 return Result; 1291 } 1292 1293 if (hasMips32r6() && isPTR64()) { 1294 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1295 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1296 Address, this, STI); 1297 if (Result != MCDisassembler::Fail) 1298 return Result; 1299 } 1300 1301 if (hasMips32r6()) { 1302 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1303 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1304 Address, this, STI); 1305 if (Result != MCDisassembler::Fail) 1306 return Result; 1307 } 1308 1309 if (hasMips2() && isPTR64()) { 1310 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1311 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1312 Address, this, STI); 1313 if (Result != MCDisassembler::Fail) 1314 return Result; 1315 } 1316 1317 if (hasCnMips()) { 1318 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1319 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1320 Address, this, STI); 1321 if (Result != MCDisassembler::Fail) 1322 return Result; 1323 } 1324 1325 if (isGP64()) { 1326 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1327 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1328 Address, this, STI); 1329 if (Result != MCDisassembler::Fail) 1330 return Result; 1331 } 1332 1333 if (isFP64()) { 1334 DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1335 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1336 Address, this, STI); 1337 if (Result != MCDisassembler::Fail) 1338 return Result; 1339 } 1340 1341 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1342 // Calling the auto-generated decoder function. 1343 Result = 1344 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1345 if (Result != MCDisassembler::Fail) 1346 return Result; 1347 1348 return MCDisassembler::Fail; 1349 } 1350 1351 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1352 unsigned RegNo, 1353 uint64_t Address, 1354 const void *Decoder) { 1355 return MCDisassembler::Fail; 1356 } 1357 1358 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1359 unsigned RegNo, 1360 uint64_t Address, 1361 const void *Decoder) { 1362 if (RegNo > 31) 1363 return MCDisassembler::Fail; 1364 1365 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1366 Inst.addOperand(MCOperand::createReg(Reg)); 1367 return MCDisassembler::Success; 1368 } 1369 1370 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1371 unsigned RegNo, 1372 uint64_t Address, 1373 const void *Decoder) { 1374 if (RegNo > 7) 1375 return MCDisassembler::Fail; 1376 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1377 Inst.addOperand(MCOperand::createReg(Reg)); 1378 return MCDisassembler::Success; 1379 } 1380 1381 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1382 unsigned RegNo, 1383 uint64_t Address, 1384 const void *Decoder) { 1385 if (RegNo > 7) 1386 return MCDisassembler::Fail; 1387 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1388 Inst.addOperand(MCOperand::createReg(Reg)); 1389 return MCDisassembler::Success; 1390 } 1391 1392 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1393 unsigned RegNo, 1394 uint64_t Address, 1395 const void *Decoder) { 1396 if (RegNo > 7) 1397 return MCDisassembler::Fail; 1398 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1399 Inst.addOperand(MCOperand::createReg(Reg)); 1400 return MCDisassembler::Success; 1401 } 1402 1403 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1404 unsigned RegNo, 1405 uint64_t Address, 1406 const void *Decoder) { 1407 if (RegNo > 31) 1408 return MCDisassembler::Fail; 1409 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1410 Inst.addOperand(MCOperand::createReg(Reg)); 1411 return MCDisassembler::Success; 1412 } 1413 1414 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1415 unsigned RegNo, 1416 uint64_t Address, 1417 const void *Decoder) { 1418 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1419 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1420 1421 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1422 } 1423 1424 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1425 unsigned RegNo, 1426 uint64_t Address, 1427 const void *Decoder) { 1428 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1429 } 1430 1431 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1432 unsigned RegNo, 1433 uint64_t Address, 1434 const void *Decoder) { 1435 if (RegNo > 31) 1436 return MCDisassembler::Fail; 1437 1438 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1439 Inst.addOperand(MCOperand::createReg(Reg)); 1440 return MCDisassembler::Success; 1441 } 1442 1443 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1444 unsigned RegNo, 1445 uint64_t Address, 1446 const void *Decoder) { 1447 if (RegNo > 31) 1448 return MCDisassembler::Fail; 1449 1450 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1451 Inst.addOperand(MCOperand::createReg(Reg)); 1452 return MCDisassembler::Success; 1453 } 1454 1455 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1456 unsigned RegNo, 1457 uint64_t Address, 1458 const void *Decoder) { 1459 if (RegNo > 31) 1460 return MCDisassembler::Fail; 1461 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1462 Inst.addOperand(MCOperand::createReg(Reg)); 1463 return MCDisassembler::Success; 1464 } 1465 1466 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1467 unsigned RegNo, 1468 uint64_t Address, 1469 const void *Decoder) { 1470 if (RegNo > 7) 1471 return MCDisassembler::Fail; 1472 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1473 Inst.addOperand(MCOperand::createReg(Reg)); 1474 return MCDisassembler::Success; 1475 } 1476 1477 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1478 uint64_t Address, 1479 const void *Decoder) { 1480 if (RegNo > 31) 1481 return MCDisassembler::Fail; 1482 1483 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1484 Inst.addOperand(MCOperand::createReg(Reg)); 1485 return MCDisassembler::Success; 1486 } 1487 1488 static DecodeStatus DecodeMem(MCInst &Inst, 1489 unsigned Insn, 1490 uint64_t Address, 1491 const void *Decoder) { 1492 int Offset = SignExtend32<16>(Insn & 0xffff); 1493 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1494 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1495 1496 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1497 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1498 1499 if (Inst.getOpcode() == Mips::SC || 1500 Inst.getOpcode() == Mips::SCD) 1501 Inst.addOperand(MCOperand::createReg(Reg)); 1502 1503 Inst.addOperand(MCOperand::createReg(Reg)); 1504 Inst.addOperand(MCOperand::createReg(Base)); 1505 Inst.addOperand(MCOperand::createImm(Offset)); 1506 1507 return MCDisassembler::Success; 1508 } 1509 1510 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1511 unsigned Insn, 1512 uint64_t Address, 1513 const void *Decoder) { 1514 int Offset = SignExtend32<9>(Insn >> 7); 1515 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1516 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1517 1518 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1519 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1520 1521 if (Inst.getOpcode() == Mips::SCE) 1522 Inst.addOperand(MCOperand::createReg(Reg)); 1523 1524 Inst.addOperand(MCOperand::createReg(Reg)); 1525 Inst.addOperand(MCOperand::createReg(Base)); 1526 Inst.addOperand(MCOperand::createImm(Offset)); 1527 1528 return MCDisassembler::Success; 1529 } 1530 1531 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1532 unsigned Insn, 1533 uint64_t Address, 1534 const void *Decoder) { 1535 int Offset = SignExtend32<16>(Insn & 0xffff); 1536 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1537 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1538 1539 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1540 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1541 1542 Inst.addOperand(MCOperand::createReg(Reg)); 1543 Inst.addOperand(MCOperand::createReg(Base)); 1544 Inst.addOperand(MCOperand::createImm(Offset)); 1545 1546 return MCDisassembler::Success; 1547 } 1548 1549 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1550 unsigned Insn, 1551 uint64_t Address, 1552 const void *Decoder) { 1553 int Offset = SignExtend32<16>(Insn & 0xffff); 1554 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1555 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1556 1557 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1558 1559 Inst.addOperand(MCOperand::createReg(Base)); 1560 Inst.addOperand(MCOperand::createImm(Offset)); 1561 Inst.addOperand(MCOperand::createImm(Hint)); 1562 1563 return MCDisassembler::Success; 1564 } 1565 1566 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1567 unsigned Insn, 1568 uint64_t Address, 1569 const void *Decoder) { 1570 int Offset = SignExtend32<12>(Insn & 0xfff); 1571 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1572 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1573 1574 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1575 1576 Inst.addOperand(MCOperand::createReg(Base)); 1577 Inst.addOperand(MCOperand::createImm(Offset)); 1578 Inst.addOperand(MCOperand::createImm(Hint)); 1579 1580 return MCDisassembler::Success; 1581 } 1582 1583 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1584 unsigned Insn, 1585 uint64_t Address, 1586 const void *Decoder) { 1587 int Offset = SignExtend32<9>(Insn & 0x1ff); 1588 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1589 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1590 1591 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1592 1593 Inst.addOperand(MCOperand::createReg(Base)); 1594 Inst.addOperand(MCOperand::createImm(Offset)); 1595 Inst.addOperand(MCOperand::createImm(Hint)); 1596 1597 return MCDisassembler::Success; 1598 } 1599 1600 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1601 unsigned Insn, 1602 uint64_t Address, 1603 const void *Decoder) { 1604 int Offset = SignExtend32<9>(Insn >> 7); 1605 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1606 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1607 1608 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1609 1610 Inst.addOperand(MCOperand::createReg(Base)); 1611 Inst.addOperand(MCOperand::createImm(Offset)); 1612 Inst.addOperand(MCOperand::createImm(Hint)); 1613 1614 return MCDisassembler::Success; 1615 } 1616 1617 static DecodeStatus DecodeSyncI(MCInst &Inst, 1618 unsigned Insn, 1619 uint64_t Address, 1620 const void *Decoder) { 1621 int Offset = SignExtend32<16>(Insn & 0xffff); 1622 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1623 1624 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1625 1626 Inst.addOperand(MCOperand::createReg(Base)); 1627 Inst.addOperand(MCOperand::createImm(Offset)); 1628 1629 return MCDisassembler::Success; 1630 } 1631 1632 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1633 unsigned Insn, 1634 uint64_t Address, 1635 const void *Decoder) { 1636 int Immediate = SignExtend32<16>(Insn & 0xffff); 1637 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1638 1639 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1640 1641 Inst.addOperand(MCOperand::createReg(Base)); 1642 Inst.addOperand(MCOperand::createImm(Immediate)); 1643 1644 return MCDisassembler::Success; 1645 } 1646 1647 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1648 uint64_t Address, const void *Decoder) { 1649 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1650 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1651 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1652 1653 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1654 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1655 1656 Inst.addOperand(MCOperand::createReg(Reg)); 1657 Inst.addOperand(MCOperand::createReg(Base)); 1658 1659 // The immediate field of an LD/ST instruction is scaled which means it must 1660 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1661 // data format. 1662 // .b - 1 byte 1663 // .h - 2 bytes 1664 // .w - 4 bytes 1665 // .d - 8 bytes 1666 switch(Inst.getOpcode()) 1667 { 1668 default: 1669 assert(false && "Unexpected instruction"); 1670 return MCDisassembler::Fail; 1671 break; 1672 case Mips::LD_B: 1673 case Mips::ST_B: 1674 Inst.addOperand(MCOperand::createImm(Offset)); 1675 break; 1676 case Mips::LD_H: 1677 case Mips::ST_H: 1678 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1679 break; 1680 case Mips::LD_W: 1681 case Mips::ST_W: 1682 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1683 break; 1684 case Mips::LD_D: 1685 case Mips::ST_D: 1686 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1687 break; 1688 } 1689 1690 return MCDisassembler::Success; 1691 } 1692 1693 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1694 unsigned Insn, 1695 uint64_t Address, 1696 const void *Decoder) { 1697 unsigned Offset = Insn & 0xf; 1698 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1699 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1700 1701 switch (Inst.getOpcode()) { 1702 case Mips::LBU16_MM: 1703 case Mips::LHU16_MM: 1704 case Mips::LW16_MM: 1705 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1706 == MCDisassembler::Fail) 1707 return MCDisassembler::Fail; 1708 break; 1709 case Mips::SB16_MM: 1710 case Mips::SB16_MMR6: 1711 case Mips::SH16_MM: 1712 case Mips::SH16_MMR6: 1713 case Mips::SW16_MM: 1714 case Mips::SW16_MMR6: 1715 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1716 == MCDisassembler::Fail) 1717 return MCDisassembler::Fail; 1718 break; 1719 } 1720 1721 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1722 == MCDisassembler::Fail) 1723 return MCDisassembler::Fail; 1724 1725 switch (Inst.getOpcode()) { 1726 case Mips::LBU16_MM: 1727 if (Offset == 0xf) 1728 Inst.addOperand(MCOperand::createImm(-1)); 1729 else 1730 Inst.addOperand(MCOperand::createImm(Offset)); 1731 break; 1732 case Mips::SB16_MM: 1733 case Mips::SB16_MMR6: 1734 Inst.addOperand(MCOperand::createImm(Offset)); 1735 break; 1736 case Mips::LHU16_MM: 1737 case Mips::SH16_MM: 1738 case Mips::SH16_MMR6: 1739 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1740 break; 1741 case Mips::LW16_MM: 1742 case Mips::SW16_MM: 1743 case Mips::SW16_MMR6: 1744 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1745 break; 1746 } 1747 1748 return MCDisassembler::Success; 1749 } 1750 1751 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1752 unsigned Insn, 1753 uint64_t Address, 1754 const void *Decoder) { 1755 unsigned Offset = Insn & 0x1F; 1756 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1757 1758 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1759 1760 Inst.addOperand(MCOperand::createReg(Reg)); 1761 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1762 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1763 1764 return MCDisassembler::Success; 1765 } 1766 1767 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1768 unsigned Insn, 1769 uint64_t Address, 1770 const void *Decoder) { 1771 unsigned Offset = Insn & 0x7F; 1772 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1773 1774 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1775 1776 Inst.addOperand(MCOperand::createReg(Reg)); 1777 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1778 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1779 1780 return MCDisassembler::Success; 1781 } 1782 1783 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1784 unsigned Insn, 1785 uint64_t Address, 1786 const void *Decoder) { 1787 int Offset; 1788 switch (Inst.getOpcode()) { 1789 case Mips::LWM16_MMR6: 1790 case Mips::SWM16_MMR6: 1791 Offset = fieldFromInstruction(Insn, 4, 4); 1792 break; 1793 default: 1794 Offset = SignExtend32<4>(Insn & 0xf); 1795 break; 1796 } 1797 1798 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1799 == MCDisassembler::Fail) 1800 return MCDisassembler::Fail; 1801 1802 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1803 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1804 1805 return MCDisassembler::Success; 1806 } 1807 1808 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1809 unsigned Insn, 1810 uint64_t Address, 1811 const void *Decoder) { 1812 int Offset = SignExtend32<9>(Insn & 0x1ff); 1813 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1814 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1815 1816 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1817 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1818 1819 if (Inst.getOpcode() == Mips::SCE_MM) 1820 Inst.addOperand(MCOperand::createReg(Reg)); 1821 1822 Inst.addOperand(MCOperand::createReg(Reg)); 1823 Inst.addOperand(MCOperand::createReg(Base)); 1824 Inst.addOperand(MCOperand::createImm(Offset)); 1825 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1830 unsigned Insn, 1831 uint64_t Address, 1832 const void *Decoder) { 1833 int Offset = SignExtend32<12>(Insn & 0x0fff); 1834 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1835 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1836 1837 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1838 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1839 1840 switch (Inst.getOpcode()) { 1841 case Mips::SWM32_MM: 1842 case Mips::LWM32_MM: 1843 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1844 == MCDisassembler::Fail) 1845 return MCDisassembler::Fail; 1846 Inst.addOperand(MCOperand::createReg(Base)); 1847 Inst.addOperand(MCOperand::createImm(Offset)); 1848 break; 1849 case Mips::SC_MM: 1850 Inst.addOperand(MCOperand::createReg(Reg)); 1851 LLVM_FALLTHROUGH; 1852 default: 1853 Inst.addOperand(MCOperand::createReg(Reg)); 1854 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1855 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1856 Inst.addOperand(MCOperand::createReg(Reg+1)); 1857 1858 Inst.addOperand(MCOperand::createReg(Base)); 1859 Inst.addOperand(MCOperand::createImm(Offset)); 1860 } 1861 1862 return MCDisassembler::Success; 1863 } 1864 1865 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1866 unsigned Insn, 1867 uint64_t Address, 1868 const void *Decoder) { 1869 int Offset = SignExtend32<16>(Insn & 0xffff); 1870 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1871 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1872 1873 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1874 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1875 1876 Inst.addOperand(MCOperand::createReg(Reg)); 1877 Inst.addOperand(MCOperand::createReg(Base)); 1878 Inst.addOperand(MCOperand::createImm(Offset)); 1879 1880 return MCDisassembler::Success; 1881 } 1882 1883 static DecodeStatus DecodeFMem(MCInst &Inst, 1884 unsigned Insn, 1885 uint64_t Address, 1886 const void *Decoder) { 1887 int Offset = SignExtend32<16>(Insn & 0xffff); 1888 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1889 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1890 1891 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1892 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1893 1894 Inst.addOperand(MCOperand::createReg(Reg)); 1895 Inst.addOperand(MCOperand::createReg(Base)); 1896 Inst.addOperand(MCOperand::createImm(Offset)); 1897 1898 return MCDisassembler::Success; 1899 } 1900 1901 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1902 uint64_t Address, const void *Decoder) { 1903 // This function is the same as DecodeFMem but with the Reg and Base fields 1904 // swapped according to microMIPS spec. 1905 int Offset = SignExtend32<16>(Insn & 0xffff); 1906 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1907 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1908 1909 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1910 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1911 1912 Inst.addOperand(MCOperand::createReg(Reg)); 1913 Inst.addOperand(MCOperand::createReg(Base)); 1914 Inst.addOperand(MCOperand::createImm(Offset)); 1915 1916 return MCDisassembler::Success; 1917 } 1918 1919 static DecodeStatus DecodeFMem2(MCInst &Inst, 1920 unsigned Insn, 1921 uint64_t Address, 1922 const void *Decoder) { 1923 int Offset = SignExtend32<16>(Insn & 0xffff); 1924 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1925 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1926 1927 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1928 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1929 1930 Inst.addOperand(MCOperand::createReg(Reg)); 1931 Inst.addOperand(MCOperand::createReg(Base)); 1932 Inst.addOperand(MCOperand::createImm(Offset)); 1933 1934 return MCDisassembler::Success; 1935 } 1936 1937 static DecodeStatus DecodeFMem3(MCInst &Inst, 1938 unsigned Insn, 1939 uint64_t Address, 1940 const void *Decoder) { 1941 int Offset = SignExtend32<16>(Insn & 0xffff); 1942 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1943 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1944 1945 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1946 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1947 1948 Inst.addOperand(MCOperand::createReg(Reg)); 1949 Inst.addOperand(MCOperand::createReg(Base)); 1950 Inst.addOperand(MCOperand::createImm(Offset)); 1951 1952 return MCDisassembler::Success; 1953 } 1954 1955 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1956 unsigned Insn, 1957 uint64_t Address, 1958 const void *Decoder) { 1959 int Offset = SignExtend32<11>(Insn & 0x07ff); 1960 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1961 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1962 1963 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1964 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1965 1966 Inst.addOperand(MCOperand::createReg(Reg)); 1967 Inst.addOperand(MCOperand::createReg(Base)); 1968 Inst.addOperand(MCOperand::createImm(Offset)); 1969 1970 return MCDisassembler::Success; 1971 } 1972 1973 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 int Offset = SignExtend32<11>(Insn & 0x07ff); 1976 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1977 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1978 1979 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1980 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1981 1982 Inst.addOperand(MCOperand::createReg(Reg)); 1983 Inst.addOperand(MCOperand::createReg(Base)); 1984 Inst.addOperand(MCOperand::createImm(Offset)); 1985 1986 return MCDisassembler::Success; 1987 } 1988 1989 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1990 unsigned Insn, 1991 uint64_t Address, 1992 const void *Decoder) { 1993 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1994 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1995 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1996 1997 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1998 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1999 2000 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2001 Inst.addOperand(MCOperand::createReg(Rt)); 2002 } 2003 2004 Inst.addOperand(MCOperand::createReg(Rt)); 2005 Inst.addOperand(MCOperand::createReg(Base)); 2006 Inst.addOperand(MCOperand::createImm(Offset)); 2007 2008 return MCDisassembler::Success; 2009 } 2010 2011 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2012 unsigned RegNo, 2013 uint64_t Address, 2014 const void *Decoder) { 2015 // Currently only hardware register 29 is supported. 2016 if (RegNo != 29) 2017 return MCDisassembler::Fail; 2018 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2019 return MCDisassembler::Success; 2020 } 2021 2022 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2023 unsigned RegNo, 2024 uint64_t Address, 2025 const void *Decoder) { 2026 if (RegNo > 30 || RegNo %2) 2027 return MCDisassembler::Fail; 2028 2029 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2030 Inst.addOperand(MCOperand::createReg(Reg)); 2031 return MCDisassembler::Success; 2032 } 2033 2034 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2035 unsigned RegNo, 2036 uint64_t Address, 2037 const void *Decoder) { 2038 if (RegNo >= 4) 2039 return MCDisassembler::Fail; 2040 2041 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2042 Inst.addOperand(MCOperand::createReg(Reg)); 2043 return MCDisassembler::Success; 2044 } 2045 2046 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2047 unsigned RegNo, 2048 uint64_t Address, 2049 const void *Decoder) { 2050 if (RegNo >= 4) 2051 return MCDisassembler::Fail; 2052 2053 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2054 Inst.addOperand(MCOperand::createReg(Reg)); 2055 return MCDisassembler::Success; 2056 } 2057 2058 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2059 unsigned RegNo, 2060 uint64_t Address, 2061 const void *Decoder) { 2062 if (RegNo >= 4) 2063 return MCDisassembler::Fail; 2064 2065 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2066 Inst.addOperand(MCOperand::createReg(Reg)); 2067 return MCDisassembler::Success; 2068 } 2069 2070 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2071 unsigned RegNo, 2072 uint64_t Address, 2073 const void *Decoder) { 2074 if (RegNo > 31) 2075 return MCDisassembler::Fail; 2076 2077 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2078 Inst.addOperand(MCOperand::createReg(Reg)); 2079 return MCDisassembler::Success; 2080 } 2081 2082 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2083 unsigned RegNo, 2084 uint64_t Address, 2085 const void *Decoder) { 2086 if (RegNo > 31) 2087 return MCDisassembler::Fail; 2088 2089 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2090 Inst.addOperand(MCOperand::createReg(Reg)); 2091 return MCDisassembler::Success; 2092 } 2093 2094 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2095 unsigned RegNo, 2096 uint64_t Address, 2097 const void *Decoder) { 2098 if (RegNo > 31) 2099 return MCDisassembler::Fail; 2100 2101 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2102 Inst.addOperand(MCOperand::createReg(Reg)); 2103 return MCDisassembler::Success; 2104 } 2105 2106 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2107 unsigned RegNo, 2108 uint64_t Address, 2109 const void *Decoder) { 2110 if (RegNo > 31) 2111 return MCDisassembler::Fail; 2112 2113 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2114 Inst.addOperand(MCOperand::createReg(Reg)); 2115 return MCDisassembler::Success; 2116 } 2117 2118 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2119 unsigned RegNo, 2120 uint64_t Address, 2121 const void *Decoder) { 2122 if (RegNo > 7) 2123 return MCDisassembler::Fail; 2124 2125 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2126 Inst.addOperand(MCOperand::createReg(Reg)); 2127 return MCDisassembler::Success; 2128 } 2129 2130 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2131 unsigned RegNo, 2132 uint64_t Address, 2133 const void *Decoder) { 2134 if (RegNo > 31) 2135 return MCDisassembler::Fail; 2136 2137 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2138 Inst.addOperand(MCOperand::createReg(Reg)); 2139 return MCDisassembler::Success; 2140 } 2141 2142 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2143 unsigned RegNo, 2144 uint64_t Address, 2145 const void *Decoder) { 2146 if (RegNo > 31) 2147 return MCDisassembler::Fail; 2148 2149 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2150 Inst.addOperand(MCOperand::createReg(Reg)); 2151 return MCDisassembler::Success; 2152 } 2153 2154 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2155 unsigned Offset, 2156 uint64_t Address, 2157 const void *Decoder) { 2158 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2159 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2160 return MCDisassembler::Success; 2161 } 2162 2163 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2164 unsigned Offset, 2165 uint64_t Address, 2166 const void *Decoder) { 2167 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2168 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2169 return MCDisassembler::Success; 2170 } 2171 2172 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2173 unsigned Insn, 2174 uint64_t Address, 2175 const void *Decoder) { 2176 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2177 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2178 return MCDisassembler::Success; 2179 } 2180 2181 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2182 unsigned Offset, 2183 uint64_t Address, 2184 const void *Decoder) { 2185 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2186 2187 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2188 return MCDisassembler::Success; 2189 } 2190 2191 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2192 unsigned Offset, 2193 uint64_t Address, 2194 const void *Decoder) { 2195 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2196 2197 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2198 return MCDisassembler::Success; 2199 } 2200 2201 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2202 unsigned Offset, 2203 uint64_t Address, 2204 const void *Decoder) { 2205 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2206 2207 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2208 return MCDisassembler::Success; 2209 } 2210 2211 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2212 unsigned Offset, 2213 uint64_t Address, 2214 const void *Decoder) { 2215 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2216 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2217 return MCDisassembler::Success; 2218 } 2219 2220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2221 unsigned Offset, 2222 uint64_t Address, 2223 const void *Decoder) { 2224 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2225 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2226 return MCDisassembler::Success; 2227 } 2228 2229 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2230 unsigned Offset, 2231 uint64_t Address, 2232 const void *Decoder) { 2233 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2234 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2235 return MCDisassembler::Success; 2236 } 2237 2238 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2239 unsigned Offset, 2240 uint64_t Address, 2241 const void *Decoder) { 2242 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2243 2244 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2245 return MCDisassembler::Success; 2246 } 2247 2248 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2249 unsigned Insn, 2250 uint64_t Address, 2251 const void *Decoder) { 2252 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2253 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2254 return MCDisassembler::Success; 2255 } 2256 2257 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2258 unsigned Value, 2259 uint64_t Address, 2260 const void *Decoder) { 2261 if (Value == 0) 2262 Inst.addOperand(MCOperand::createImm(1)); 2263 else if (Value == 0x7) 2264 Inst.addOperand(MCOperand::createImm(-1)); 2265 else 2266 Inst.addOperand(MCOperand::createImm(Value << 2)); 2267 return MCDisassembler::Success; 2268 } 2269 2270 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2271 unsigned Value, 2272 uint64_t Address, 2273 const void *Decoder) { 2274 if (Value == 0x7F) 2275 Inst.addOperand(MCOperand::createImm(-1)); 2276 else 2277 Inst.addOperand(MCOperand::createImm(Value)); 2278 return MCDisassembler::Success; 2279 } 2280 2281 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2282 unsigned Value, 2283 uint64_t Address, 2284 const void *Decoder) { 2285 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2286 return MCDisassembler::Success; 2287 } 2288 2289 template <unsigned Bits, int Offset, int Scale> 2290 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2291 uint64_t Address, 2292 const void *Decoder) { 2293 Value &= ((1 << Bits) - 1); 2294 Value *= Scale; 2295 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2296 return MCDisassembler::Success; 2297 } 2298 2299 template <unsigned Bits, int Offset, int ScaleBy> 2300 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2301 uint64_t Address, 2302 const void *Decoder) { 2303 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2304 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2305 return MCDisassembler::Success; 2306 } 2307 2308 static DecodeStatus DecodeInsSize(MCInst &Inst, 2309 unsigned Insn, 2310 uint64_t Address, 2311 const void *Decoder) { 2312 // First we need to grab the pos(lsb) from MCInst. 2313 // This function only handles the 32 bit variants of ins, as dins 2314 // variants are handled differently. 2315 int Pos = Inst.getOperand(2).getImm(); 2316 int Size = (int) Insn - Pos + 1; 2317 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2318 return MCDisassembler::Success; 2319 } 2320 2321 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2322 uint64_t Address, const void *Decoder) { 2323 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2324 return MCDisassembler::Success; 2325 } 2326 2327 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2328 uint64_t Address, const void *Decoder) { 2329 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2330 return MCDisassembler::Success; 2331 } 2332 2333 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2334 uint64_t Address, const void *Decoder) { 2335 int32_t DecodedValue; 2336 switch (Insn) { 2337 case 0: DecodedValue = 256; break; 2338 case 1: DecodedValue = 257; break; 2339 case 510: DecodedValue = -258; break; 2340 case 511: DecodedValue = -257; break; 2341 default: DecodedValue = SignExtend32<9>(Insn); break; 2342 } 2343 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2344 return MCDisassembler::Success; 2345 } 2346 2347 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2348 uint64_t Address, const void *Decoder) { 2349 // Insn must be >= 0, since it is unsigned that condition is always true. 2350 assert(Insn < 16); 2351 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2352 255, 32768, 65535}; 2353 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2354 return MCDisassembler::Success; 2355 } 2356 2357 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2358 unsigned Insn, 2359 uint64_t Address, 2360 const void *Decoder) { 2361 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2362 Mips::S6, Mips::S7, Mips::FP}; 2363 unsigned RegNum; 2364 2365 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2366 2367 // Empty register lists are not allowed. 2368 if (RegLst == 0) 2369 return MCDisassembler::Fail; 2370 2371 RegNum = RegLst & 0xf; 2372 2373 // RegLst values 10-15, and 26-31 are reserved. 2374 if (RegNum > 9) 2375 return MCDisassembler::Fail; 2376 2377 for (unsigned i = 0; i < RegNum; i++) 2378 Inst.addOperand(MCOperand::createReg(Regs[i])); 2379 2380 if (RegLst & 0x10) 2381 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2382 2383 return MCDisassembler::Success; 2384 } 2385 2386 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2387 uint64_t Address, 2388 const void *Decoder) { 2389 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2390 unsigned RegLst; 2391 switch(Inst.getOpcode()) { 2392 default: 2393 RegLst = fieldFromInstruction(Insn, 4, 2); 2394 break; 2395 case Mips::LWM16_MMR6: 2396 case Mips::SWM16_MMR6: 2397 RegLst = fieldFromInstruction(Insn, 8, 2); 2398 break; 2399 } 2400 unsigned RegNum = RegLst & 0x3; 2401 2402 for (unsigned i = 0; i <= RegNum; i++) 2403 Inst.addOperand(MCOperand::createReg(Regs[i])); 2404 2405 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2406 2407 return MCDisassembler::Success; 2408 } 2409 2410 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2411 uint64_t Address, const void *Decoder) { 2412 switch (RegPair) { 2413 default: 2414 return MCDisassembler::Fail; 2415 case 0: 2416 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2417 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2418 break; 2419 case 1: 2420 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2421 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2422 break; 2423 case 2: 2424 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2425 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2426 break; 2427 case 3: 2428 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2429 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2430 break; 2431 case 4: 2432 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2433 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2434 break; 2435 case 5: 2436 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2437 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2438 break; 2439 case 6: 2440 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2441 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2442 break; 2443 case 7: 2444 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2445 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2446 break; 2447 } 2448 2449 return MCDisassembler::Success; 2450 } 2451 2452 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2453 uint64_t Address, const void *Decoder) { 2454 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2455 return MCDisassembler::Success; 2456 } 2457 2458 template <typename InsnType> 2459 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2460 uint64_t Address, 2461 const void *Decoder) { 2462 // We have: 2463 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2464 // Invalid if rt == 0 2465 // BGTZALC_MMR6 if rs == 0 && rt != 0 2466 // BLTZALC_MMR6 if rs != 0 && rs == rt 2467 // BLTUC_MMR6 if rs != 0 && rs != rt 2468 2469 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2470 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2471 InsnType Imm = 0; 2472 bool HasRs = false; 2473 bool HasRt = false; 2474 2475 if (Rt == 0) 2476 return MCDisassembler::Fail; 2477 else if (Rs == 0) { 2478 MI.setOpcode(Mips::BGTZALC_MMR6); 2479 HasRt = true; 2480 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2481 } 2482 else if (Rs == Rt) { 2483 MI.setOpcode(Mips::BLTZALC_MMR6); 2484 HasRs = true; 2485 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2486 } 2487 else { 2488 MI.setOpcode(Mips::BLTUC_MMR6); 2489 HasRs = true; 2490 HasRt = true; 2491 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2492 } 2493 2494 if (HasRs) 2495 MI.addOperand( 2496 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2497 2498 if (HasRt) 2499 MI.addOperand( 2500 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2501 2502 MI.addOperand(MCOperand::createImm(Imm)); 2503 2504 return MCDisassembler::Success; 2505 } 2506 2507 template <typename InsnType> 2508 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2509 uint64_t Address, 2510 const void *Decoder) { 2511 // We have: 2512 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2513 // Invalid if rt == 0 2514 // BLEZALC_MMR6 if rs == 0 && rt != 0 2515 // BGEZALC_MMR6 if rs == rt && rt != 0 2516 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2517 2518 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2519 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2520 InsnType Imm = 0; 2521 bool HasRs = false; 2522 2523 if (Rt == 0) 2524 return MCDisassembler::Fail; 2525 else if (Rs == 0) { 2526 MI.setOpcode(Mips::BLEZALC_MMR6); 2527 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2528 } 2529 else if (Rs == Rt) { 2530 MI.setOpcode(Mips::BGEZALC_MMR6); 2531 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2532 } 2533 else { 2534 HasRs = true; 2535 MI.setOpcode(Mips::BGEUC_MMR6); 2536 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2537 } 2538 2539 if (HasRs) 2540 MI.addOperand( 2541 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2542 MI.addOperand( 2543 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2544 2545 MI.addOperand(MCOperand::createImm(Imm)); 2546 2547 return MCDisassembler::Success; 2548 } 2549