1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 49 50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 51 52 bool hasCOP3() const { 53 // Only present in MIPS-I and MIPS-II 54 return !hasMips32() && !hasMips3(); 55 } 56 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 }; 62 63 } // end anonymous namespace 64 65 // Forward declare these because the autogenerated code will reference them. 66 // Definitions are further down. 67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 68 unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 78 unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 132 unsigned Insn, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 142 unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 147 unsigned RegNo, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 192 unsigned Offset, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 202 unsigned Offset, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 212 // shifted left by 1 bit. 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 235 unsigned Insn, 236 uint64_t Address, 237 const void *Decoder); 238 239 static DecodeStatus DecodeMem(MCInst &Inst, 240 unsigned Insn, 241 uint64_t Address, 242 const void *Decoder); 243 244 static DecodeStatus DecodeCacheOp(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 249 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 250 unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 254 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 255 unsigned Insn, 256 uint64_t Address, 257 const void *Decoder); 258 259 static DecodeStatus DecodeSyncI(MCInst &Inst, 260 unsigned Insn, 261 uint64_t Address, 262 const void *Decoder); 263 264 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 265 uint64_t Address, const void *Decoder); 266 267 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 298 uint64_t Address, 299 const void *Decoder); 300 301 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 306 uint64_t Address, 307 const void *Decoder); 308 309 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 310 uint64_t Address, 311 const void *Decoder); 312 313 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 314 unsigned Insn, 315 uint64_t Address, 316 const void *Decoder); 317 318 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 319 unsigned Value, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 324 unsigned Value, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 329 unsigned Value, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeSimm4(MCInst &Inst, 334 unsigned Value, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeSimm16(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 // Decode the immediate field of an LSA instruction which 344 // is off by one. 345 static DecodeStatus DecodeLSAImm(MCInst &Inst, 346 unsigned Insn, 347 uint64_t Address, 348 const void *Decoder); 349 350 static DecodeStatus DecodeInsSize(MCInst &Inst, 351 unsigned Insn, 352 uint64_t Address, 353 const void *Decoder); 354 355 static DecodeStatus DecodeExtSize(MCInst &Inst, 356 unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362 363 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 366 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 369 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 372 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 375 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 378 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 379 /// handle. 380 template <typename InsnType> 381 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 382 const void *Decoder); 383 384 template <typename InsnType> 385 static DecodeStatus 386 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 387 const void *Decoder); 388 389 template <typename InsnType> 390 static DecodeStatus 391 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 392 const void *Decoder); 393 394 template <typename InsnType> 395 static DecodeStatus 396 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 397 const void *Decoder); 398 399 template <typename InsnType> 400 static DecodeStatus 401 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 402 const void *Decoder); 403 404 template <typename InsnType> 405 static DecodeStatus 406 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 407 const void *Decoder); 408 409 template <typename InsnType> 410 static DecodeStatus 411 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 412 const void *Decoder); 413 414 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 415 uint64_t Address, 416 const void *Decoder); 417 418 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 419 uint64_t Address, 420 const void *Decoder); 421 422 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 423 uint64_t Address, 424 const void *Decoder); 425 426 namespace llvm { 427 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 428 TheMips64elTarget; 429 } 430 431 static MCDisassembler *createMipsDisassembler( 432 const Target &T, 433 const MCSubtargetInfo &STI, 434 MCContext &Ctx) { 435 return new MipsDisassembler(STI, Ctx, true); 436 } 437 438 static MCDisassembler *createMipselDisassembler( 439 const Target &T, 440 const MCSubtargetInfo &STI, 441 MCContext &Ctx) { 442 return new MipsDisassembler(STI, Ctx, false); 443 } 444 445 extern "C" void LLVMInitializeMipsDisassembler() { 446 // Register the disassembler. 447 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 448 createMipsDisassembler); 449 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 450 createMipselDisassembler); 451 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 452 createMipsDisassembler); 453 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 454 createMipselDisassembler); 455 } 456 457 #include "MipsGenDisassemblerTables.inc" 458 459 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 460 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 461 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 462 return *(RegInfo->getRegClass(RC).begin() + RegNo); 463 } 464 465 template <typename InsnType> 466 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 467 const void *Decoder) { 468 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 469 // The size of the n field depends on the element size 470 // The register class also depends on this. 471 InsnType tmp = fieldFromInstruction(insn, 17, 5); 472 unsigned NSize = 0; 473 DecodeFN RegDecoder = nullptr; 474 if ((tmp & 0x18) == 0x00) { // INSVE_B 475 NSize = 4; 476 RegDecoder = DecodeMSA128BRegisterClass; 477 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 478 NSize = 3; 479 RegDecoder = DecodeMSA128HRegisterClass; 480 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 481 NSize = 2; 482 RegDecoder = DecodeMSA128WRegisterClass; 483 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 484 NSize = 1; 485 RegDecoder = DecodeMSA128DRegisterClass; 486 } else 487 llvm_unreachable("Invalid encoding"); 488 489 assert(NSize != 0 && RegDecoder != nullptr); 490 491 // $wd 492 tmp = fieldFromInstruction(insn, 6, 5); 493 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 494 return MCDisassembler::Fail; 495 // $wd_in 496 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 497 return MCDisassembler::Fail; 498 // $n 499 tmp = fieldFromInstruction(insn, 16, NSize); 500 MI.addOperand(MCOperand::createImm(tmp)); 501 // $ws 502 tmp = fieldFromInstruction(insn, 11, 5); 503 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 504 return MCDisassembler::Fail; 505 // $n2 506 MI.addOperand(MCOperand::createImm(0)); 507 508 return MCDisassembler::Success; 509 } 510 511 template <typename InsnType> 512 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 513 uint64_t Address, 514 const void *Decoder) { 515 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 516 // (otherwise we would have matched the ADDI instruction from the earlier 517 // ISA's instead). 518 // 519 // We have: 520 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 521 // BOVC if rs >= rt 522 // BEQZALC if rs == 0 && rt != 0 523 // BEQC if rs < rt && rs != 0 524 525 InsnType Rs = fieldFromInstruction(insn, 21, 5); 526 InsnType Rt = fieldFromInstruction(insn, 16, 5); 527 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 528 bool HasRs = false; 529 530 if (Rs >= Rt) { 531 MI.setOpcode(Mips::BOVC); 532 HasRs = true; 533 } else if (Rs != 0 && Rs < Rt) { 534 MI.setOpcode(Mips::BEQC); 535 HasRs = true; 536 } else 537 MI.setOpcode(Mips::BEQZALC); 538 539 if (HasRs) 540 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 541 Rs))); 542 543 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 544 Rt))); 545 MI.addOperand(MCOperand::createImm(Imm)); 546 547 return MCDisassembler::Success; 548 } 549 550 template <typename InsnType> 551 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 552 uint64_t Address, 553 const void *Decoder) { 554 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 555 // (otherwise we would have matched the ADDI instruction from the earlier 556 // ISA's instead). 557 // 558 // We have: 559 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 560 // BNVC if rs >= rt 561 // BNEZALC if rs == 0 && rt != 0 562 // BNEC if rs < rt && rs != 0 563 564 InsnType Rs = fieldFromInstruction(insn, 21, 5); 565 InsnType Rt = fieldFromInstruction(insn, 16, 5); 566 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 567 bool HasRs = false; 568 569 if (Rs >= Rt) { 570 MI.setOpcode(Mips::BNVC); 571 HasRs = true; 572 } else if (Rs != 0 && Rs < Rt) { 573 MI.setOpcode(Mips::BNEC); 574 HasRs = true; 575 } else 576 MI.setOpcode(Mips::BNEZALC); 577 578 if (HasRs) 579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 580 Rs))); 581 582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 583 Rt))); 584 MI.addOperand(MCOperand::createImm(Imm)); 585 586 return MCDisassembler::Success; 587 } 588 589 template <typename InsnType> 590 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 591 uint64_t Address, 592 const void *Decoder) { 593 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 594 // (otherwise we would have matched the BLEZL instruction from the earlier 595 // ISA's instead). 596 // 597 // We have: 598 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 599 // Invalid if rs == 0 600 // BLEZC if rs == 0 && rt != 0 601 // BGEZC if rs == rt && rt != 0 602 // BGEC if rs != rt && rs != 0 && rt != 0 603 604 InsnType Rs = fieldFromInstruction(insn, 21, 5); 605 InsnType Rt = fieldFromInstruction(insn, 16, 5); 606 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 607 bool HasRs = false; 608 609 if (Rt == 0) 610 return MCDisassembler::Fail; 611 else if (Rs == 0) 612 MI.setOpcode(Mips::BLEZC); 613 else if (Rs == Rt) 614 MI.setOpcode(Mips::BGEZC); 615 else { 616 HasRs = true; 617 MI.setOpcode(Mips::BGEC); 618 } 619 620 if (HasRs) 621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 622 Rs))); 623 624 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 625 Rt))); 626 627 MI.addOperand(MCOperand::createImm(Imm)); 628 629 return MCDisassembler::Success; 630 } 631 632 template <typename InsnType> 633 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 634 uint64_t Address, 635 const void *Decoder) { 636 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 637 // (otherwise we would have matched the BGTZL instruction from the earlier 638 // ISA's instead). 639 // 640 // We have: 641 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 642 // Invalid if rs == 0 643 // BGTZC if rs == 0 && rt != 0 644 // BLTZC if rs == rt && rt != 0 645 // BLTC if rs != rt && rs != 0 && rt != 0 646 647 bool HasRs = false; 648 649 InsnType Rs = fieldFromInstruction(insn, 21, 5); 650 InsnType Rt = fieldFromInstruction(insn, 16, 5); 651 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 652 653 if (Rt == 0) 654 return MCDisassembler::Fail; 655 else if (Rs == 0) 656 MI.setOpcode(Mips::BGTZC); 657 else if (Rs == Rt) 658 MI.setOpcode(Mips::BLTZC); 659 else { 660 MI.setOpcode(Mips::BLTC); 661 HasRs = true; 662 } 663 664 if (HasRs) 665 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 666 Rs))); 667 668 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 669 Rt))); 670 671 MI.addOperand(MCOperand::createImm(Imm)); 672 673 return MCDisassembler::Success; 674 } 675 676 template <typename InsnType> 677 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 678 uint64_t Address, 679 const void *Decoder) { 680 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 681 // (otherwise we would have matched the BGTZ instruction from the earlier 682 // ISA's instead). 683 // 684 // We have: 685 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 686 // BGTZ if rt == 0 687 // BGTZALC if rs == 0 && rt != 0 688 // BLTZALC if rs != 0 && rs == rt 689 // BLTUC if rs != 0 && rs != rt 690 691 InsnType Rs = fieldFromInstruction(insn, 21, 5); 692 InsnType Rt = fieldFromInstruction(insn, 16, 5); 693 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 694 bool HasRs = false; 695 bool HasRt = false; 696 697 if (Rt == 0) { 698 MI.setOpcode(Mips::BGTZ); 699 HasRs = true; 700 } else if (Rs == 0) { 701 MI.setOpcode(Mips::BGTZALC); 702 HasRt = true; 703 } else if (Rs == Rt) { 704 MI.setOpcode(Mips::BLTZALC); 705 HasRs = true; 706 } else { 707 MI.setOpcode(Mips::BLTUC); 708 HasRs = true; 709 HasRt = true; 710 } 711 712 if (HasRs) 713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 714 Rs))); 715 716 if (HasRt) 717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 718 Rt))); 719 720 MI.addOperand(MCOperand::createImm(Imm)); 721 722 return MCDisassembler::Success; 723 } 724 725 template <typename InsnType> 726 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 727 uint64_t Address, 728 const void *Decoder) { 729 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 730 // (otherwise we would have matched the BLEZL instruction from the earlier 731 // ISA's instead). 732 // 733 // We have: 734 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 735 // Invalid if rs == 0 736 // BLEZALC if rs == 0 && rt != 0 737 // BGEZALC if rs == rt && rt != 0 738 // BGEUC if rs != rt && rs != 0 && rt != 0 739 740 InsnType Rs = fieldFromInstruction(insn, 21, 5); 741 InsnType Rt = fieldFromInstruction(insn, 16, 5); 742 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 743 bool HasRs = false; 744 745 if (Rt == 0) 746 return MCDisassembler::Fail; 747 else if (Rs == 0) 748 MI.setOpcode(Mips::BLEZALC); 749 else if (Rs == Rt) 750 MI.setOpcode(Mips::BGEZALC); 751 else { 752 HasRs = true; 753 MI.setOpcode(Mips::BGEUC); 754 } 755 756 if (HasRs) 757 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 758 Rs))); 759 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 760 Rt))); 761 762 MI.addOperand(MCOperand::createImm(Imm)); 763 764 return MCDisassembler::Success; 765 } 766 767 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 768 /// according to the given endianess. 769 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 770 uint64_t &Size, uint32_t &Insn, 771 bool IsBigEndian) { 772 // We want to read exactly 2 Bytes of data. 773 if (Bytes.size() < 2) { 774 Size = 0; 775 return MCDisassembler::Fail; 776 } 777 778 if (IsBigEndian) { 779 Insn = (Bytes[0] << 8) | Bytes[1]; 780 } else { 781 Insn = (Bytes[1] << 8) | Bytes[0]; 782 } 783 784 return MCDisassembler::Success; 785 } 786 787 /// Read four bytes from the ArrayRef and return 32 bit word sorted 788 /// according to the given endianess 789 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 790 uint64_t &Size, uint32_t &Insn, 791 bool IsBigEndian, bool IsMicroMips) { 792 // We want to read exactly 4 Bytes of data. 793 if (Bytes.size() < 4) { 794 Size = 0; 795 return MCDisassembler::Fail; 796 } 797 798 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 799 // always precede the low 16 bits in the instruction stream (that is, they 800 // are placed at lower addresses in the instruction stream). 801 // 802 // microMIPS byte ordering: 803 // Big-endian: 0 | 1 | 2 | 3 804 // Little-endian: 1 | 0 | 3 | 2 805 806 if (IsBigEndian) { 807 // Encoded as a big-endian 32-bit word in the stream. 808 Insn = 809 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 810 } else { 811 if (IsMicroMips) { 812 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 813 (Bytes[1] << 24); 814 } else { 815 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 816 (Bytes[3] << 24); 817 } 818 } 819 820 return MCDisassembler::Success; 821 } 822 823 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 824 ArrayRef<uint8_t> Bytes, 825 uint64_t Address, 826 raw_ostream &VStream, 827 raw_ostream &CStream) const { 828 uint32_t Insn; 829 DecodeStatus Result; 830 831 if (IsMicroMips) { 832 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 833 834 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 835 // Calling the auto-generated decoder function. 836 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 837 this, STI); 838 if (Result != MCDisassembler::Fail) { 839 Size = 2; 840 return Result; 841 } 842 843 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 844 if (Result == MCDisassembler::Fail) 845 return MCDisassembler::Fail; 846 847 if (hasMips32r6()) { 848 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 849 // Calling the auto-generated decoder function. 850 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 851 this, STI); 852 } else { 853 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 854 // Calling the auto-generated decoder function. 855 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 856 this, STI); 857 } 858 859 if (Result != MCDisassembler::Fail) { 860 Size = 4; 861 return Result; 862 } 863 return MCDisassembler::Fail; 864 } 865 866 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 867 if (Result == MCDisassembler::Fail) 868 return MCDisassembler::Fail; 869 870 if (hasCOP3()) { 871 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 872 Result = 873 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 874 if (Result != MCDisassembler::Fail) { 875 Size = 4; 876 return Result; 877 } 878 } 879 880 if (hasMips32r6() && isGP64()) { 881 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 882 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 883 Address, this, STI); 884 if (Result != MCDisassembler::Fail) { 885 Size = 4; 886 return Result; 887 } 888 } 889 890 if (hasMips32r6()) { 891 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 892 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 893 Address, this, STI); 894 if (Result != MCDisassembler::Fail) { 895 Size = 4; 896 return Result; 897 } 898 } 899 900 if (hasCnMips()) { 901 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 902 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 903 Address, this, STI); 904 if (Result != MCDisassembler::Fail) { 905 Size = 4; 906 return Result; 907 } 908 } 909 910 if (isGP64()) { 911 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 912 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 913 Address, this, STI); 914 if (Result != MCDisassembler::Fail) { 915 Size = 4; 916 return Result; 917 } 918 } 919 920 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 921 // Calling the auto-generated decoder function. 922 Result = 923 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 924 if (Result != MCDisassembler::Fail) { 925 Size = 4; 926 return Result; 927 } 928 929 return MCDisassembler::Fail; 930 } 931 932 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 933 unsigned RegNo, 934 uint64_t Address, 935 const void *Decoder) { 936 937 return MCDisassembler::Fail; 938 939 } 940 941 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 942 unsigned RegNo, 943 uint64_t Address, 944 const void *Decoder) { 945 946 if (RegNo > 31) 947 return MCDisassembler::Fail; 948 949 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 950 Inst.addOperand(MCOperand::createReg(Reg)); 951 return MCDisassembler::Success; 952 } 953 954 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 955 unsigned RegNo, 956 uint64_t Address, 957 const void *Decoder) { 958 if (RegNo > 7) 959 return MCDisassembler::Fail; 960 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 961 Inst.addOperand(MCOperand::createReg(Reg)); 962 return MCDisassembler::Success; 963 } 964 965 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 966 unsigned RegNo, 967 uint64_t Address, 968 const void *Decoder) { 969 if (RegNo > 7) 970 return MCDisassembler::Fail; 971 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 972 Inst.addOperand(MCOperand::createReg(Reg)); 973 return MCDisassembler::Success; 974 } 975 976 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 977 unsigned RegNo, 978 uint64_t Address, 979 const void *Decoder) { 980 if (RegNo > 7) 981 return MCDisassembler::Fail; 982 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 983 Inst.addOperand(MCOperand::createReg(Reg)); 984 return MCDisassembler::Success; 985 } 986 987 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 988 unsigned RegNo, 989 uint64_t Address, 990 const void *Decoder) { 991 if (RegNo > 31) 992 return MCDisassembler::Fail; 993 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 994 Inst.addOperand(MCOperand::createReg(Reg)); 995 return MCDisassembler::Success; 996 } 997 998 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 999 unsigned RegNo, 1000 uint64_t Address, 1001 const void *Decoder) { 1002 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1003 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1004 1005 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1006 } 1007 1008 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1009 unsigned RegNo, 1010 uint64_t Address, 1011 const void *Decoder) { 1012 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1013 } 1014 1015 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1016 unsigned RegNo, 1017 uint64_t Address, 1018 const void *Decoder) { 1019 if (RegNo > 31) 1020 return MCDisassembler::Fail; 1021 1022 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1023 Inst.addOperand(MCOperand::createReg(Reg)); 1024 return MCDisassembler::Success; 1025 } 1026 1027 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1028 unsigned RegNo, 1029 uint64_t Address, 1030 const void *Decoder) { 1031 if (RegNo > 31) 1032 return MCDisassembler::Fail; 1033 1034 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1035 Inst.addOperand(MCOperand::createReg(Reg)); 1036 return MCDisassembler::Success; 1037 } 1038 1039 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1040 unsigned RegNo, 1041 uint64_t Address, 1042 const void *Decoder) { 1043 if (RegNo > 31) 1044 return MCDisassembler::Fail; 1045 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1046 Inst.addOperand(MCOperand::createReg(Reg)); 1047 return MCDisassembler::Success; 1048 } 1049 1050 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1051 unsigned RegNo, 1052 uint64_t Address, 1053 const void *Decoder) { 1054 if (RegNo > 7) 1055 return MCDisassembler::Fail; 1056 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1057 Inst.addOperand(MCOperand::createReg(Reg)); 1058 return MCDisassembler::Success; 1059 } 1060 1061 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1062 uint64_t Address, 1063 const void *Decoder) { 1064 if (RegNo > 31) 1065 return MCDisassembler::Fail; 1066 1067 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1068 Inst.addOperand(MCOperand::createReg(Reg)); 1069 return MCDisassembler::Success; 1070 } 1071 1072 static DecodeStatus DecodeMem(MCInst &Inst, 1073 unsigned Insn, 1074 uint64_t Address, 1075 const void *Decoder) { 1076 int Offset = SignExtend32<16>(Insn & 0xffff); 1077 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1078 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1079 1080 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1081 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1082 1083 if(Inst.getOpcode() == Mips::SC || 1084 Inst.getOpcode() == Mips::SCD){ 1085 Inst.addOperand(MCOperand::createReg(Reg)); 1086 } 1087 1088 Inst.addOperand(MCOperand::createReg(Reg)); 1089 Inst.addOperand(MCOperand::createReg(Base)); 1090 Inst.addOperand(MCOperand::createImm(Offset)); 1091 1092 return MCDisassembler::Success; 1093 } 1094 1095 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1096 unsigned Insn, 1097 uint64_t Address, 1098 const void *Decoder) { 1099 int Offset = SignExtend32<16>(Insn & 0xffff); 1100 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1101 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1102 1103 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1104 1105 Inst.addOperand(MCOperand::createReg(Base)); 1106 Inst.addOperand(MCOperand::createImm(Offset)); 1107 Inst.addOperand(MCOperand::createImm(Hint)); 1108 1109 return MCDisassembler::Success; 1110 } 1111 1112 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1113 unsigned Insn, 1114 uint64_t Address, 1115 const void *Decoder) { 1116 int Offset = SignExtend32<12>(Insn & 0xfff); 1117 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1118 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1119 1120 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1121 1122 Inst.addOperand(MCOperand::createReg(Base)); 1123 Inst.addOperand(MCOperand::createImm(Offset)); 1124 Inst.addOperand(MCOperand::createImm(Hint)); 1125 1126 return MCDisassembler::Success; 1127 } 1128 1129 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 1130 unsigned Insn, 1131 uint64_t Address, 1132 const void *Decoder) { 1133 int Offset = fieldFromInstruction(Insn, 7, 9); 1134 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1135 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1136 1137 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1138 1139 Inst.addOperand(MCOperand::createReg(Base)); 1140 Inst.addOperand(MCOperand::createImm(Offset)); 1141 Inst.addOperand(MCOperand::createImm(Hint)); 1142 1143 return MCDisassembler::Success; 1144 } 1145 1146 static DecodeStatus DecodeSyncI(MCInst &Inst, 1147 unsigned Insn, 1148 uint64_t Address, 1149 const void *Decoder) { 1150 int Offset = SignExtend32<16>(Insn & 0xffff); 1151 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1152 1153 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1154 1155 Inst.addOperand(MCOperand::createReg(Base)); 1156 Inst.addOperand(MCOperand::createImm(Offset)); 1157 1158 return MCDisassembler::Success; 1159 } 1160 1161 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1162 uint64_t Address, const void *Decoder) { 1163 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1164 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1165 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1166 1167 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1168 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1169 1170 Inst.addOperand(MCOperand::createReg(Reg)); 1171 Inst.addOperand(MCOperand::createReg(Base)); 1172 1173 // The immediate field of an LD/ST instruction is scaled which means it must 1174 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1175 // data format. 1176 // .b - 1 byte 1177 // .h - 2 bytes 1178 // .w - 4 bytes 1179 // .d - 8 bytes 1180 switch(Inst.getOpcode()) 1181 { 1182 default: 1183 assert (0 && "Unexpected instruction"); 1184 return MCDisassembler::Fail; 1185 break; 1186 case Mips::LD_B: 1187 case Mips::ST_B: 1188 Inst.addOperand(MCOperand::createImm(Offset)); 1189 break; 1190 case Mips::LD_H: 1191 case Mips::ST_H: 1192 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1193 break; 1194 case Mips::LD_W: 1195 case Mips::ST_W: 1196 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1197 break; 1198 case Mips::LD_D: 1199 case Mips::ST_D: 1200 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1201 break; 1202 } 1203 1204 return MCDisassembler::Success; 1205 } 1206 1207 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1208 unsigned Insn, 1209 uint64_t Address, 1210 const void *Decoder) { 1211 unsigned Offset = Insn & 0xf; 1212 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1213 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1214 1215 switch (Inst.getOpcode()) { 1216 case Mips::LBU16_MM: 1217 case Mips::LHU16_MM: 1218 case Mips::LW16_MM: 1219 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1220 == MCDisassembler::Fail) 1221 return MCDisassembler::Fail; 1222 break; 1223 case Mips::SB16_MM: 1224 case Mips::SH16_MM: 1225 case Mips::SW16_MM: 1226 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1227 == MCDisassembler::Fail) 1228 return MCDisassembler::Fail; 1229 break; 1230 } 1231 1232 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1233 == MCDisassembler::Fail) 1234 return MCDisassembler::Fail; 1235 1236 switch (Inst.getOpcode()) { 1237 case Mips::LBU16_MM: 1238 if (Offset == 0xf) 1239 Inst.addOperand(MCOperand::createImm(-1)); 1240 else 1241 Inst.addOperand(MCOperand::createImm(Offset)); 1242 break; 1243 case Mips::SB16_MM: 1244 Inst.addOperand(MCOperand::createImm(Offset)); 1245 break; 1246 case Mips::LHU16_MM: 1247 case Mips::SH16_MM: 1248 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1249 break; 1250 case Mips::LW16_MM: 1251 case Mips::SW16_MM: 1252 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1253 break; 1254 } 1255 1256 return MCDisassembler::Success; 1257 } 1258 1259 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1260 unsigned Insn, 1261 uint64_t Address, 1262 const void *Decoder) { 1263 unsigned Offset = Insn & 0x1F; 1264 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1265 1266 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1267 1268 Inst.addOperand(MCOperand::createReg(Reg)); 1269 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1270 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1271 1272 return MCDisassembler::Success; 1273 } 1274 1275 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1276 unsigned Insn, 1277 uint64_t Address, 1278 const void *Decoder) { 1279 unsigned Offset = Insn & 0x7F; 1280 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1281 1282 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1283 1284 Inst.addOperand(MCOperand::createReg(Reg)); 1285 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1286 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1287 1288 return MCDisassembler::Success; 1289 } 1290 1291 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1292 unsigned Insn, 1293 uint64_t Address, 1294 const void *Decoder) { 1295 int Offset = SignExtend32<4>(Insn & 0xf); 1296 1297 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1298 == MCDisassembler::Fail) 1299 return MCDisassembler::Fail; 1300 1301 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1302 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1303 1304 return MCDisassembler::Success; 1305 } 1306 1307 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1308 unsigned Insn, 1309 uint64_t Address, 1310 const void *Decoder) { 1311 int Offset = SignExtend32<12>(Insn & 0x0fff); 1312 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1313 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1314 1315 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1316 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1317 1318 switch (Inst.getOpcode()) { 1319 case Mips::SWM32_MM: 1320 case Mips::LWM32_MM: 1321 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1322 == MCDisassembler::Fail) 1323 return MCDisassembler::Fail; 1324 Inst.addOperand(MCOperand::createReg(Base)); 1325 Inst.addOperand(MCOperand::createImm(Offset)); 1326 break; 1327 case Mips::SC_MM: 1328 Inst.addOperand(MCOperand::createReg(Reg)); 1329 // fallthrough 1330 default: 1331 Inst.addOperand(MCOperand::createReg(Reg)); 1332 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1333 Inst.addOperand(MCOperand::createReg(Reg+1)); 1334 1335 Inst.addOperand(MCOperand::createReg(Base)); 1336 Inst.addOperand(MCOperand::createImm(Offset)); 1337 } 1338 1339 return MCDisassembler::Success; 1340 } 1341 1342 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1343 unsigned Insn, 1344 uint64_t Address, 1345 const void *Decoder) { 1346 int Offset = SignExtend32<16>(Insn & 0xffff); 1347 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1348 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1349 1350 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1351 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1352 1353 Inst.addOperand(MCOperand::createReg(Reg)); 1354 Inst.addOperand(MCOperand::createReg(Base)); 1355 Inst.addOperand(MCOperand::createImm(Offset)); 1356 1357 return MCDisassembler::Success; 1358 } 1359 1360 static DecodeStatus DecodeFMem(MCInst &Inst, 1361 unsigned Insn, 1362 uint64_t Address, 1363 const void *Decoder) { 1364 int Offset = SignExtend32<16>(Insn & 0xffff); 1365 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1366 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1367 1368 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1369 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1370 1371 Inst.addOperand(MCOperand::createReg(Reg)); 1372 Inst.addOperand(MCOperand::createReg(Base)); 1373 Inst.addOperand(MCOperand::createImm(Offset)); 1374 1375 return MCDisassembler::Success; 1376 } 1377 1378 static DecodeStatus DecodeFMem2(MCInst &Inst, 1379 unsigned Insn, 1380 uint64_t Address, 1381 const void *Decoder) { 1382 int Offset = SignExtend32<16>(Insn & 0xffff); 1383 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1384 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1385 1386 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1387 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1388 1389 Inst.addOperand(MCOperand::createReg(Reg)); 1390 Inst.addOperand(MCOperand::createReg(Base)); 1391 Inst.addOperand(MCOperand::createImm(Offset)); 1392 1393 return MCDisassembler::Success; 1394 } 1395 1396 static DecodeStatus DecodeFMem3(MCInst &Inst, 1397 unsigned Insn, 1398 uint64_t Address, 1399 const void *Decoder) { 1400 int Offset = SignExtend32<16>(Insn & 0xffff); 1401 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1402 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1403 1404 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1405 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1406 1407 Inst.addOperand(MCOperand::createReg(Reg)); 1408 Inst.addOperand(MCOperand::createReg(Base)); 1409 Inst.addOperand(MCOperand::createImm(Offset)); 1410 1411 return MCDisassembler::Success; 1412 } 1413 1414 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1415 unsigned Insn, 1416 uint64_t Address, 1417 const void *Decoder) { 1418 int Offset = SignExtend32<11>(Insn & 0x07ff); 1419 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1420 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1421 1422 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1423 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1424 1425 Inst.addOperand(MCOperand::createReg(Reg)); 1426 Inst.addOperand(MCOperand::createReg(Base)); 1427 Inst.addOperand(MCOperand::createImm(Offset)); 1428 1429 return MCDisassembler::Success; 1430 } 1431 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1432 unsigned Insn, 1433 uint64_t Address, 1434 const void *Decoder) { 1435 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1436 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1437 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1438 1439 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1440 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1441 1442 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1443 Inst.addOperand(MCOperand::createReg(Rt)); 1444 } 1445 1446 Inst.addOperand(MCOperand::createReg(Rt)); 1447 Inst.addOperand(MCOperand::createReg(Base)); 1448 Inst.addOperand(MCOperand::createImm(Offset)); 1449 1450 return MCDisassembler::Success; 1451 } 1452 1453 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1454 unsigned RegNo, 1455 uint64_t Address, 1456 const void *Decoder) { 1457 // Currently only hardware register 29 is supported. 1458 if (RegNo != 29) 1459 return MCDisassembler::Fail; 1460 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1461 return MCDisassembler::Success; 1462 } 1463 1464 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1465 unsigned RegNo, 1466 uint64_t Address, 1467 const void *Decoder) { 1468 if (RegNo > 30 || RegNo %2) 1469 return MCDisassembler::Fail; 1470 1471 ; 1472 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1473 Inst.addOperand(MCOperand::createReg(Reg)); 1474 return MCDisassembler::Success; 1475 } 1476 1477 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1478 unsigned RegNo, 1479 uint64_t Address, 1480 const void *Decoder) { 1481 if (RegNo >= 4) 1482 return MCDisassembler::Fail; 1483 1484 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1485 Inst.addOperand(MCOperand::createReg(Reg)); 1486 return MCDisassembler::Success; 1487 } 1488 1489 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1490 unsigned RegNo, 1491 uint64_t Address, 1492 const void *Decoder) { 1493 if (RegNo >= 4) 1494 return MCDisassembler::Fail; 1495 1496 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1497 Inst.addOperand(MCOperand::createReg(Reg)); 1498 return MCDisassembler::Success; 1499 } 1500 1501 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1502 unsigned RegNo, 1503 uint64_t Address, 1504 const void *Decoder) { 1505 if (RegNo >= 4) 1506 return MCDisassembler::Fail; 1507 1508 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1509 Inst.addOperand(MCOperand::createReg(Reg)); 1510 return MCDisassembler::Success; 1511 } 1512 1513 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1514 unsigned RegNo, 1515 uint64_t Address, 1516 const void *Decoder) { 1517 if (RegNo > 31) 1518 return MCDisassembler::Fail; 1519 1520 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1521 Inst.addOperand(MCOperand::createReg(Reg)); 1522 return MCDisassembler::Success; 1523 } 1524 1525 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1526 unsigned RegNo, 1527 uint64_t Address, 1528 const void *Decoder) { 1529 if (RegNo > 31) 1530 return MCDisassembler::Fail; 1531 1532 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1533 Inst.addOperand(MCOperand::createReg(Reg)); 1534 return MCDisassembler::Success; 1535 } 1536 1537 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1538 unsigned RegNo, 1539 uint64_t Address, 1540 const void *Decoder) { 1541 if (RegNo > 31) 1542 return MCDisassembler::Fail; 1543 1544 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1545 Inst.addOperand(MCOperand::createReg(Reg)); 1546 return MCDisassembler::Success; 1547 } 1548 1549 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1550 unsigned RegNo, 1551 uint64_t Address, 1552 const void *Decoder) { 1553 if (RegNo > 31) 1554 return MCDisassembler::Fail; 1555 1556 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1557 Inst.addOperand(MCOperand::createReg(Reg)); 1558 return MCDisassembler::Success; 1559 } 1560 1561 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1562 unsigned RegNo, 1563 uint64_t Address, 1564 const void *Decoder) { 1565 if (RegNo > 7) 1566 return MCDisassembler::Fail; 1567 1568 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1569 Inst.addOperand(MCOperand::createReg(Reg)); 1570 return MCDisassembler::Success; 1571 } 1572 1573 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1574 unsigned RegNo, 1575 uint64_t Address, 1576 const void *Decoder) { 1577 if (RegNo > 31) 1578 return MCDisassembler::Fail; 1579 1580 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1581 Inst.addOperand(MCOperand::createReg(Reg)); 1582 return MCDisassembler::Success; 1583 } 1584 1585 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1586 unsigned RegNo, 1587 uint64_t Address, 1588 const void *Decoder) { 1589 if (RegNo > 31) 1590 return MCDisassembler::Fail; 1591 1592 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1593 Inst.addOperand(MCOperand::createReg(Reg)); 1594 return MCDisassembler::Success; 1595 } 1596 1597 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1598 unsigned Offset, 1599 uint64_t Address, 1600 const void *Decoder) { 1601 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1602 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1603 return MCDisassembler::Success; 1604 } 1605 1606 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1607 unsigned Insn, 1608 uint64_t Address, 1609 const void *Decoder) { 1610 1611 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1612 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1613 return MCDisassembler::Success; 1614 } 1615 1616 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1617 unsigned Offset, 1618 uint64_t Address, 1619 const void *Decoder) { 1620 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1621 1622 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1623 return MCDisassembler::Success; 1624 } 1625 1626 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1627 unsigned Offset, 1628 uint64_t Address, 1629 const void *Decoder) { 1630 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1631 1632 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1633 return MCDisassembler::Success; 1634 } 1635 1636 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1637 unsigned Offset, 1638 uint64_t Address, 1639 const void *Decoder) { 1640 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1641 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1642 return MCDisassembler::Success; 1643 } 1644 1645 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1646 unsigned Offset, 1647 uint64_t Address, 1648 const void *Decoder) { 1649 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1650 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1651 return MCDisassembler::Success; 1652 } 1653 1654 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1655 unsigned Offset, 1656 uint64_t Address, 1657 const void *Decoder) { 1658 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1659 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1660 return MCDisassembler::Success; 1661 } 1662 1663 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1664 unsigned Insn, 1665 uint64_t Address, 1666 const void *Decoder) { 1667 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1668 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1669 return MCDisassembler::Success; 1670 } 1671 1672 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1673 unsigned Value, 1674 uint64_t Address, 1675 const void *Decoder) { 1676 if (Value == 0) 1677 Inst.addOperand(MCOperand::createImm(1)); 1678 else if (Value == 0x7) 1679 Inst.addOperand(MCOperand::createImm(-1)); 1680 else 1681 Inst.addOperand(MCOperand::createImm(Value << 2)); 1682 return MCDisassembler::Success; 1683 } 1684 1685 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1686 unsigned Value, 1687 uint64_t Address, 1688 const void *Decoder) { 1689 Inst.addOperand(MCOperand::createImm(Value << 2)); 1690 return MCDisassembler::Success; 1691 } 1692 1693 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1694 unsigned Value, 1695 uint64_t Address, 1696 const void *Decoder) { 1697 if (Value == 0x7F) 1698 Inst.addOperand(MCOperand::createImm(-1)); 1699 else 1700 Inst.addOperand(MCOperand::createImm(Value)); 1701 return MCDisassembler::Success; 1702 } 1703 1704 static DecodeStatus DecodeSimm4(MCInst &Inst, 1705 unsigned Value, 1706 uint64_t Address, 1707 const void *Decoder) { 1708 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); 1709 return MCDisassembler::Success; 1710 } 1711 1712 static DecodeStatus DecodeSimm16(MCInst &Inst, 1713 unsigned Insn, 1714 uint64_t Address, 1715 const void *Decoder) { 1716 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); 1717 return MCDisassembler::Success; 1718 } 1719 1720 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1721 unsigned Insn, 1722 uint64_t Address, 1723 const void *Decoder) { 1724 // We add one to the immediate field as it was encoded as 'imm - 1'. 1725 Inst.addOperand(MCOperand::createImm(Insn + 1)); 1726 return MCDisassembler::Success; 1727 } 1728 1729 static DecodeStatus DecodeInsSize(MCInst &Inst, 1730 unsigned Insn, 1731 uint64_t Address, 1732 const void *Decoder) { 1733 // First we need to grab the pos(lsb) from MCInst. 1734 int Pos = Inst.getOperand(2).getImm(); 1735 int Size = (int) Insn - Pos + 1; 1736 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1737 return MCDisassembler::Success; 1738 } 1739 1740 static DecodeStatus DecodeExtSize(MCInst &Inst, 1741 unsigned Insn, 1742 uint64_t Address, 1743 const void *Decoder) { 1744 int Size = (int) Insn + 1; 1745 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1746 return MCDisassembler::Success; 1747 } 1748 1749 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1750 uint64_t Address, const void *Decoder) { 1751 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1752 return MCDisassembler::Success; 1753 } 1754 1755 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1756 uint64_t Address, const void *Decoder) { 1757 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1758 return MCDisassembler::Success; 1759 } 1760 1761 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1762 uint64_t Address, const void *Decoder) { 1763 int32_t DecodedValue; 1764 switch (Insn) { 1765 case 0: DecodedValue = 256; break; 1766 case 1: DecodedValue = 257; break; 1767 case 510: DecodedValue = -258; break; 1768 case 511: DecodedValue = -257; break; 1769 default: DecodedValue = SignExtend32<9>(Insn); break; 1770 } 1771 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1772 return MCDisassembler::Success; 1773 } 1774 1775 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1776 uint64_t Address, const void *Decoder) { 1777 // Insn must be >= 0, since it is unsigned that condition is always true. 1778 assert(Insn < 16); 1779 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1780 255, 32768, 65535}; 1781 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 1782 return MCDisassembler::Success; 1783 } 1784 1785 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1786 uint64_t Address, const void *Decoder) { 1787 Inst.addOperand(MCOperand::createImm(Insn << 2)); 1788 return MCDisassembler::Success; 1789 } 1790 1791 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1792 unsigned Insn, 1793 uint64_t Address, 1794 const void *Decoder) { 1795 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1796 Mips::S6, Mips::FP}; 1797 unsigned RegNum; 1798 1799 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1800 // Empty register lists are not allowed. 1801 if (RegLst == 0) 1802 return MCDisassembler::Fail; 1803 1804 RegNum = RegLst & 0xf; 1805 for (unsigned i = 0; i < RegNum; i++) 1806 Inst.addOperand(MCOperand::createReg(Regs[i])); 1807 1808 if (RegLst & 0x10) 1809 Inst.addOperand(MCOperand::createReg(Mips::RA)); 1810 1811 return MCDisassembler::Success; 1812 } 1813 1814 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 1815 uint64_t Address, 1816 const void *Decoder) { 1817 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 1818 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 1819 unsigned RegNum = RegLst & 0x3; 1820 1821 for (unsigned i = 0; i <= RegNum; i++) 1822 Inst.addOperand(MCOperand::createReg(Regs[i])); 1823 1824 Inst.addOperand(MCOperand::createReg(Mips::RA)); 1825 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 1830 uint64_t Address, const void *Decoder) { 1831 1832 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 1833 1834 switch (RegPair) { 1835 default: 1836 return MCDisassembler::Fail; 1837 case 0: 1838 Inst.addOperand(MCOperand::createReg(Mips::A1)); 1839 Inst.addOperand(MCOperand::createReg(Mips::A2)); 1840 break; 1841 case 1: 1842 Inst.addOperand(MCOperand::createReg(Mips::A1)); 1843 Inst.addOperand(MCOperand::createReg(Mips::A3)); 1844 break; 1845 case 2: 1846 Inst.addOperand(MCOperand::createReg(Mips::A2)); 1847 Inst.addOperand(MCOperand::createReg(Mips::A3)); 1848 break; 1849 case 3: 1850 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1851 Inst.addOperand(MCOperand::createReg(Mips::S5)); 1852 break; 1853 case 4: 1854 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1855 Inst.addOperand(MCOperand::createReg(Mips::S6)); 1856 break; 1857 case 5: 1858 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1859 Inst.addOperand(MCOperand::createReg(Mips::A1)); 1860 break; 1861 case 6: 1862 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1863 Inst.addOperand(MCOperand::createReg(Mips::A2)); 1864 break; 1865 case 7: 1866 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1867 Inst.addOperand(MCOperand::createReg(Mips::A3)); 1868 break; 1869 } 1870 1871 return MCDisassembler::Success; 1872 } 1873 1874 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 1875 uint64_t Address, const void *Decoder) { 1876 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 1877 return MCDisassembler::Success; 1878 } 1879