1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 49 50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 51 52 bool hasCOP3() const { 53 // Only present in MIPS-I and MIPS-II 54 return !hasMips32() && !hasMips3(); 55 } 56 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 }; 62 63 } // end anonymous namespace 64 65 // Forward declare these because the autogenerated code will reference them. 66 // Definitions are further down. 67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 68 unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 78 unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 132 unsigned Insn, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 142 unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 147 unsigned RegNo, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 192 unsigned Offset, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 202 unsigned Offset, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 212 // shifted left by 1 bit. 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 235 unsigned Insn, 236 uint64_t Address, 237 const void *Decoder); 238 239 static DecodeStatus DecodeMem(MCInst &Inst, 240 unsigned Insn, 241 uint64_t Address, 242 const void *Decoder); 243 244 static DecodeStatus DecodeMemEVA(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 249 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 250 unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 254 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 255 unsigned Insn, 256 uint64_t Address, 257 const void *Decoder); 258 259 static DecodeStatus DecodeCacheOp(MCInst &Inst, 260 unsigned Insn, 261 uint64_t Address, 262 const void *Decoder); 263 264 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 265 unsigned Insn, 266 uint64_t Address, 267 const void *Decoder); 268 269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 270 unsigned Insn, 271 uint64_t Address, 272 const void *Decoder); 273 274 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeSyncI(MCInst &Inst, 285 unsigned Insn, 286 uint64_t Address, 287 const void *Decoder); 288 289 static DecodeStatus DecodeSynciR6(MCInst &Inst, 290 unsigned Insn, 291 uint64_t Address, 292 const void *Decoder); 293 294 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 297 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 313 unsigned Insn, 314 uint64_t Address, 315 const void *Decoder); 316 317 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 318 unsigned Insn, 319 uint64_t Address, 320 const void *Decoder); 321 322 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 323 unsigned Insn, 324 uint64_t Address, 325 const void *Decoder); 326 327 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 328 unsigned Insn, 329 uint64_t Address, 330 const void *Decoder); 331 332 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 341 uint64_t Address, 342 const void *Decoder); 343 344 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 354 unsigned Value, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 359 unsigned Value, 360 uint64_t Address, 361 const void *Decoder); 362 363 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 364 unsigned Value, 365 uint64_t Address, 366 const void *Decoder); 367 368 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 369 unsigned Value, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeSimm4(MCInst &Inst, 374 unsigned Value, 375 uint64_t Address, 376 const void *Decoder); 377 378 static DecodeStatus DecodeSimm16(MCInst &Inst, 379 unsigned Insn, 380 uint64_t Address, 381 const void *Decoder); 382 383 template <unsigned Bits, int Offset> 384 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 385 uint64_t Address, const void *Decoder); 386 387 static DecodeStatus DecodeInsSize(MCInst &Inst, 388 unsigned Insn, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodeExtSize(MCInst &Inst, 393 unsigned Insn, 394 uint64_t Address, 395 const void *Decoder); 396 397 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 400 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 401 uint64_t Address, const void *Decoder); 402 403 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 404 uint64_t Address, const void *Decoder); 405 406 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 407 uint64_t Address, const void *Decoder); 408 409 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 410 uint64_t Address, const void *Decoder); 411 412 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void *Decoder); 414 415 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 416 /// handle. 417 template <typename InsnType> 418 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 419 const void *Decoder); 420 421 template <typename InsnType> 422 static DecodeStatus 423 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 424 const void *Decoder); 425 426 template <typename InsnType> 427 static DecodeStatus 428 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 429 const void *Decoder); 430 431 template <typename InsnType> 432 static DecodeStatus 433 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 434 const void *Decoder); 435 436 template <typename InsnType> 437 static DecodeStatus 438 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 439 const void *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus 443 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 444 const void *Decoder); 445 446 template <typename InsnType> 447 static DecodeStatus 448 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 449 const void *Decoder); 450 451 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 452 uint64_t Address, 453 const void *Decoder); 454 455 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 456 uint64_t Address, 457 const void *Decoder); 458 459 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 460 uint64_t Address, 461 const void *Decoder); 462 463 namespace llvm { 464 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 465 TheMips64elTarget; 466 } 467 468 static MCDisassembler *createMipsDisassembler( 469 const Target &T, 470 const MCSubtargetInfo &STI, 471 MCContext &Ctx) { 472 return new MipsDisassembler(STI, Ctx, true); 473 } 474 475 static MCDisassembler *createMipselDisassembler( 476 const Target &T, 477 const MCSubtargetInfo &STI, 478 MCContext &Ctx) { 479 return new MipsDisassembler(STI, Ctx, false); 480 } 481 482 extern "C" void LLVMInitializeMipsDisassembler() { 483 // Register the disassembler. 484 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 485 createMipsDisassembler); 486 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 487 createMipselDisassembler); 488 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 489 createMipsDisassembler); 490 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 491 createMipselDisassembler); 492 } 493 494 #include "MipsGenDisassemblerTables.inc" 495 496 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 497 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 498 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 499 return *(RegInfo->getRegClass(RC).begin() + RegNo); 500 } 501 502 template <typename InsnType> 503 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 504 const void *Decoder) { 505 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 506 // The size of the n field depends on the element size 507 // The register class also depends on this. 508 InsnType tmp = fieldFromInstruction(insn, 17, 5); 509 unsigned NSize = 0; 510 DecodeFN RegDecoder = nullptr; 511 if ((tmp & 0x18) == 0x00) { // INSVE_B 512 NSize = 4; 513 RegDecoder = DecodeMSA128BRegisterClass; 514 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 515 NSize = 3; 516 RegDecoder = DecodeMSA128HRegisterClass; 517 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 518 NSize = 2; 519 RegDecoder = DecodeMSA128WRegisterClass; 520 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 521 NSize = 1; 522 RegDecoder = DecodeMSA128DRegisterClass; 523 } else 524 llvm_unreachable("Invalid encoding"); 525 526 assert(NSize != 0 && RegDecoder != nullptr); 527 528 // $wd 529 tmp = fieldFromInstruction(insn, 6, 5); 530 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 531 return MCDisassembler::Fail; 532 // $wd_in 533 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 534 return MCDisassembler::Fail; 535 // $n 536 tmp = fieldFromInstruction(insn, 16, NSize); 537 MI.addOperand(MCOperand::createImm(tmp)); 538 // $ws 539 tmp = fieldFromInstruction(insn, 11, 5); 540 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 541 return MCDisassembler::Fail; 542 // $n2 543 MI.addOperand(MCOperand::createImm(0)); 544 545 return MCDisassembler::Success; 546 } 547 548 template <typename InsnType> 549 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 550 uint64_t Address, 551 const void *Decoder) { 552 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 553 // (otherwise we would have matched the ADDI instruction from the earlier 554 // ISA's instead). 555 // 556 // We have: 557 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 558 // BOVC if rs >= rt 559 // BEQZALC if rs == 0 && rt != 0 560 // BEQC if rs < rt && rs != 0 561 562 InsnType Rs = fieldFromInstruction(insn, 21, 5); 563 InsnType Rt = fieldFromInstruction(insn, 16, 5); 564 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 565 bool HasRs = false; 566 567 if (Rs >= Rt) { 568 MI.setOpcode(Mips::BOVC); 569 HasRs = true; 570 } else if (Rs != 0 && Rs < Rt) { 571 MI.setOpcode(Mips::BEQC); 572 HasRs = true; 573 } else 574 MI.setOpcode(Mips::BEQZALC); 575 576 if (HasRs) 577 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 578 Rs))); 579 580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 581 Rt))); 582 MI.addOperand(MCOperand::createImm(Imm)); 583 584 return MCDisassembler::Success; 585 } 586 587 template <typename InsnType> 588 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 589 uint64_t Address, 590 const void *Decoder) { 591 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 592 // (otherwise we would have matched the ADDI instruction from the earlier 593 // ISA's instead). 594 // 595 // We have: 596 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 597 // BNVC if rs >= rt 598 // BNEZALC if rs == 0 && rt != 0 599 // BNEC if rs < rt && rs != 0 600 601 InsnType Rs = fieldFromInstruction(insn, 21, 5); 602 InsnType Rt = fieldFromInstruction(insn, 16, 5); 603 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 604 bool HasRs = false; 605 606 if (Rs >= Rt) { 607 MI.setOpcode(Mips::BNVC); 608 HasRs = true; 609 } else if (Rs != 0 && Rs < Rt) { 610 MI.setOpcode(Mips::BNEC); 611 HasRs = true; 612 } else 613 MI.setOpcode(Mips::BNEZALC); 614 615 if (HasRs) 616 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 617 Rs))); 618 619 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 620 Rt))); 621 MI.addOperand(MCOperand::createImm(Imm)); 622 623 return MCDisassembler::Success; 624 } 625 626 template <typename InsnType> 627 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 628 uint64_t Address, 629 const void *Decoder) { 630 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 631 // (otherwise we would have matched the BLEZL instruction from the earlier 632 // ISA's instead). 633 // 634 // We have: 635 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 636 // Invalid if rs == 0 637 // BLEZC if rs == 0 && rt != 0 638 // BGEZC if rs == rt && rt != 0 639 // BGEC if rs != rt && rs != 0 && rt != 0 640 641 InsnType Rs = fieldFromInstruction(insn, 21, 5); 642 InsnType Rt = fieldFromInstruction(insn, 16, 5); 643 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 644 bool HasRs = false; 645 646 if (Rt == 0) 647 return MCDisassembler::Fail; 648 else if (Rs == 0) 649 MI.setOpcode(Mips::BLEZC); 650 else if (Rs == Rt) 651 MI.setOpcode(Mips::BGEZC); 652 else { 653 HasRs = true; 654 MI.setOpcode(Mips::BGEC); 655 } 656 657 if (HasRs) 658 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 659 Rs))); 660 661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 662 Rt))); 663 664 MI.addOperand(MCOperand::createImm(Imm)); 665 666 return MCDisassembler::Success; 667 } 668 669 template <typename InsnType> 670 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 671 uint64_t Address, 672 const void *Decoder) { 673 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 674 // (otherwise we would have matched the BGTZL instruction from the earlier 675 // ISA's instead). 676 // 677 // We have: 678 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 679 // Invalid if rs == 0 680 // BGTZC if rs == 0 && rt != 0 681 // BLTZC if rs == rt && rt != 0 682 // BLTC if rs != rt && rs != 0 && rt != 0 683 684 bool HasRs = false; 685 686 InsnType Rs = fieldFromInstruction(insn, 21, 5); 687 InsnType Rt = fieldFromInstruction(insn, 16, 5); 688 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 689 690 if (Rt == 0) 691 return MCDisassembler::Fail; 692 else if (Rs == 0) 693 MI.setOpcode(Mips::BGTZC); 694 else if (Rs == Rt) 695 MI.setOpcode(Mips::BLTZC); 696 else { 697 MI.setOpcode(Mips::BLTC); 698 HasRs = true; 699 } 700 701 if (HasRs) 702 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 703 Rs))); 704 705 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 706 Rt))); 707 708 MI.addOperand(MCOperand::createImm(Imm)); 709 710 return MCDisassembler::Success; 711 } 712 713 template <typename InsnType> 714 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 715 uint64_t Address, 716 const void *Decoder) { 717 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 718 // (otherwise we would have matched the BGTZ instruction from the earlier 719 // ISA's instead). 720 // 721 // We have: 722 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 723 // BGTZ if rt == 0 724 // BGTZALC if rs == 0 && rt != 0 725 // BLTZALC if rs != 0 && rs == rt 726 // BLTUC if rs != 0 && rs != rt 727 728 InsnType Rs = fieldFromInstruction(insn, 21, 5); 729 InsnType Rt = fieldFromInstruction(insn, 16, 5); 730 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 731 bool HasRs = false; 732 bool HasRt = false; 733 734 if (Rt == 0) { 735 MI.setOpcode(Mips::BGTZ); 736 HasRs = true; 737 } else if (Rs == 0) { 738 MI.setOpcode(Mips::BGTZALC); 739 HasRt = true; 740 } else if (Rs == Rt) { 741 MI.setOpcode(Mips::BLTZALC); 742 HasRs = true; 743 } else { 744 MI.setOpcode(Mips::BLTUC); 745 HasRs = true; 746 HasRt = true; 747 } 748 749 if (HasRs) 750 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 751 Rs))); 752 753 if (HasRt) 754 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 755 Rt))); 756 757 MI.addOperand(MCOperand::createImm(Imm)); 758 759 return MCDisassembler::Success; 760 } 761 762 template <typename InsnType> 763 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 764 uint64_t Address, 765 const void *Decoder) { 766 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 767 // (otherwise we would have matched the BLEZL instruction from the earlier 768 // ISA's instead). 769 // 770 // We have: 771 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 772 // Invalid if rs == 0 773 // BLEZALC if rs == 0 && rt != 0 774 // BGEZALC if rs == rt && rt != 0 775 // BGEUC if rs != rt && rs != 0 && rt != 0 776 777 InsnType Rs = fieldFromInstruction(insn, 21, 5); 778 InsnType Rt = fieldFromInstruction(insn, 16, 5); 779 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 780 bool HasRs = false; 781 782 if (Rt == 0) 783 return MCDisassembler::Fail; 784 else if (Rs == 0) 785 MI.setOpcode(Mips::BLEZALC); 786 else if (Rs == Rt) 787 MI.setOpcode(Mips::BGEZALC); 788 else { 789 HasRs = true; 790 MI.setOpcode(Mips::BGEUC); 791 } 792 793 if (HasRs) 794 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 795 Rs))); 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rt))); 798 799 MI.addOperand(MCOperand::createImm(Imm)); 800 801 return MCDisassembler::Success; 802 } 803 804 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 805 /// according to the given endianess. 806 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 807 uint64_t &Size, uint32_t &Insn, 808 bool IsBigEndian) { 809 // We want to read exactly 2 Bytes of data. 810 if (Bytes.size() < 2) { 811 Size = 0; 812 return MCDisassembler::Fail; 813 } 814 815 if (IsBigEndian) { 816 Insn = (Bytes[0] << 8) | Bytes[1]; 817 } else { 818 Insn = (Bytes[1] << 8) | Bytes[0]; 819 } 820 821 return MCDisassembler::Success; 822 } 823 824 /// Read four bytes from the ArrayRef and return 32 bit word sorted 825 /// according to the given endianess 826 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 827 uint64_t &Size, uint32_t &Insn, 828 bool IsBigEndian, bool IsMicroMips) { 829 // We want to read exactly 4 Bytes of data. 830 if (Bytes.size() < 4) { 831 Size = 0; 832 return MCDisassembler::Fail; 833 } 834 835 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 836 // always precede the low 16 bits in the instruction stream (that is, they 837 // are placed at lower addresses in the instruction stream). 838 // 839 // microMIPS byte ordering: 840 // Big-endian: 0 | 1 | 2 | 3 841 // Little-endian: 1 | 0 | 3 | 2 842 843 if (IsBigEndian) { 844 // Encoded as a big-endian 32-bit word in the stream. 845 Insn = 846 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 847 } else { 848 if (IsMicroMips) { 849 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 850 (Bytes[1] << 24); 851 } else { 852 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 853 (Bytes[3] << 24); 854 } 855 } 856 857 return MCDisassembler::Success; 858 } 859 860 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 861 ArrayRef<uint8_t> Bytes, 862 uint64_t Address, 863 raw_ostream &VStream, 864 raw_ostream &CStream) const { 865 uint32_t Insn; 866 DecodeStatus Result; 867 868 if (IsMicroMips) { 869 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 870 if (Result == MCDisassembler::Fail) 871 return MCDisassembler::Fail; 872 873 if (hasMips32r6()) { 874 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 875 // Calling the auto-generated decoder function for microMIPS32R6 876 // (and microMIPS64R6) 16-bit instructions. 877 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 878 Address, this, STI); 879 if (Result != MCDisassembler::Fail) { 880 Size = 2; 881 return Result; 882 } 883 } 884 885 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 886 // Calling the auto-generated decoder function for microMIPS 16-bit 887 // instructions. 888 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 889 this, STI); 890 if (Result != MCDisassembler::Fail) { 891 Size = 2; 892 return Result; 893 } 894 895 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 896 if (Result == MCDisassembler::Fail) 897 return MCDisassembler::Fail; 898 899 if (hasMips32r6()) { 900 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 901 // Calling the auto-generated decoder function. 902 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 903 this, STI); 904 if (Result != MCDisassembler::Fail) { 905 Size = 4; 906 return Result; 907 } 908 } 909 910 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 911 // Calling the auto-generated decoder function. 912 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 913 this, STI); 914 if (Result != MCDisassembler::Fail) { 915 Size = 4; 916 return Result; 917 } 918 // This is an invalid instruction. Let the disassembler move forward by the 919 // minimum instruction size. 920 Size = 2; 921 return MCDisassembler::Fail; 922 } 923 924 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 925 if (Result == MCDisassembler::Fail) { 926 Size = 4; 927 return MCDisassembler::Fail; 928 } 929 930 if (hasCOP3()) { 931 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 932 Result = 933 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 934 if (Result != MCDisassembler::Fail) { 935 Size = 4; 936 return Result; 937 } 938 } 939 940 if (hasMips32r6() && isGP64()) { 941 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 942 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 943 Address, this, STI); 944 if (Result != MCDisassembler::Fail) { 945 Size = 4; 946 return Result; 947 } 948 } 949 950 if (hasMips32r6()) { 951 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 952 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 953 Address, this, STI); 954 if (Result != MCDisassembler::Fail) { 955 Size = 4; 956 return Result; 957 } 958 } 959 960 if (hasCnMips()) { 961 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 962 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 963 Address, this, STI); 964 if (Result != MCDisassembler::Fail) { 965 Size = 4; 966 return Result; 967 } 968 } 969 970 if (isGP64()) { 971 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 972 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 973 Address, this, STI); 974 if (Result != MCDisassembler::Fail) { 975 Size = 4; 976 return Result; 977 } 978 } 979 980 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 981 // Calling the auto-generated decoder function. 982 Result = 983 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 984 if (Result != MCDisassembler::Fail) { 985 Size = 4; 986 return Result; 987 } 988 989 Size = 4; 990 return MCDisassembler::Fail; 991 } 992 993 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 994 unsigned RegNo, 995 uint64_t Address, 996 const void *Decoder) { 997 998 return MCDisassembler::Fail; 999 1000 } 1001 1002 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1003 unsigned RegNo, 1004 uint64_t Address, 1005 const void *Decoder) { 1006 1007 if (RegNo > 31) 1008 return MCDisassembler::Fail; 1009 1010 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1011 Inst.addOperand(MCOperand::createReg(Reg)); 1012 return MCDisassembler::Success; 1013 } 1014 1015 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1016 unsigned RegNo, 1017 uint64_t Address, 1018 const void *Decoder) { 1019 if (RegNo > 7) 1020 return MCDisassembler::Fail; 1021 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1022 Inst.addOperand(MCOperand::createReg(Reg)); 1023 return MCDisassembler::Success; 1024 } 1025 1026 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1027 unsigned RegNo, 1028 uint64_t Address, 1029 const void *Decoder) { 1030 if (RegNo > 7) 1031 return MCDisassembler::Fail; 1032 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1033 Inst.addOperand(MCOperand::createReg(Reg)); 1034 return MCDisassembler::Success; 1035 } 1036 1037 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1038 unsigned RegNo, 1039 uint64_t Address, 1040 const void *Decoder) { 1041 if (RegNo > 7) 1042 return MCDisassembler::Fail; 1043 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1044 Inst.addOperand(MCOperand::createReg(Reg)); 1045 return MCDisassembler::Success; 1046 } 1047 1048 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1049 unsigned RegNo, 1050 uint64_t Address, 1051 const void *Decoder) { 1052 if (RegNo > 31) 1053 return MCDisassembler::Fail; 1054 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1055 Inst.addOperand(MCOperand::createReg(Reg)); 1056 return MCDisassembler::Success; 1057 } 1058 1059 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1060 unsigned RegNo, 1061 uint64_t Address, 1062 const void *Decoder) { 1063 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1064 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1065 1066 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1067 } 1068 1069 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1070 unsigned RegNo, 1071 uint64_t Address, 1072 const void *Decoder) { 1073 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1074 } 1075 1076 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1077 unsigned RegNo, 1078 uint64_t Address, 1079 const void *Decoder) { 1080 if (RegNo > 31) 1081 return MCDisassembler::Fail; 1082 1083 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1084 Inst.addOperand(MCOperand::createReg(Reg)); 1085 return MCDisassembler::Success; 1086 } 1087 1088 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1089 unsigned RegNo, 1090 uint64_t Address, 1091 const void *Decoder) { 1092 if (RegNo > 31) 1093 return MCDisassembler::Fail; 1094 1095 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1096 Inst.addOperand(MCOperand::createReg(Reg)); 1097 return MCDisassembler::Success; 1098 } 1099 1100 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1101 unsigned RegNo, 1102 uint64_t Address, 1103 const void *Decoder) { 1104 if (RegNo > 31) 1105 return MCDisassembler::Fail; 1106 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1107 Inst.addOperand(MCOperand::createReg(Reg)); 1108 return MCDisassembler::Success; 1109 } 1110 1111 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1112 unsigned RegNo, 1113 uint64_t Address, 1114 const void *Decoder) { 1115 if (RegNo > 7) 1116 return MCDisassembler::Fail; 1117 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1118 Inst.addOperand(MCOperand::createReg(Reg)); 1119 return MCDisassembler::Success; 1120 } 1121 1122 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1123 uint64_t Address, 1124 const void *Decoder) { 1125 if (RegNo > 31) 1126 return MCDisassembler::Fail; 1127 1128 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1129 Inst.addOperand(MCOperand::createReg(Reg)); 1130 return MCDisassembler::Success; 1131 } 1132 1133 static DecodeStatus DecodeMem(MCInst &Inst, 1134 unsigned Insn, 1135 uint64_t Address, 1136 const void *Decoder) { 1137 int Offset = SignExtend32<16>(Insn & 0xffff); 1138 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1139 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1140 1141 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1142 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1143 1144 if (Inst.getOpcode() == Mips::SC || 1145 Inst.getOpcode() == Mips::SCD) 1146 Inst.addOperand(MCOperand::createReg(Reg)); 1147 1148 Inst.addOperand(MCOperand::createReg(Reg)); 1149 Inst.addOperand(MCOperand::createReg(Base)); 1150 Inst.addOperand(MCOperand::createImm(Offset)); 1151 1152 return MCDisassembler::Success; 1153 } 1154 1155 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1156 unsigned Insn, 1157 uint64_t Address, 1158 const void *Decoder) { 1159 int Offset = SignExtend32<9>(Insn >> 7); 1160 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1161 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1162 1163 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1164 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1165 1166 if (Inst.getOpcode() == Mips::SCE) 1167 Inst.addOperand(MCOperand::createReg(Reg)); 1168 1169 Inst.addOperand(MCOperand::createReg(Reg)); 1170 Inst.addOperand(MCOperand::createReg(Base)); 1171 Inst.addOperand(MCOperand::createImm(Offset)); 1172 1173 return MCDisassembler::Success; 1174 } 1175 1176 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1177 unsigned Insn, 1178 uint64_t Address, 1179 const void *Decoder) { 1180 int Offset = SignExtend32<9>(Insn & 0x1ff); 1181 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1182 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1183 1184 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1185 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1186 1187 Inst.addOperand(MCOperand::createReg(Reg)); 1188 Inst.addOperand(MCOperand::createReg(Base)); 1189 Inst.addOperand(MCOperand::createImm(Offset)); 1190 1191 return MCDisassembler::Success; 1192 } 1193 1194 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1195 unsigned Insn, 1196 uint64_t Address, 1197 const void *Decoder) { 1198 int Offset = SignExtend32<16>(Insn & 0xffff); 1199 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1200 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1201 1202 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1203 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1204 1205 Inst.addOperand(MCOperand::createReg(Reg)); 1206 Inst.addOperand(MCOperand::createReg(Base)); 1207 Inst.addOperand(MCOperand::createImm(Offset)); 1208 1209 return MCDisassembler::Success; 1210 } 1211 1212 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1213 unsigned Insn, 1214 uint64_t Address, 1215 const void *Decoder) { 1216 int Offset = SignExtend32<16>(Insn & 0xffff); 1217 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1218 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1219 1220 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1221 1222 Inst.addOperand(MCOperand::createReg(Base)); 1223 Inst.addOperand(MCOperand::createImm(Offset)); 1224 Inst.addOperand(MCOperand::createImm(Hint)); 1225 1226 return MCDisassembler::Success; 1227 } 1228 1229 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1230 unsigned Insn, 1231 uint64_t Address, 1232 const void *Decoder) { 1233 int Offset = SignExtend32<12>(Insn & 0xfff); 1234 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1235 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1236 1237 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1238 1239 Inst.addOperand(MCOperand::createReg(Base)); 1240 Inst.addOperand(MCOperand::createImm(Offset)); 1241 Inst.addOperand(MCOperand::createImm(Hint)); 1242 1243 return MCDisassembler::Success; 1244 } 1245 1246 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1247 unsigned Insn, 1248 uint64_t Address, 1249 const void *Decoder) { 1250 int Offset = SignExtend32<9>(Insn & 0x1ff); 1251 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1252 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1253 1254 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1255 1256 Inst.addOperand(MCOperand::createReg(Base)); 1257 Inst.addOperand(MCOperand::createImm(Offset)); 1258 Inst.addOperand(MCOperand::createImm(Hint)); 1259 1260 return MCDisassembler::Success; 1261 } 1262 1263 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1264 unsigned Insn, 1265 uint64_t Address, 1266 const void *Decoder) { 1267 int Offset = SignExtend32<9>(Insn >> 7); 1268 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1269 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1270 1271 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1272 1273 Inst.addOperand(MCOperand::createReg(Base)); 1274 Inst.addOperand(MCOperand::createImm(Offset)); 1275 Inst.addOperand(MCOperand::createImm(Hint)); 1276 1277 return MCDisassembler::Success; 1278 } 1279 1280 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1281 unsigned Insn, 1282 uint64_t Address, 1283 const void *Decoder) { 1284 int Offset = SignExtend32<9>(Insn & 0x1ff); 1285 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1286 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1287 1288 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1289 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1290 1291 Inst.addOperand(MCOperand::createReg(Reg)); 1292 Inst.addOperand(MCOperand::createReg(Base)); 1293 Inst.addOperand(MCOperand::createImm(Offset)); 1294 1295 return MCDisassembler::Success; 1296 } 1297 1298 static DecodeStatus DecodeSyncI(MCInst &Inst, 1299 unsigned Insn, 1300 uint64_t Address, 1301 const void *Decoder) { 1302 int Offset = SignExtend32<16>(Insn & 0xffff); 1303 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1304 1305 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1306 1307 Inst.addOperand(MCOperand::createReg(Base)); 1308 Inst.addOperand(MCOperand::createImm(Offset)); 1309 1310 return MCDisassembler::Success; 1311 } 1312 1313 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1314 unsigned Insn, 1315 uint64_t Address, 1316 const void *Decoder) { 1317 int Immediate = SignExtend32<16>(Insn & 0xffff); 1318 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1319 1320 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1321 1322 Inst.addOperand(MCOperand::createReg(Base)); 1323 Inst.addOperand(MCOperand::createImm(Immediate)); 1324 1325 return MCDisassembler::Success; 1326 } 1327 1328 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1329 uint64_t Address, const void *Decoder) { 1330 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1331 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1332 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1333 1334 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1335 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1336 1337 Inst.addOperand(MCOperand::createReg(Reg)); 1338 Inst.addOperand(MCOperand::createReg(Base)); 1339 1340 // The immediate field of an LD/ST instruction is scaled which means it must 1341 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1342 // data format. 1343 // .b - 1 byte 1344 // .h - 2 bytes 1345 // .w - 4 bytes 1346 // .d - 8 bytes 1347 switch(Inst.getOpcode()) 1348 { 1349 default: 1350 assert (0 && "Unexpected instruction"); 1351 return MCDisassembler::Fail; 1352 break; 1353 case Mips::LD_B: 1354 case Mips::ST_B: 1355 Inst.addOperand(MCOperand::createImm(Offset)); 1356 break; 1357 case Mips::LD_H: 1358 case Mips::ST_H: 1359 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1360 break; 1361 case Mips::LD_W: 1362 case Mips::ST_W: 1363 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1364 break; 1365 case Mips::LD_D: 1366 case Mips::ST_D: 1367 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1368 break; 1369 } 1370 1371 return MCDisassembler::Success; 1372 } 1373 1374 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1375 unsigned Insn, 1376 uint64_t Address, 1377 const void *Decoder) { 1378 unsigned Offset = Insn & 0xf; 1379 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1380 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1381 1382 switch (Inst.getOpcode()) { 1383 case Mips::LBU16_MM: 1384 case Mips::LHU16_MM: 1385 case Mips::LW16_MM: 1386 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1387 == MCDisassembler::Fail) 1388 return MCDisassembler::Fail; 1389 break; 1390 case Mips::SB16_MM: 1391 case Mips::SB16_MMR6: 1392 case Mips::SH16_MM: 1393 case Mips::SH16_MMR6: 1394 case Mips::SW16_MM: 1395 case Mips::SW16_MMR6: 1396 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1397 == MCDisassembler::Fail) 1398 return MCDisassembler::Fail; 1399 break; 1400 } 1401 1402 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1403 == MCDisassembler::Fail) 1404 return MCDisassembler::Fail; 1405 1406 switch (Inst.getOpcode()) { 1407 case Mips::LBU16_MM: 1408 if (Offset == 0xf) 1409 Inst.addOperand(MCOperand::createImm(-1)); 1410 else 1411 Inst.addOperand(MCOperand::createImm(Offset)); 1412 break; 1413 case Mips::SB16_MM: 1414 case Mips::SB16_MMR6: 1415 Inst.addOperand(MCOperand::createImm(Offset)); 1416 break; 1417 case Mips::LHU16_MM: 1418 case Mips::SH16_MM: 1419 case Mips::SH16_MMR6: 1420 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1421 break; 1422 case Mips::LW16_MM: 1423 case Mips::SW16_MM: 1424 case Mips::SW16_MMR6: 1425 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1426 break; 1427 } 1428 1429 return MCDisassembler::Success; 1430 } 1431 1432 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1433 unsigned Insn, 1434 uint64_t Address, 1435 const void *Decoder) { 1436 unsigned Offset = Insn & 0x1F; 1437 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1438 1439 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1440 1441 Inst.addOperand(MCOperand::createReg(Reg)); 1442 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1443 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1444 1445 return MCDisassembler::Success; 1446 } 1447 1448 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1449 unsigned Insn, 1450 uint64_t Address, 1451 const void *Decoder) { 1452 unsigned Offset = Insn & 0x7F; 1453 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1454 1455 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1456 1457 Inst.addOperand(MCOperand::createReg(Reg)); 1458 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1459 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1460 1461 return MCDisassembler::Success; 1462 } 1463 1464 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1465 unsigned Insn, 1466 uint64_t Address, 1467 const void *Decoder) { 1468 int Offset; 1469 switch (Inst.getOpcode()) { 1470 case Mips::LWM16_MMR6: 1471 case Mips::SWM16_MMR6: 1472 Offset = fieldFromInstruction(Insn, 4, 4); 1473 break; 1474 default: 1475 Offset = SignExtend32<4>(Insn & 0xf); 1476 break; 1477 } 1478 1479 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1480 == MCDisassembler::Fail) 1481 return MCDisassembler::Fail; 1482 1483 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1484 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1485 1486 return MCDisassembler::Success; 1487 } 1488 1489 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1490 unsigned Insn, 1491 uint64_t Address, 1492 const void *Decoder) { 1493 int Offset = SignExtend32<9>(Insn & 0x1ff); 1494 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1495 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1496 1497 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1498 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1499 1500 if (Inst.getOpcode() == Mips::SCE_MM) 1501 Inst.addOperand(MCOperand::createReg(Reg)); 1502 1503 Inst.addOperand(MCOperand::createReg(Reg)); 1504 Inst.addOperand(MCOperand::createReg(Base)); 1505 Inst.addOperand(MCOperand::createImm(Offset)); 1506 1507 return MCDisassembler::Success; 1508 } 1509 1510 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1511 unsigned Insn, 1512 uint64_t Address, 1513 const void *Decoder) { 1514 int Offset = SignExtend32<12>(Insn & 0x0fff); 1515 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1516 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1517 1518 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1519 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1520 1521 switch (Inst.getOpcode()) { 1522 case Mips::SWM32_MM: 1523 case Mips::LWM32_MM: 1524 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1525 == MCDisassembler::Fail) 1526 return MCDisassembler::Fail; 1527 Inst.addOperand(MCOperand::createReg(Base)); 1528 Inst.addOperand(MCOperand::createImm(Offset)); 1529 break; 1530 case Mips::SC_MM: 1531 Inst.addOperand(MCOperand::createReg(Reg)); 1532 // fallthrough 1533 default: 1534 Inst.addOperand(MCOperand::createReg(Reg)); 1535 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1536 Inst.addOperand(MCOperand::createReg(Reg+1)); 1537 1538 Inst.addOperand(MCOperand::createReg(Base)); 1539 Inst.addOperand(MCOperand::createImm(Offset)); 1540 } 1541 1542 return MCDisassembler::Success; 1543 } 1544 1545 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1546 unsigned Insn, 1547 uint64_t Address, 1548 const void *Decoder) { 1549 int Offset = SignExtend32<16>(Insn & 0xffff); 1550 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1551 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1552 1553 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1554 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1555 1556 Inst.addOperand(MCOperand::createReg(Reg)); 1557 Inst.addOperand(MCOperand::createReg(Base)); 1558 Inst.addOperand(MCOperand::createImm(Offset)); 1559 1560 return MCDisassembler::Success; 1561 } 1562 1563 static DecodeStatus DecodeFMem(MCInst &Inst, 1564 unsigned Insn, 1565 uint64_t Address, 1566 const void *Decoder) { 1567 int Offset = SignExtend32<16>(Insn & 0xffff); 1568 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1569 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1570 1571 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1572 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1573 1574 Inst.addOperand(MCOperand::createReg(Reg)); 1575 Inst.addOperand(MCOperand::createReg(Base)); 1576 Inst.addOperand(MCOperand::createImm(Offset)); 1577 1578 return MCDisassembler::Success; 1579 } 1580 1581 static DecodeStatus DecodeFMem2(MCInst &Inst, 1582 unsigned Insn, 1583 uint64_t Address, 1584 const void *Decoder) { 1585 int Offset = SignExtend32<16>(Insn & 0xffff); 1586 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1587 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1588 1589 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1590 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1591 1592 Inst.addOperand(MCOperand::createReg(Reg)); 1593 Inst.addOperand(MCOperand::createReg(Base)); 1594 Inst.addOperand(MCOperand::createImm(Offset)); 1595 1596 return MCDisassembler::Success; 1597 } 1598 1599 static DecodeStatus DecodeFMem3(MCInst &Inst, 1600 unsigned Insn, 1601 uint64_t Address, 1602 const void *Decoder) { 1603 int Offset = SignExtend32<16>(Insn & 0xffff); 1604 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1605 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1606 1607 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1608 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1609 1610 Inst.addOperand(MCOperand::createReg(Reg)); 1611 Inst.addOperand(MCOperand::createReg(Base)); 1612 Inst.addOperand(MCOperand::createImm(Offset)); 1613 1614 return MCDisassembler::Success; 1615 } 1616 1617 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1618 unsigned Insn, 1619 uint64_t Address, 1620 const void *Decoder) { 1621 int Offset = SignExtend32<11>(Insn & 0x07ff); 1622 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1623 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1624 1625 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1626 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1627 1628 Inst.addOperand(MCOperand::createReg(Reg)); 1629 Inst.addOperand(MCOperand::createReg(Base)); 1630 Inst.addOperand(MCOperand::createImm(Offset)); 1631 1632 return MCDisassembler::Success; 1633 } 1634 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1635 unsigned Insn, 1636 uint64_t Address, 1637 const void *Decoder) { 1638 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1639 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1640 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1641 1642 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1643 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1644 1645 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1646 Inst.addOperand(MCOperand::createReg(Rt)); 1647 } 1648 1649 Inst.addOperand(MCOperand::createReg(Rt)); 1650 Inst.addOperand(MCOperand::createReg(Base)); 1651 Inst.addOperand(MCOperand::createImm(Offset)); 1652 1653 return MCDisassembler::Success; 1654 } 1655 1656 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1657 unsigned RegNo, 1658 uint64_t Address, 1659 const void *Decoder) { 1660 // Currently only hardware register 29 is supported. 1661 if (RegNo != 29) 1662 return MCDisassembler::Fail; 1663 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1664 return MCDisassembler::Success; 1665 } 1666 1667 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1668 unsigned RegNo, 1669 uint64_t Address, 1670 const void *Decoder) { 1671 if (RegNo > 30 || RegNo %2) 1672 return MCDisassembler::Fail; 1673 1674 ; 1675 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1676 Inst.addOperand(MCOperand::createReg(Reg)); 1677 return MCDisassembler::Success; 1678 } 1679 1680 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1681 unsigned RegNo, 1682 uint64_t Address, 1683 const void *Decoder) { 1684 if (RegNo >= 4) 1685 return MCDisassembler::Fail; 1686 1687 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1688 Inst.addOperand(MCOperand::createReg(Reg)); 1689 return MCDisassembler::Success; 1690 } 1691 1692 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1693 unsigned RegNo, 1694 uint64_t Address, 1695 const void *Decoder) { 1696 if (RegNo >= 4) 1697 return MCDisassembler::Fail; 1698 1699 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1700 Inst.addOperand(MCOperand::createReg(Reg)); 1701 return MCDisassembler::Success; 1702 } 1703 1704 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1705 unsigned RegNo, 1706 uint64_t Address, 1707 const void *Decoder) { 1708 if (RegNo >= 4) 1709 return MCDisassembler::Fail; 1710 1711 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1712 Inst.addOperand(MCOperand::createReg(Reg)); 1713 return MCDisassembler::Success; 1714 } 1715 1716 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1717 unsigned RegNo, 1718 uint64_t Address, 1719 const void *Decoder) { 1720 if (RegNo > 31) 1721 return MCDisassembler::Fail; 1722 1723 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1724 Inst.addOperand(MCOperand::createReg(Reg)); 1725 return MCDisassembler::Success; 1726 } 1727 1728 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1729 unsigned RegNo, 1730 uint64_t Address, 1731 const void *Decoder) { 1732 if (RegNo > 31) 1733 return MCDisassembler::Fail; 1734 1735 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1736 Inst.addOperand(MCOperand::createReg(Reg)); 1737 return MCDisassembler::Success; 1738 } 1739 1740 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1741 unsigned RegNo, 1742 uint64_t Address, 1743 const void *Decoder) { 1744 if (RegNo > 31) 1745 return MCDisassembler::Fail; 1746 1747 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1748 Inst.addOperand(MCOperand::createReg(Reg)); 1749 return MCDisassembler::Success; 1750 } 1751 1752 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1753 unsigned RegNo, 1754 uint64_t Address, 1755 const void *Decoder) { 1756 if (RegNo > 31) 1757 return MCDisassembler::Fail; 1758 1759 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1760 Inst.addOperand(MCOperand::createReg(Reg)); 1761 return MCDisassembler::Success; 1762 } 1763 1764 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1765 unsigned RegNo, 1766 uint64_t Address, 1767 const void *Decoder) { 1768 if (RegNo > 7) 1769 return MCDisassembler::Fail; 1770 1771 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1772 Inst.addOperand(MCOperand::createReg(Reg)); 1773 return MCDisassembler::Success; 1774 } 1775 1776 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1777 unsigned RegNo, 1778 uint64_t Address, 1779 const void *Decoder) { 1780 if (RegNo > 31) 1781 return MCDisassembler::Fail; 1782 1783 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1784 Inst.addOperand(MCOperand::createReg(Reg)); 1785 return MCDisassembler::Success; 1786 } 1787 1788 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1789 unsigned RegNo, 1790 uint64_t Address, 1791 const void *Decoder) { 1792 if (RegNo > 31) 1793 return MCDisassembler::Fail; 1794 1795 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1796 Inst.addOperand(MCOperand::createReg(Reg)); 1797 return MCDisassembler::Success; 1798 } 1799 1800 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1801 unsigned Offset, 1802 uint64_t Address, 1803 const void *Decoder) { 1804 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1805 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1806 return MCDisassembler::Success; 1807 } 1808 1809 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1810 unsigned Insn, 1811 uint64_t Address, 1812 const void *Decoder) { 1813 1814 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1815 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1816 return MCDisassembler::Success; 1817 } 1818 1819 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1820 unsigned Offset, 1821 uint64_t Address, 1822 const void *Decoder) { 1823 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1824 1825 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1830 unsigned Offset, 1831 uint64_t Address, 1832 const void *Decoder) { 1833 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1834 1835 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1836 return MCDisassembler::Success; 1837 } 1838 1839 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1840 unsigned Offset, 1841 uint64_t Address, 1842 const void *Decoder) { 1843 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1844 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1845 return MCDisassembler::Success; 1846 } 1847 1848 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1849 unsigned Offset, 1850 uint64_t Address, 1851 const void *Decoder) { 1852 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1853 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1854 return MCDisassembler::Success; 1855 } 1856 1857 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1858 unsigned Offset, 1859 uint64_t Address, 1860 const void *Decoder) { 1861 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1862 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1863 return MCDisassembler::Success; 1864 } 1865 1866 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1867 unsigned Insn, 1868 uint64_t Address, 1869 const void *Decoder) { 1870 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1871 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1872 return MCDisassembler::Success; 1873 } 1874 1875 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1876 unsigned Value, 1877 uint64_t Address, 1878 const void *Decoder) { 1879 if (Value == 0) 1880 Inst.addOperand(MCOperand::createImm(1)); 1881 else if (Value == 0x7) 1882 Inst.addOperand(MCOperand::createImm(-1)); 1883 else 1884 Inst.addOperand(MCOperand::createImm(Value << 2)); 1885 return MCDisassembler::Success; 1886 } 1887 1888 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1889 unsigned Value, 1890 uint64_t Address, 1891 const void *Decoder) { 1892 Inst.addOperand(MCOperand::createImm(Value << 2)); 1893 return MCDisassembler::Success; 1894 } 1895 1896 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1897 unsigned Value, 1898 uint64_t Address, 1899 const void *Decoder) { 1900 if (Value == 0x7F) 1901 Inst.addOperand(MCOperand::createImm(-1)); 1902 else 1903 Inst.addOperand(MCOperand::createImm(Value)); 1904 return MCDisassembler::Success; 1905 } 1906 1907 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1908 unsigned Value, 1909 uint64_t Address, 1910 const void *Decoder) { 1911 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1912 return MCDisassembler::Success; 1913 } 1914 1915 static DecodeStatus DecodeSimm4(MCInst &Inst, 1916 unsigned Value, 1917 uint64_t Address, 1918 const void *Decoder) { 1919 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); 1920 return MCDisassembler::Success; 1921 } 1922 1923 static DecodeStatus DecodeSimm16(MCInst &Inst, 1924 unsigned Insn, 1925 uint64_t Address, 1926 const void *Decoder) { 1927 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); 1928 return MCDisassembler::Success; 1929 } 1930 1931 template <unsigned Bits, int Offset> 1932 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 1933 uint64_t Address, 1934 const void *Decoder) { 1935 Value &= ((1 << Bits) - 1); 1936 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1937 return MCDisassembler::Success; 1938 } 1939 1940 static DecodeStatus DecodeInsSize(MCInst &Inst, 1941 unsigned Insn, 1942 uint64_t Address, 1943 const void *Decoder) { 1944 // First we need to grab the pos(lsb) from MCInst. 1945 int Pos = Inst.getOperand(2).getImm(); 1946 int Size = (int) Insn - Pos + 1; 1947 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1948 return MCDisassembler::Success; 1949 } 1950 1951 static DecodeStatus DecodeExtSize(MCInst &Inst, 1952 unsigned Insn, 1953 uint64_t Address, 1954 const void *Decoder) { 1955 int Size = (int) Insn + 1; 1956 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1957 return MCDisassembler::Success; 1958 } 1959 1960 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1961 uint64_t Address, const void *Decoder) { 1962 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1963 return MCDisassembler::Success; 1964 } 1965 1966 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1967 uint64_t Address, const void *Decoder) { 1968 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1969 return MCDisassembler::Success; 1970 } 1971 1972 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1973 uint64_t Address, const void *Decoder) { 1974 int32_t DecodedValue; 1975 switch (Insn) { 1976 case 0: DecodedValue = 256; break; 1977 case 1: DecodedValue = 257; break; 1978 case 510: DecodedValue = -258; break; 1979 case 511: DecodedValue = -257; break; 1980 default: DecodedValue = SignExtend32<9>(Insn); break; 1981 } 1982 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1983 return MCDisassembler::Success; 1984 } 1985 1986 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1987 uint64_t Address, const void *Decoder) { 1988 // Insn must be >= 0, since it is unsigned that condition is always true. 1989 assert(Insn < 16); 1990 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1991 255, 32768, 65535}; 1992 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 1993 return MCDisassembler::Success; 1994 } 1995 1996 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1997 uint64_t Address, const void *Decoder) { 1998 Inst.addOperand(MCOperand::createImm(Insn << 2)); 1999 return MCDisassembler::Success; 2000 } 2001 2002 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2003 unsigned Insn, 2004 uint64_t Address, 2005 const void *Decoder) { 2006 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2007 Mips::S6, Mips::S7, Mips::FP}; 2008 unsigned RegNum; 2009 2010 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2011 2012 // Empty register lists are not allowed. 2013 if (RegLst == 0) 2014 return MCDisassembler::Fail; 2015 2016 RegNum = RegLst & 0xf; 2017 2018 // RegLst values 10-15, and 26-31 are reserved. 2019 if (RegNum > 9) 2020 return MCDisassembler::Fail; 2021 2022 for (unsigned i = 0; i < RegNum; i++) 2023 Inst.addOperand(MCOperand::createReg(Regs[i])); 2024 2025 if (RegLst & 0x10) 2026 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2027 2028 return MCDisassembler::Success; 2029 } 2030 2031 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2032 uint64_t Address, 2033 const void *Decoder) { 2034 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2035 unsigned RegLst; 2036 switch(Inst.getOpcode()) { 2037 default: 2038 RegLst = fieldFromInstruction(Insn, 4, 2); 2039 break; 2040 case Mips::LWM16_MMR6: 2041 case Mips::SWM16_MMR6: 2042 RegLst = fieldFromInstruction(Insn, 8, 2); 2043 break; 2044 } 2045 unsigned RegNum = RegLst & 0x3; 2046 2047 for (unsigned i = 0; i <= RegNum; i++) 2048 Inst.addOperand(MCOperand::createReg(Regs[i])); 2049 2050 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2051 2052 return MCDisassembler::Success; 2053 } 2054 2055 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2056 uint64_t Address, const void *Decoder) { 2057 2058 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2059 2060 switch (RegPair) { 2061 default: 2062 return MCDisassembler::Fail; 2063 case 0: 2064 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2065 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2066 break; 2067 case 1: 2068 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2069 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2070 break; 2071 case 2: 2072 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2073 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2074 break; 2075 case 3: 2076 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2077 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2078 break; 2079 case 4: 2080 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2081 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2082 break; 2083 case 5: 2084 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2085 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2086 break; 2087 case 6: 2088 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2089 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2090 break; 2091 case 7: 2092 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2093 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2094 break; 2095 } 2096 2097 return MCDisassembler::Success; 2098 } 2099 2100 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2101 uint64_t Address, const void *Decoder) { 2102 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2103 return MCDisassembler::Success; 2104 } 2105