1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 49 50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 51 52 bool hasCOP3() const { 53 // Only present in MIPS-I and MIPS-II 54 return !hasMips32() && !hasMips3(); 55 } 56 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 }; 62 63 } // end anonymous namespace 64 65 // Forward declare these because the autogenerated code will reference them. 66 // Definitions are further down. 67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 68 unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 78 unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 132 unsigned Insn, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 142 unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 147 unsigned RegNo, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 192 unsigned Offset, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 202 unsigned Offset, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 212 // shifted left by 1 bit. 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 235 unsigned Offset, 236 uint64_t Address, 237 const void *Decoder); 238 239 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 240 // shifted left by 1 bit. 241 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 242 unsigned Insn, 243 uint64_t Address, 244 const void *Decoder); 245 246 static DecodeStatus DecodeMem(MCInst &Inst, 247 unsigned Insn, 248 uint64_t Address, 249 const void *Decoder); 250 251 static DecodeStatus DecodeMemEVA(MCInst &Inst, 252 unsigned Insn, 253 uint64_t Address, 254 const void *Decoder); 255 256 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 257 unsigned Insn, 258 uint64_t Address, 259 const void *Decoder); 260 261 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 262 unsigned Insn, 263 uint64_t Address, 264 const void *Decoder); 265 266 static DecodeStatus DecodeCacheOp(MCInst &Inst, 267 unsigned Insn, 268 uint64_t Address, 269 const void *Decoder); 270 271 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 272 unsigned Insn, 273 uint64_t Address, 274 const void *Decoder); 275 276 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 277 unsigned Insn, 278 uint64_t Address, 279 const void *Decoder); 280 281 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 282 unsigned Insn, 283 uint64_t Address, 284 const void *Decoder); 285 286 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 287 unsigned Insn, 288 uint64_t Address, 289 const void *Decoder); 290 291 static DecodeStatus DecodeSyncI(MCInst &Inst, 292 unsigned Insn, 293 uint64_t Address, 294 const void *Decoder); 295 296 static DecodeStatus DecodeSynciR6(MCInst &Inst, 297 unsigned Insn, 298 uint64_t Address, 299 const void *Decoder); 300 301 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 304 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 305 unsigned Insn, 306 uint64_t Address, 307 const void *Decoder); 308 309 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 310 unsigned Insn, 311 uint64_t Address, 312 const void *Decoder); 313 314 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 315 unsigned Insn, 316 uint64_t Address, 317 const void *Decoder); 318 319 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 320 unsigned Insn, 321 uint64_t Address, 322 const void *Decoder); 323 324 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 325 unsigned Insn, 326 uint64_t Address, 327 const void *Decoder); 328 329 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 330 unsigned Insn, 331 uint64_t Address, 332 const void *Decoder); 333 334 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 335 unsigned Insn, 336 uint64_t Address, 337 const void *Decoder); 338 339 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 344 uint64_t Address, 345 const void *Decoder); 346 347 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 352 uint64_t Address, 353 const void *Decoder); 354 355 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 356 unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 361 unsigned Value, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 366 unsigned Value, 367 uint64_t Address, 368 const void *Decoder); 369 370 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 371 unsigned Value, 372 uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 376 unsigned Value, 377 uint64_t Address, 378 const void *Decoder); 379 380 static DecodeStatus DecodeSimm4(MCInst &Inst, 381 unsigned Value, 382 uint64_t Address, 383 const void *Decoder); 384 385 static DecodeStatus DecodeSimm16(MCInst &Inst, 386 unsigned Insn, 387 uint64_t Address, 388 const void *Decoder); 389 390 template <unsigned Bits, int Offset> 391 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 392 uint64_t Address, const void *Decoder); 393 394 static DecodeStatus DecodeInsSize(MCInst &Inst, 395 unsigned Insn, 396 uint64_t Address, 397 const void *Decoder); 398 399 static DecodeStatus DecodeExtSize(MCInst &Inst, 400 unsigned Insn, 401 uint64_t Address, 402 const void *Decoder); 403 404 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 405 uint64_t Address, const void *Decoder); 406 407 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 408 uint64_t Address, const void *Decoder); 409 410 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 411 uint64_t Address, const void *Decoder); 412 413 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 414 uint64_t Address, const void *Decoder); 415 416 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 417 uint64_t Address, const void *Decoder); 418 419 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 420 uint64_t Address, const void *Decoder); 421 422 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 423 /// handle. 424 template <typename InsnType> 425 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 426 const void *Decoder); 427 428 template <typename InsnType> 429 static DecodeStatus 430 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 431 const void *Decoder); 432 433 template <typename InsnType> 434 static DecodeStatus 435 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 436 const void *Decoder); 437 438 template <typename InsnType> 439 static DecodeStatus 440 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 441 const void *Decoder); 442 443 template <typename InsnType> 444 static DecodeStatus 445 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 446 const void *Decoder); 447 448 template <typename InsnType> 449 static DecodeStatus 450 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 451 const void *Decoder); 452 453 template <typename InsnType> 454 static DecodeStatus 455 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 459 uint64_t Address, 460 const void *Decoder); 461 462 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 463 uint64_t Address, 464 const void *Decoder); 465 466 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 467 uint64_t Address, 468 const void *Decoder); 469 470 namespace llvm { 471 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 472 TheMips64elTarget; 473 } 474 475 static MCDisassembler *createMipsDisassembler( 476 const Target &T, 477 const MCSubtargetInfo &STI, 478 MCContext &Ctx) { 479 return new MipsDisassembler(STI, Ctx, true); 480 } 481 482 static MCDisassembler *createMipselDisassembler( 483 const Target &T, 484 const MCSubtargetInfo &STI, 485 MCContext &Ctx) { 486 return new MipsDisassembler(STI, Ctx, false); 487 } 488 489 extern "C" void LLVMInitializeMipsDisassembler() { 490 // Register the disassembler. 491 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 492 createMipsDisassembler); 493 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 494 createMipselDisassembler); 495 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 496 createMipsDisassembler); 497 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 498 createMipselDisassembler); 499 } 500 501 #include "MipsGenDisassemblerTables.inc" 502 503 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 504 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 505 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 506 return *(RegInfo->getRegClass(RC).begin() + RegNo); 507 } 508 509 template <typename InsnType> 510 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 511 const void *Decoder) { 512 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 513 // The size of the n field depends on the element size 514 // The register class also depends on this. 515 InsnType tmp = fieldFromInstruction(insn, 17, 5); 516 unsigned NSize = 0; 517 DecodeFN RegDecoder = nullptr; 518 if ((tmp & 0x18) == 0x00) { // INSVE_B 519 NSize = 4; 520 RegDecoder = DecodeMSA128BRegisterClass; 521 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 522 NSize = 3; 523 RegDecoder = DecodeMSA128HRegisterClass; 524 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 525 NSize = 2; 526 RegDecoder = DecodeMSA128WRegisterClass; 527 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 528 NSize = 1; 529 RegDecoder = DecodeMSA128DRegisterClass; 530 } else 531 llvm_unreachable("Invalid encoding"); 532 533 assert(NSize != 0 && RegDecoder != nullptr); 534 535 // $wd 536 tmp = fieldFromInstruction(insn, 6, 5); 537 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 538 return MCDisassembler::Fail; 539 // $wd_in 540 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 541 return MCDisassembler::Fail; 542 // $n 543 tmp = fieldFromInstruction(insn, 16, NSize); 544 MI.addOperand(MCOperand::createImm(tmp)); 545 // $ws 546 tmp = fieldFromInstruction(insn, 11, 5); 547 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 548 return MCDisassembler::Fail; 549 // $n2 550 MI.addOperand(MCOperand::createImm(0)); 551 552 return MCDisassembler::Success; 553 } 554 555 template <typename InsnType> 556 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 557 uint64_t Address, 558 const void *Decoder) { 559 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 560 // (otherwise we would have matched the ADDI instruction from the earlier 561 // ISA's instead). 562 // 563 // We have: 564 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 565 // BOVC if rs >= rt 566 // BEQZALC if rs == 0 && rt != 0 567 // BEQC if rs < rt && rs != 0 568 569 InsnType Rs = fieldFromInstruction(insn, 21, 5); 570 InsnType Rt = fieldFromInstruction(insn, 16, 5); 571 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 572 bool HasRs = false; 573 574 if (Rs >= Rt) { 575 MI.setOpcode(Mips::BOVC); 576 HasRs = true; 577 } else if (Rs != 0 && Rs < Rt) { 578 MI.setOpcode(Mips::BEQC); 579 HasRs = true; 580 } else 581 MI.setOpcode(Mips::BEQZALC); 582 583 if (HasRs) 584 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 585 Rs))); 586 587 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 588 Rt))); 589 MI.addOperand(MCOperand::createImm(Imm)); 590 591 return MCDisassembler::Success; 592 } 593 594 template <typename InsnType> 595 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 596 uint64_t Address, 597 const void *Decoder) { 598 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 599 // (otherwise we would have matched the ADDI instruction from the earlier 600 // ISA's instead). 601 // 602 // We have: 603 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 604 // BNVC if rs >= rt 605 // BNEZALC if rs == 0 && rt != 0 606 // BNEC if rs < rt && rs != 0 607 608 InsnType Rs = fieldFromInstruction(insn, 21, 5); 609 InsnType Rt = fieldFromInstruction(insn, 16, 5); 610 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 611 bool HasRs = false; 612 613 if (Rs >= Rt) { 614 MI.setOpcode(Mips::BNVC); 615 HasRs = true; 616 } else if (Rs != 0 && Rs < Rt) { 617 MI.setOpcode(Mips::BNEC); 618 HasRs = true; 619 } else 620 MI.setOpcode(Mips::BNEZALC); 621 622 if (HasRs) 623 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 624 Rs))); 625 626 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 627 Rt))); 628 MI.addOperand(MCOperand::createImm(Imm)); 629 630 return MCDisassembler::Success; 631 } 632 633 template <typename InsnType> 634 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 635 uint64_t Address, 636 const void *Decoder) { 637 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 638 // (otherwise we would have matched the BLEZL instruction from the earlier 639 // ISA's instead). 640 // 641 // We have: 642 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 643 // Invalid if rs == 0 644 // BLEZC if rs == 0 && rt != 0 645 // BGEZC if rs == rt && rt != 0 646 // BGEC if rs != rt && rs != 0 && rt != 0 647 648 InsnType Rs = fieldFromInstruction(insn, 21, 5); 649 InsnType Rt = fieldFromInstruction(insn, 16, 5); 650 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 651 bool HasRs = false; 652 653 if (Rt == 0) 654 return MCDisassembler::Fail; 655 else if (Rs == 0) 656 MI.setOpcode(Mips::BLEZC); 657 else if (Rs == Rt) 658 MI.setOpcode(Mips::BGEZC); 659 else { 660 HasRs = true; 661 MI.setOpcode(Mips::BGEC); 662 } 663 664 if (HasRs) 665 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 666 Rs))); 667 668 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 669 Rt))); 670 671 MI.addOperand(MCOperand::createImm(Imm)); 672 673 return MCDisassembler::Success; 674 } 675 676 template <typename InsnType> 677 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 678 uint64_t Address, 679 const void *Decoder) { 680 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 681 // (otherwise we would have matched the BGTZL instruction from the earlier 682 // ISA's instead). 683 // 684 // We have: 685 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 686 // Invalid if rs == 0 687 // BGTZC if rs == 0 && rt != 0 688 // BLTZC if rs == rt && rt != 0 689 // BLTC if rs != rt && rs != 0 && rt != 0 690 691 bool HasRs = false; 692 693 InsnType Rs = fieldFromInstruction(insn, 21, 5); 694 InsnType Rt = fieldFromInstruction(insn, 16, 5); 695 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 696 697 if (Rt == 0) 698 return MCDisassembler::Fail; 699 else if (Rs == 0) 700 MI.setOpcode(Mips::BGTZC); 701 else if (Rs == Rt) 702 MI.setOpcode(Mips::BLTZC); 703 else { 704 MI.setOpcode(Mips::BLTC); 705 HasRs = true; 706 } 707 708 if (HasRs) 709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 710 Rs))); 711 712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 713 Rt))); 714 715 MI.addOperand(MCOperand::createImm(Imm)); 716 717 return MCDisassembler::Success; 718 } 719 720 template <typename InsnType> 721 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 722 uint64_t Address, 723 const void *Decoder) { 724 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 725 // (otherwise we would have matched the BGTZ instruction from the earlier 726 // ISA's instead). 727 // 728 // We have: 729 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 730 // BGTZ if rt == 0 731 // BGTZALC if rs == 0 && rt != 0 732 // BLTZALC if rs != 0 && rs == rt 733 // BLTUC if rs != 0 && rs != rt 734 735 InsnType Rs = fieldFromInstruction(insn, 21, 5); 736 InsnType Rt = fieldFromInstruction(insn, 16, 5); 737 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 738 bool HasRs = false; 739 bool HasRt = false; 740 741 if (Rt == 0) { 742 MI.setOpcode(Mips::BGTZ); 743 HasRs = true; 744 } else if (Rs == 0) { 745 MI.setOpcode(Mips::BGTZALC); 746 HasRt = true; 747 } else if (Rs == Rt) { 748 MI.setOpcode(Mips::BLTZALC); 749 HasRs = true; 750 } else { 751 MI.setOpcode(Mips::BLTUC); 752 HasRs = true; 753 HasRt = true; 754 } 755 756 if (HasRs) 757 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 758 Rs))); 759 760 if (HasRt) 761 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 762 Rt))); 763 764 MI.addOperand(MCOperand::createImm(Imm)); 765 766 return MCDisassembler::Success; 767 } 768 769 template <typename InsnType> 770 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 771 uint64_t Address, 772 const void *Decoder) { 773 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 774 // (otherwise we would have matched the BLEZL instruction from the earlier 775 // ISA's instead). 776 // 777 // We have: 778 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 779 // Invalid if rs == 0 780 // BLEZALC if rs == 0 && rt != 0 781 // BGEZALC if rs == rt && rt != 0 782 // BGEUC if rs != rt && rs != 0 && rt != 0 783 784 InsnType Rs = fieldFromInstruction(insn, 21, 5); 785 InsnType Rt = fieldFromInstruction(insn, 16, 5); 786 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 787 bool HasRs = false; 788 789 if (Rt == 0) 790 return MCDisassembler::Fail; 791 else if (Rs == 0) 792 MI.setOpcode(Mips::BLEZALC); 793 else if (Rs == Rt) 794 MI.setOpcode(Mips::BGEZALC); 795 else { 796 HasRs = true; 797 MI.setOpcode(Mips::BGEUC); 798 } 799 800 if (HasRs) 801 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 802 Rs))); 803 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 804 Rt))); 805 806 MI.addOperand(MCOperand::createImm(Imm)); 807 808 return MCDisassembler::Success; 809 } 810 811 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 812 /// according to the given endianess. 813 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 814 uint64_t &Size, uint32_t &Insn, 815 bool IsBigEndian) { 816 // We want to read exactly 2 Bytes of data. 817 if (Bytes.size() < 2) { 818 Size = 0; 819 return MCDisassembler::Fail; 820 } 821 822 if (IsBigEndian) { 823 Insn = (Bytes[0] << 8) | Bytes[1]; 824 } else { 825 Insn = (Bytes[1] << 8) | Bytes[0]; 826 } 827 828 return MCDisassembler::Success; 829 } 830 831 /// Read four bytes from the ArrayRef and return 32 bit word sorted 832 /// according to the given endianess 833 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 834 uint64_t &Size, uint32_t &Insn, 835 bool IsBigEndian, bool IsMicroMips) { 836 // We want to read exactly 4 Bytes of data. 837 if (Bytes.size() < 4) { 838 Size = 0; 839 return MCDisassembler::Fail; 840 } 841 842 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 843 // always precede the low 16 bits in the instruction stream (that is, they 844 // are placed at lower addresses in the instruction stream). 845 // 846 // microMIPS byte ordering: 847 // Big-endian: 0 | 1 | 2 | 3 848 // Little-endian: 1 | 0 | 3 | 2 849 850 if (IsBigEndian) { 851 // Encoded as a big-endian 32-bit word in the stream. 852 Insn = 853 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 854 } else { 855 if (IsMicroMips) { 856 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 857 (Bytes[1] << 24); 858 } else { 859 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 860 (Bytes[3] << 24); 861 } 862 } 863 864 return MCDisassembler::Success; 865 } 866 867 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 868 ArrayRef<uint8_t> Bytes, 869 uint64_t Address, 870 raw_ostream &VStream, 871 raw_ostream &CStream) const { 872 uint32_t Insn; 873 DecodeStatus Result; 874 875 if (IsMicroMips) { 876 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 877 if (Result == MCDisassembler::Fail) 878 return MCDisassembler::Fail; 879 880 if (hasMips32r6()) { 881 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 882 // Calling the auto-generated decoder function for microMIPS32R6 883 // (and microMIPS64R6) 16-bit instructions. 884 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 885 Address, this, STI); 886 if (Result != MCDisassembler::Fail) { 887 Size = 2; 888 return Result; 889 } 890 } 891 892 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 893 // Calling the auto-generated decoder function for microMIPS 16-bit 894 // instructions. 895 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 896 this, STI); 897 if (Result != MCDisassembler::Fail) { 898 Size = 2; 899 return Result; 900 } 901 902 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 903 if (Result == MCDisassembler::Fail) 904 return MCDisassembler::Fail; 905 906 if (hasMips32r6()) { 907 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 908 // Calling the auto-generated decoder function. 909 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 910 this, STI); 911 if (Result != MCDisassembler::Fail) { 912 Size = 4; 913 return Result; 914 } 915 } 916 917 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 918 // Calling the auto-generated decoder function. 919 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 920 this, STI); 921 if (Result != MCDisassembler::Fail) { 922 Size = 4; 923 return Result; 924 } 925 // This is an invalid instruction. Let the disassembler move forward by the 926 // minimum instruction size. 927 Size = 2; 928 return MCDisassembler::Fail; 929 } 930 931 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 932 if (Result == MCDisassembler::Fail) { 933 Size = 4; 934 return MCDisassembler::Fail; 935 } 936 937 if (hasCOP3()) { 938 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 939 Result = 940 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 941 if (Result != MCDisassembler::Fail) { 942 Size = 4; 943 return Result; 944 } 945 } 946 947 if (hasMips32r6() && isGP64()) { 948 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 949 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 950 Address, this, STI); 951 if (Result != MCDisassembler::Fail) { 952 Size = 4; 953 return Result; 954 } 955 } 956 957 if (hasMips32r6()) { 958 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 959 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 960 Address, this, STI); 961 if (Result != MCDisassembler::Fail) { 962 Size = 4; 963 return Result; 964 } 965 } 966 967 if (hasCnMips()) { 968 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 969 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 970 Address, this, STI); 971 if (Result != MCDisassembler::Fail) { 972 Size = 4; 973 return Result; 974 } 975 } 976 977 if (isGP64()) { 978 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 979 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 980 Address, this, STI); 981 if (Result != MCDisassembler::Fail) { 982 Size = 4; 983 return Result; 984 } 985 } 986 987 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 988 // Calling the auto-generated decoder function. 989 Result = 990 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 991 if (Result != MCDisassembler::Fail) { 992 Size = 4; 993 return Result; 994 } 995 996 Size = 4; 997 return MCDisassembler::Fail; 998 } 999 1000 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1001 unsigned RegNo, 1002 uint64_t Address, 1003 const void *Decoder) { 1004 1005 return MCDisassembler::Fail; 1006 1007 } 1008 1009 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1010 unsigned RegNo, 1011 uint64_t Address, 1012 const void *Decoder) { 1013 1014 if (RegNo > 31) 1015 return MCDisassembler::Fail; 1016 1017 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1018 Inst.addOperand(MCOperand::createReg(Reg)); 1019 return MCDisassembler::Success; 1020 } 1021 1022 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1023 unsigned RegNo, 1024 uint64_t Address, 1025 const void *Decoder) { 1026 if (RegNo > 7) 1027 return MCDisassembler::Fail; 1028 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1029 Inst.addOperand(MCOperand::createReg(Reg)); 1030 return MCDisassembler::Success; 1031 } 1032 1033 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1034 unsigned RegNo, 1035 uint64_t Address, 1036 const void *Decoder) { 1037 if (RegNo > 7) 1038 return MCDisassembler::Fail; 1039 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1040 Inst.addOperand(MCOperand::createReg(Reg)); 1041 return MCDisassembler::Success; 1042 } 1043 1044 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1045 unsigned RegNo, 1046 uint64_t Address, 1047 const void *Decoder) { 1048 if (RegNo > 7) 1049 return MCDisassembler::Fail; 1050 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1051 Inst.addOperand(MCOperand::createReg(Reg)); 1052 return MCDisassembler::Success; 1053 } 1054 1055 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1056 unsigned RegNo, 1057 uint64_t Address, 1058 const void *Decoder) { 1059 if (RegNo > 31) 1060 return MCDisassembler::Fail; 1061 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1062 Inst.addOperand(MCOperand::createReg(Reg)); 1063 return MCDisassembler::Success; 1064 } 1065 1066 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1067 unsigned RegNo, 1068 uint64_t Address, 1069 const void *Decoder) { 1070 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1071 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1072 1073 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1074 } 1075 1076 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1077 unsigned RegNo, 1078 uint64_t Address, 1079 const void *Decoder) { 1080 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1081 } 1082 1083 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1084 unsigned RegNo, 1085 uint64_t Address, 1086 const void *Decoder) { 1087 if (RegNo > 31) 1088 return MCDisassembler::Fail; 1089 1090 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1091 Inst.addOperand(MCOperand::createReg(Reg)); 1092 return MCDisassembler::Success; 1093 } 1094 1095 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1096 unsigned RegNo, 1097 uint64_t Address, 1098 const void *Decoder) { 1099 if (RegNo > 31) 1100 return MCDisassembler::Fail; 1101 1102 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1103 Inst.addOperand(MCOperand::createReg(Reg)); 1104 return MCDisassembler::Success; 1105 } 1106 1107 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1108 unsigned RegNo, 1109 uint64_t Address, 1110 const void *Decoder) { 1111 if (RegNo > 31) 1112 return MCDisassembler::Fail; 1113 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1114 Inst.addOperand(MCOperand::createReg(Reg)); 1115 return MCDisassembler::Success; 1116 } 1117 1118 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1119 unsigned RegNo, 1120 uint64_t Address, 1121 const void *Decoder) { 1122 if (RegNo > 7) 1123 return MCDisassembler::Fail; 1124 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1125 Inst.addOperand(MCOperand::createReg(Reg)); 1126 return MCDisassembler::Success; 1127 } 1128 1129 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1130 uint64_t Address, 1131 const void *Decoder) { 1132 if (RegNo > 31) 1133 return MCDisassembler::Fail; 1134 1135 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1136 Inst.addOperand(MCOperand::createReg(Reg)); 1137 return MCDisassembler::Success; 1138 } 1139 1140 static DecodeStatus DecodeMem(MCInst &Inst, 1141 unsigned Insn, 1142 uint64_t Address, 1143 const void *Decoder) { 1144 int Offset = SignExtend32<16>(Insn & 0xffff); 1145 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1146 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1147 1148 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1149 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1150 1151 if (Inst.getOpcode() == Mips::SC || 1152 Inst.getOpcode() == Mips::SCD) 1153 Inst.addOperand(MCOperand::createReg(Reg)); 1154 1155 Inst.addOperand(MCOperand::createReg(Reg)); 1156 Inst.addOperand(MCOperand::createReg(Base)); 1157 Inst.addOperand(MCOperand::createImm(Offset)); 1158 1159 return MCDisassembler::Success; 1160 } 1161 1162 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1163 unsigned Insn, 1164 uint64_t Address, 1165 const void *Decoder) { 1166 int Offset = SignExtend32<9>(Insn >> 7); 1167 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1168 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1169 1170 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1171 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1172 1173 if (Inst.getOpcode() == Mips::SCE) 1174 Inst.addOperand(MCOperand::createReg(Reg)); 1175 1176 Inst.addOperand(MCOperand::createReg(Reg)); 1177 Inst.addOperand(MCOperand::createReg(Base)); 1178 Inst.addOperand(MCOperand::createImm(Offset)); 1179 1180 return MCDisassembler::Success; 1181 } 1182 1183 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1184 unsigned Insn, 1185 uint64_t Address, 1186 const void *Decoder) { 1187 int Offset = SignExtend32<9>(Insn & 0x1ff); 1188 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1189 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1190 1191 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1192 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1193 1194 Inst.addOperand(MCOperand::createReg(Reg)); 1195 Inst.addOperand(MCOperand::createReg(Base)); 1196 Inst.addOperand(MCOperand::createImm(Offset)); 1197 1198 return MCDisassembler::Success; 1199 } 1200 1201 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1202 unsigned Insn, 1203 uint64_t Address, 1204 const void *Decoder) { 1205 int Offset = SignExtend32<16>(Insn & 0xffff); 1206 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1207 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1208 1209 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1210 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1211 1212 Inst.addOperand(MCOperand::createReg(Reg)); 1213 Inst.addOperand(MCOperand::createReg(Base)); 1214 Inst.addOperand(MCOperand::createImm(Offset)); 1215 1216 return MCDisassembler::Success; 1217 } 1218 1219 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1220 unsigned Insn, 1221 uint64_t Address, 1222 const void *Decoder) { 1223 int Offset = SignExtend32<16>(Insn & 0xffff); 1224 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1225 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1226 1227 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1228 1229 Inst.addOperand(MCOperand::createReg(Base)); 1230 Inst.addOperand(MCOperand::createImm(Offset)); 1231 Inst.addOperand(MCOperand::createImm(Hint)); 1232 1233 return MCDisassembler::Success; 1234 } 1235 1236 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1237 unsigned Insn, 1238 uint64_t Address, 1239 const void *Decoder) { 1240 int Offset = SignExtend32<12>(Insn & 0xfff); 1241 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1242 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1243 1244 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1245 1246 Inst.addOperand(MCOperand::createReg(Base)); 1247 Inst.addOperand(MCOperand::createImm(Offset)); 1248 Inst.addOperand(MCOperand::createImm(Hint)); 1249 1250 return MCDisassembler::Success; 1251 } 1252 1253 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1254 unsigned Insn, 1255 uint64_t Address, 1256 const void *Decoder) { 1257 int Offset = SignExtend32<9>(Insn & 0x1ff); 1258 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1259 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1260 1261 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1262 1263 Inst.addOperand(MCOperand::createReg(Base)); 1264 Inst.addOperand(MCOperand::createImm(Offset)); 1265 Inst.addOperand(MCOperand::createImm(Hint)); 1266 1267 return MCDisassembler::Success; 1268 } 1269 1270 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1271 unsigned Insn, 1272 uint64_t Address, 1273 const void *Decoder) { 1274 int Offset = SignExtend32<9>(Insn >> 7); 1275 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1276 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1277 1278 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1279 1280 Inst.addOperand(MCOperand::createReg(Base)); 1281 Inst.addOperand(MCOperand::createImm(Offset)); 1282 Inst.addOperand(MCOperand::createImm(Hint)); 1283 1284 return MCDisassembler::Success; 1285 } 1286 1287 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1288 unsigned Insn, 1289 uint64_t Address, 1290 const void *Decoder) { 1291 int Offset = SignExtend32<9>(Insn & 0x1ff); 1292 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1293 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1294 1295 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1296 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1297 1298 Inst.addOperand(MCOperand::createReg(Reg)); 1299 Inst.addOperand(MCOperand::createReg(Base)); 1300 Inst.addOperand(MCOperand::createImm(Offset)); 1301 1302 return MCDisassembler::Success; 1303 } 1304 1305 static DecodeStatus DecodeSyncI(MCInst &Inst, 1306 unsigned Insn, 1307 uint64_t Address, 1308 const void *Decoder) { 1309 int Offset = SignExtend32<16>(Insn & 0xffff); 1310 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1311 1312 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1313 1314 Inst.addOperand(MCOperand::createReg(Base)); 1315 Inst.addOperand(MCOperand::createImm(Offset)); 1316 1317 return MCDisassembler::Success; 1318 } 1319 1320 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1321 unsigned Insn, 1322 uint64_t Address, 1323 const void *Decoder) { 1324 int Immediate = SignExtend32<16>(Insn & 0xffff); 1325 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1326 1327 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1328 1329 Inst.addOperand(MCOperand::createReg(Base)); 1330 Inst.addOperand(MCOperand::createImm(Immediate)); 1331 1332 return MCDisassembler::Success; 1333 } 1334 1335 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1336 uint64_t Address, const void *Decoder) { 1337 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1338 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1339 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1340 1341 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1342 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1343 1344 Inst.addOperand(MCOperand::createReg(Reg)); 1345 Inst.addOperand(MCOperand::createReg(Base)); 1346 1347 // The immediate field of an LD/ST instruction is scaled which means it must 1348 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1349 // data format. 1350 // .b - 1 byte 1351 // .h - 2 bytes 1352 // .w - 4 bytes 1353 // .d - 8 bytes 1354 switch(Inst.getOpcode()) 1355 { 1356 default: 1357 assert (0 && "Unexpected instruction"); 1358 return MCDisassembler::Fail; 1359 break; 1360 case Mips::LD_B: 1361 case Mips::ST_B: 1362 Inst.addOperand(MCOperand::createImm(Offset)); 1363 break; 1364 case Mips::LD_H: 1365 case Mips::ST_H: 1366 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1367 break; 1368 case Mips::LD_W: 1369 case Mips::ST_W: 1370 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1371 break; 1372 case Mips::LD_D: 1373 case Mips::ST_D: 1374 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1375 break; 1376 } 1377 1378 return MCDisassembler::Success; 1379 } 1380 1381 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1382 unsigned Insn, 1383 uint64_t Address, 1384 const void *Decoder) { 1385 unsigned Offset = Insn & 0xf; 1386 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1387 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1388 1389 switch (Inst.getOpcode()) { 1390 case Mips::LBU16_MM: 1391 case Mips::LHU16_MM: 1392 case Mips::LW16_MM: 1393 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1394 == MCDisassembler::Fail) 1395 return MCDisassembler::Fail; 1396 break; 1397 case Mips::SB16_MM: 1398 case Mips::SB16_MMR6: 1399 case Mips::SH16_MM: 1400 case Mips::SH16_MMR6: 1401 case Mips::SW16_MM: 1402 case Mips::SW16_MMR6: 1403 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1404 == MCDisassembler::Fail) 1405 return MCDisassembler::Fail; 1406 break; 1407 } 1408 1409 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1410 == MCDisassembler::Fail) 1411 return MCDisassembler::Fail; 1412 1413 switch (Inst.getOpcode()) { 1414 case Mips::LBU16_MM: 1415 if (Offset == 0xf) 1416 Inst.addOperand(MCOperand::createImm(-1)); 1417 else 1418 Inst.addOperand(MCOperand::createImm(Offset)); 1419 break; 1420 case Mips::SB16_MM: 1421 case Mips::SB16_MMR6: 1422 Inst.addOperand(MCOperand::createImm(Offset)); 1423 break; 1424 case Mips::LHU16_MM: 1425 case Mips::SH16_MM: 1426 case Mips::SH16_MMR6: 1427 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1428 break; 1429 case Mips::LW16_MM: 1430 case Mips::SW16_MM: 1431 case Mips::SW16_MMR6: 1432 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1433 break; 1434 } 1435 1436 return MCDisassembler::Success; 1437 } 1438 1439 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1440 unsigned Insn, 1441 uint64_t Address, 1442 const void *Decoder) { 1443 unsigned Offset = Insn & 0x1F; 1444 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1445 1446 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1447 1448 Inst.addOperand(MCOperand::createReg(Reg)); 1449 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1450 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1451 1452 return MCDisassembler::Success; 1453 } 1454 1455 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1456 unsigned Insn, 1457 uint64_t Address, 1458 const void *Decoder) { 1459 unsigned Offset = Insn & 0x7F; 1460 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1461 1462 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1463 1464 Inst.addOperand(MCOperand::createReg(Reg)); 1465 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1466 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1467 1468 return MCDisassembler::Success; 1469 } 1470 1471 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1472 unsigned Insn, 1473 uint64_t Address, 1474 const void *Decoder) { 1475 int Offset; 1476 switch (Inst.getOpcode()) { 1477 case Mips::LWM16_MMR6: 1478 case Mips::SWM16_MMR6: 1479 Offset = fieldFromInstruction(Insn, 4, 4); 1480 break; 1481 default: 1482 Offset = SignExtend32<4>(Insn & 0xf); 1483 break; 1484 } 1485 1486 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1487 == MCDisassembler::Fail) 1488 return MCDisassembler::Fail; 1489 1490 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1491 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1492 1493 return MCDisassembler::Success; 1494 } 1495 1496 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1497 unsigned Insn, 1498 uint64_t Address, 1499 const void *Decoder) { 1500 int Offset = SignExtend32<9>(Insn & 0x1ff); 1501 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1502 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1503 1504 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1505 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1506 1507 if (Inst.getOpcode() == Mips::SCE_MM) 1508 Inst.addOperand(MCOperand::createReg(Reg)); 1509 1510 Inst.addOperand(MCOperand::createReg(Reg)); 1511 Inst.addOperand(MCOperand::createReg(Base)); 1512 Inst.addOperand(MCOperand::createImm(Offset)); 1513 1514 return MCDisassembler::Success; 1515 } 1516 1517 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1518 unsigned Insn, 1519 uint64_t Address, 1520 const void *Decoder) { 1521 int Offset = SignExtend32<12>(Insn & 0x0fff); 1522 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1523 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1524 1525 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1526 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1527 1528 switch (Inst.getOpcode()) { 1529 case Mips::SWM32_MM: 1530 case Mips::LWM32_MM: 1531 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1532 == MCDisassembler::Fail) 1533 return MCDisassembler::Fail; 1534 Inst.addOperand(MCOperand::createReg(Base)); 1535 Inst.addOperand(MCOperand::createImm(Offset)); 1536 break; 1537 case Mips::SC_MM: 1538 Inst.addOperand(MCOperand::createReg(Reg)); 1539 // fallthrough 1540 default: 1541 Inst.addOperand(MCOperand::createReg(Reg)); 1542 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1543 Inst.addOperand(MCOperand::createReg(Reg+1)); 1544 1545 Inst.addOperand(MCOperand::createReg(Base)); 1546 Inst.addOperand(MCOperand::createImm(Offset)); 1547 } 1548 1549 return MCDisassembler::Success; 1550 } 1551 1552 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1553 unsigned Insn, 1554 uint64_t Address, 1555 const void *Decoder) { 1556 int Offset = SignExtend32<16>(Insn & 0xffff); 1557 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1558 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1559 1560 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1561 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1562 1563 Inst.addOperand(MCOperand::createReg(Reg)); 1564 Inst.addOperand(MCOperand::createReg(Base)); 1565 Inst.addOperand(MCOperand::createImm(Offset)); 1566 1567 return MCDisassembler::Success; 1568 } 1569 1570 static DecodeStatus DecodeFMem(MCInst &Inst, 1571 unsigned Insn, 1572 uint64_t Address, 1573 const void *Decoder) { 1574 int Offset = SignExtend32<16>(Insn & 0xffff); 1575 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1576 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1577 1578 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1579 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1580 1581 Inst.addOperand(MCOperand::createReg(Reg)); 1582 Inst.addOperand(MCOperand::createReg(Base)); 1583 Inst.addOperand(MCOperand::createImm(Offset)); 1584 1585 return MCDisassembler::Success; 1586 } 1587 1588 static DecodeStatus DecodeFMem2(MCInst &Inst, 1589 unsigned Insn, 1590 uint64_t Address, 1591 const void *Decoder) { 1592 int Offset = SignExtend32<16>(Insn & 0xffff); 1593 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1594 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1595 1596 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1597 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1598 1599 Inst.addOperand(MCOperand::createReg(Reg)); 1600 Inst.addOperand(MCOperand::createReg(Base)); 1601 Inst.addOperand(MCOperand::createImm(Offset)); 1602 1603 return MCDisassembler::Success; 1604 } 1605 1606 static DecodeStatus DecodeFMem3(MCInst &Inst, 1607 unsigned Insn, 1608 uint64_t Address, 1609 const void *Decoder) { 1610 int Offset = SignExtend32<16>(Insn & 0xffff); 1611 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1612 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1613 1614 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1615 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1616 1617 Inst.addOperand(MCOperand::createReg(Reg)); 1618 Inst.addOperand(MCOperand::createReg(Base)); 1619 Inst.addOperand(MCOperand::createImm(Offset)); 1620 1621 return MCDisassembler::Success; 1622 } 1623 1624 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1625 unsigned Insn, 1626 uint64_t Address, 1627 const void *Decoder) { 1628 int Offset = SignExtend32<11>(Insn & 0x07ff); 1629 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1630 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1631 1632 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1633 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1634 1635 Inst.addOperand(MCOperand::createReg(Reg)); 1636 Inst.addOperand(MCOperand::createReg(Base)); 1637 Inst.addOperand(MCOperand::createImm(Offset)); 1638 1639 return MCDisassembler::Success; 1640 } 1641 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1642 unsigned Insn, 1643 uint64_t Address, 1644 const void *Decoder) { 1645 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1646 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1647 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1648 1649 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1650 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1651 1652 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1653 Inst.addOperand(MCOperand::createReg(Rt)); 1654 } 1655 1656 Inst.addOperand(MCOperand::createReg(Rt)); 1657 Inst.addOperand(MCOperand::createReg(Base)); 1658 Inst.addOperand(MCOperand::createImm(Offset)); 1659 1660 return MCDisassembler::Success; 1661 } 1662 1663 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1664 unsigned RegNo, 1665 uint64_t Address, 1666 const void *Decoder) { 1667 // Currently only hardware register 29 is supported. 1668 if (RegNo != 29) 1669 return MCDisassembler::Fail; 1670 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1671 return MCDisassembler::Success; 1672 } 1673 1674 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1675 unsigned RegNo, 1676 uint64_t Address, 1677 const void *Decoder) { 1678 if (RegNo > 30 || RegNo %2) 1679 return MCDisassembler::Fail; 1680 1681 ; 1682 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1683 Inst.addOperand(MCOperand::createReg(Reg)); 1684 return MCDisassembler::Success; 1685 } 1686 1687 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1688 unsigned RegNo, 1689 uint64_t Address, 1690 const void *Decoder) { 1691 if (RegNo >= 4) 1692 return MCDisassembler::Fail; 1693 1694 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1695 Inst.addOperand(MCOperand::createReg(Reg)); 1696 return MCDisassembler::Success; 1697 } 1698 1699 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1700 unsigned RegNo, 1701 uint64_t Address, 1702 const void *Decoder) { 1703 if (RegNo >= 4) 1704 return MCDisassembler::Fail; 1705 1706 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1707 Inst.addOperand(MCOperand::createReg(Reg)); 1708 return MCDisassembler::Success; 1709 } 1710 1711 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1712 unsigned RegNo, 1713 uint64_t Address, 1714 const void *Decoder) { 1715 if (RegNo >= 4) 1716 return MCDisassembler::Fail; 1717 1718 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1719 Inst.addOperand(MCOperand::createReg(Reg)); 1720 return MCDisassembler::Success; 1721 } 1722 1723 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1724 unsigned RegNo, 1725 uint64_t Address, 1726 const void *Decoder) { 1727 if (RegNo > 31) 1728 return MCDisassembler::Fail; 1729 1730 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1731 Inst.addOperand(MCOperand::createReg(Reg)); 1732 return MCDisassembler::Success; 1733 } 1734 1735 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1736 unsigned RegNo, 1737 uint64_t Address, 1738 const void *Decoder) { 1739 if (RegNo > 31) 1740 return MCDisassembler::Fail; 1741 1742 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1743 Inst.addOperand(MCOperand::createReg(Reg)); 1744 return MCDisassembler::Success; 1745 } 1746 1747 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1748 unsigned RegNo, 1749 uint64_t Address, 1750 const void *Decoder) { 1751 if (RegNo > 31) 1752 return MCDisassembler::Fail; 1753 1754 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1755 Inst.addOperand(MCOperand::createReg(Reg)); 1756 return MCDisassembler::Success; 1757 } 1758 1759 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1760 unsigned RegNo, 1761 uint64_t Address, 1762 const void *Decoder) { 1763 if (RegNo > 31) 1764 return MCDisassembler::Fail; 1765 1766 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1767 Inst.addOperand(MCOperand::createReg(Reg)); 1768 return MCDisassembler::Success; 1769 } 1770 1771 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1772 unsigned RegNo, 1773 uint64_t Address, 1774 const void *Decoder) { 1775 if (RegNo > 7) 1776 return MCDisassembler::Fail; 1777 1778 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1779 Inst.addOperand(MCOperand::createReg(Reg)); 1780 return MCDisassembler::Success; 1781 } 1782 1783 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1784 unsigned RegNo, 1785 uint64_t Address, 1786 const void *Decoder) { 1787 if (RegNo > 31) 1788 return MCDisassembler::Fail; 1789 1790 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1791 Inst.addOperand(MCOperand::createReg(Reg)); 1792 return MCDisassembler::Success; 1793 } 1794 1795 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1796 unsigned RegNo, 1797 uint64_t Address, 1798 const void *Decoder) { 1799 if (RegNo > 31) 1800 return MCDisassembler::Fail; 1801 1802 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1803 Inst.addOperand(MCOperand::createReg(Reg)); 1804 return MCDisassembler::Success; 1805 } 1806 1807 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1808 unsigned Offset, 1809 uint64_t Address, 1810 const void *Decoder) { 1811 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1812 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1813 return MCDisassembler::Success; 1814 } 1815 1816 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1817 unsigned Insn, 1818 uint64_t Address, 1819 const void *Decoder) { 1820 1821 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1822 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1823 return MCDisassembler::Success; 1824 } 1825 1826 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1827 unsigned Offset, 1828 uint64_t Address, 1829 const void *Decoder) { 1830 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1831 1832 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1833 return MCDisassembler::Success; 1834 } 1835 1836 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1837 unsigned Offset, 1838 uint64_t Address, 1839 const void *Decoder) { 1840 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1841 1842 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1843 return MCDisassembler::Success; 1844 } 1845 1846 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1847 unsigned Offset, 1848 uint64_t Address, 1849 const void *Decoder) { 1850 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1851 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1852 return MCDisassembler::Success; 1853 } 1854 1855 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1856 unsigned Offset, 1857 uint64_t Address, 1858 const void *Decoder) { 1859 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1860 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1861 return MCDisassembler::Success; 1862 } 1863 1864 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1865 unsigned Offset, 1866 uint64_t Address, 1867 const void *Decoder) { 1868 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1869 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1870 return MCDisassembler::Success; 1871 } 1872 1873 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 1874 unsigned Offset, 1875 uint64_t Address, 1876 const void *Decoder) { 1877 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 1878 1879 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1880 return MCDisassembler::Success; 1881 } 1882 1883 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1884 unsigned Insn, 1885 uint64_t Address, 1886 const void *Decoder) { 1887 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1888 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1889 return MCDisassembler::Success; 1890 } 1891 1892 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1893 unsigned Value, 1894 uint64_t Address, 1895 const void *Decoder) { 1896 if (Value == 0) 1897 Inst.addOperand(MCOperand::createImm(1)); 1898 else if (Value == 0x7) 1899 Inst.addOperand(MCOperand::createImm(-1)); 1900 else 1901 Inst.addOperand(MCOperand::createImm(Value << 2)); 1902 return MCDisassembler::Success; 1903 } 1904 1905 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1906 unsigned Value, 1907 uint64_t Address, 1908 const void *Decoder) { 1909 Inst.addOperand(MCOperand::createImm(Value << 2)); 1910 return MCDisassembler::Success; 1911 } 1912 1913 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1914 unsigned Value, 1915 uint64_t Address, 1916 const void *Decoder) { 1917 if (Value == 0x7F) 1918 Inst.addOperand(MCOperand::createImm(-1)); 1919 else 1920 Inst.addOperand(MCOperand::createImm(Value)); 1921 return MCDisassembler::Success; 1922 } 1923 1924 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1925 unsigned Value, 1926 uint64_t Address, 1927 const void *Decoder) { 1928 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1929 return MCDisassembler::Success; 1930 } 1931 1932 static DecodeStatus DecodeSimm4(MCInst &Inst, 1933 unsigned Value, 1934 uint64_t Address, 1935 const void *Decoder) { 1936 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); 1937 return MCDisassembler::Success; 1938 } 1939 1940 static DecodeStatus DecodeSimm16(MCInst &Inst, 1941 unsigned Insn, 1942 uint64_t Address, 1943 const void *Decoder) { 1944 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); 1945 return MCDisassembler::Success; 1946 } 1947 1948 template <unsigned Bits, int Offset> 1949 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 1950 uint64_t Address, 1951 const void *Decoder) { 1952 Value &= ((1 << Bits) - 1); 1953 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1954 return MCDisassembler::Success; 1955 } 1956 1957 static DecodeStatus DecodeInsSize(MCInst &Inst, 1958 unsigned Insn, 1959 uint64_t Address, 1960 const void *Decoder) { 1961 // First we need to grab the pos(lsb) from MCInst. 1962 int Pos = Inst.getOperand(2).getImm(); 1963 int Size = (int) Insn - Pos + 1; 1964 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1965 return MCDisassembler::Success; 1966 } 1967 1968 static DecodeStatus DecodeExtSize(MCInst &Inst, 1969 unsigned Insn, 1970 uint64_t Address, 1971 const void *Decoder) { 1972 int Size = (int) Insn + 1; 1973 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1974 return MCDisassembler::Success; 1975 } 1976 1977 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1978 uint64_t Address, const void *Decoder) { 1979 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1980 return MCDisassembler::Success; 1981 } 1982 1983 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1984 uint64_t Address, const void *Decoder) { 1985 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1986 return MCDisassembler::Success; 1987 } 1988 1989 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1990 uint64_t Address, const void *Decoder) { 1991 int32_t DecodedValue; 1992 switch (Insn) { 1993 case 0: DecodedValue = 256; break; 1994 case 1: DecodedValue = 257; break; 1995 case 510: DecodedValue = -258; break; 1996 case 511: DecodedValue = -257; break; 1997 default: DecodedValue = SignExtend32<9>(Insn); break; 1998 } 1999 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2000 return MCDisassembler::Success; 2001 } 2002 2003 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2004 uint64_t Address, const void *Decoder) { 2005 // Insn must be >= 0, since it is unsigned that condition is always true. 2006 assert(Insn < 16); 2007 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2008 255, 32768, 65535}; 2009 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2010 return MCDisassembler::Success; 2011 } 2012 2013 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 2014 uint64_t Address, const void *Decoder) { 2015 Inst.addOperand(MCOperand::createImm(Insn << 2)); 2016 return MCDisassembler::Success; 2017 } 2018 2019 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2020 unsigned Insn, 2021 uint64_t Address, 2022 const void *Decoder) { 2023 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2024 Mips::S6, Mips::S7, Mips::FP}; 2025 unsigned RegNum; 2026 2027 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2028 2029 // Empty register lists are not allowed. 2030 if (RegLst == 0) 2031 return MCDisassembler::Fail; 2032 2033 RegNum = RegLst & 0xf; 2034 2035 // RegLst values 10-15, and 26-31 are reserved. 2036 if (RegNum > 9) 2037 return MCDisassembler::Fail; 2038 2039 for (unsigned i = 0; i < RegNum; i++) 2040 Inst.addOperand(MCOperand::createReg(Regs[i])); 2041 2042 if (RegLst & 0x10) 2043 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2044 2045 return MCDisassembler::Success; 2046 } 2047 2048 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2049 uint64_t Address, 2050 const void *Decoder) { 2051 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2052 unsigned RegLst; 2053 switch(Inst.getOpcode()) { 2054 default: 2055 RegLst = fieldFromInstruction(Insn, 4, 2); 2056 break; 2057 case Mips::LWM16_MMR6: 2058 case Mips::SWM16_MMR6: 2059 RegLst = fieldFromInstruction(Insn, 8, 2); 2060 break; 2061 } 2062 unsigned RegNum = RegLst & 0x3; 2063 2064 for (unsigned i = 0; i <= RegNum; i++) 2065 Inst.addOperand(MCOperand::createReg(Regs[i])); 2066 2067 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2068 2069 return MCDisassembler::Success; 2070 } 2071 2072 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2073 uint64_t Address, const void *Decoder) { 2074 2075 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2076 2077 switch (RegPair) { 2078 default: 2079 return MCDisassembler::Fail; 2080 case 0: 2081 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2082 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2083 break; 2084 case 1: 2085 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2086 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2087 break; 2088 case 2: 2089 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2090 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2091 break; 2092 case 3: 2093 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2094 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2095 break; 2096 case 4: 2097 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2098 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2099 break; 2100 case 5: 2101 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2102 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2103 break; 2104 case 6: 2105 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2106 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2107 break; 2108 case 7: 2109 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2110 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2111 break; 2112 } 2113 2114 return MCDisassembler::Success; 2115 } 2116 2117 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2118 uint64_t Address, const void *Decoder) { 2119 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2120 return MCDisassembler::Success; 2121 } 2122