1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 48 49 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 50 51 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 52 53 bool hasCOP3() const { 54 // Only present in MIPS-I and MIPS-II 55 return !hasMips32() && !hasMips3(); 56 } 57 58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 59 ArrayRef<uint8_t> Bytes, uint64_t Address, 60 raw_ostream &VStream, 61 raw_ostream &CStream) const override; 62 }; 63 64 } // end anonymous namespace 65 66 // Forward declare these because the autogenerated code will reference them. 67 // Definitions are further down. 68 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 69 unsigned RegNo, 70 uint64_t Address, 71 const void *Decoder); 72 73 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 74 unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 78 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 79 unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 83 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 99 unsigned Insn, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 114 unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 133 unsigned Insn, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 193 unsigned Offset, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 198 unsigned Offset, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 203 unsigned Insn, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 213 unsigned Offset, 214 uint64_t Address, 215 const void *Decoder); 216 217 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 218 unsigned Offset, 219 uint64_t Address, 220 const void *Decoder); 221 222 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 223 // shifted left by 1 bit. 224 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 225 unsigned Offset, 226 uint64_t Address, 227 const void *Decoder); 228 229 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 230 // shifted left by 1 bit. 231 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 232 unsigned Offset, 233 uint64_t Address, 234 const void *Decoder); 235 236 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 237 // shifted left by 1 bit. 238 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 239 unsigned Offset, 240 uint64_t Address, 241 const void *Decoder); 242 243 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 244 // shifted left by 1 bit. 245 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 246 unsigned Offset, 247 uint64_t Address, 248 const void *Decoder); 249 250 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 251 // shifted left by 1 bit. 252 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 253 unsigned Insn, 254 uint64_t Address, 255 const void *Decoder); 256 257 static DecodeStatus DecodeMem(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 262 static DecodeStatus DecodeMemEVA(MCInst &Inst, 263 unsigned Insn, 264 uint64_t Address, 265 const void *Decoder); 266 267 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeCacheOp(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeSyncI(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeSynciR6(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 315 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 321 unsigned Insn, 322 uint64_t Address, 323 const void *Decoder); 324 325 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 326 unsigned Insn, 327 uint64_t Address, 328 const void *Decoder); 329 330 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 331 unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 336 unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 341 unsigned Insn, 342 uint64_t Address, 343 const void *Decoder); 344 345 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 346 unsigned Insn, 347 uint64_t Address, 348 const void *Decoder); 349 350 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 351 uint64_t Address, 352 const void *Decoder); 353 354 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 359 uint64_t Address, 360 const void *Decoder); 361 362 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 363 uint64_t Address, 364 const void *Decoder); 365 366 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 367 unsigned Insn, 368 uint64_t Address, 369 const void *Decoder); 370 371 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 372 unsigned Value, 373 uint64_t Address, 374 const void *Decoder); 375 376 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 377 unsigned Value, 378 uint64_t Address, 379 const void *Decoder); 380 381 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 382 unsigned Value, 383 uint64_t Address, 384 const void *Decoder); 385 386 template <unsigned Bits, int Offset, int Scale> 387 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 388 uint64_t Address, 389 const void *Decoder); 390 391 template <unsigned Bits, int Offset> 392 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 393 uint64_t Address, 394 const void *Decoder) { 395 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 396 Decoder); 397 } 398 399 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 400 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 401 uint64_t Address, 402 const void *Decoder); 403 404 static DecodeStatus DecodeInsSize(MCInst &Inst, 405 unsigned Insn, 406 uint64_t Address, 407 const void *Decoder); 408 409 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 410 uint64_t Address, const void *Decoder); 411 412 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void *Decoder); 414 415 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 416 uint64_t Address, const void *Decoder); 417 418 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 419 uint64_t Address, const void *Decoder); 420 421 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void *Decoder); 423 424 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 425 /// handle. 426 template <typename InsnType> 427 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 428 const void *Decoder); 429 430 template <typename InsnType> 431 static DecodeStatus 432 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 433 const void *Decoder); 434 435 template <typename InsnType> 436 static DecodeStatus 437 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 438 const void *Decoder); 439 440 template <typename InsnType> 441 static DecodeStatus 442 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus 447 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus 452 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 453 const void *Decoder); 454 455 template <typename InsnType> 456 static DecodeStatus 457 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 458 const void *Decoder); 459 460 template <typename InsnType> 461 static DecodeStatus 462 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 463 const void *Decoder); 464 465 template <typename InsnType> 466 static DecodeStatus 467 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 468 const void *Decoder); 469 470 template <typename InsnType> 471 static DecodeStatus 472 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 473 const void *Decoder); 474 475 template <typename InsnType> 476 static DecodeStatus 477 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 478 const void *Decoder); 479 480 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 481 uint64_t Address, 482 const void *Decoder); 483 484 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 485 uint64_t Address, 486 const void *Decoder); 487 488 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 489 uint64_t Address, 490 const void *Decoder); 491 492 namespace llvm { 493 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 494 TheMips64elTarget; 495 } 496 497 static MCDisassembler *createMipsDisassembler( 498 const Target &T, 499 const MCSubtargetInfo &STI, 500 MCContext &Ctx) { 501 return new MipsDisassembler(STI, Ctx, true); 502 } 503 504 static MCDisassembler *createMipselDisassembler( 505 const Target &T, 506 const MCSubtargetInfo &STI, 507 MCContext &Ctx) { 508 return new MipsDisassembler(STI, Ctx, false); 509 } 510 511 extern "C" void LLVMInitializeMipsDisassembler() { 512 // Register the disassembler. 513 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 514 createMipsDisassembler); 515 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 516 createMipselDisassembler); 517 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 518 createMipsDisassembler); 519 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 520 createMipselDisassembler); 521 } 522 523 #include "MipsGenDisassemblerTables.inc" 524 525 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 526 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 527 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 528 return *(RegInfo->getRegClass(RC).begin() + RegNo); 529 } 530 531 template <typename InsnType> 532 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 533 const void *Decoder) { 534 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 535 // The size of the n field depends on the element size 536 // The register class also depends on this. 537 InsnType tmp = fieldFromInstruction(insn, 17, 5); 538 unsigned NSize = 0; 539 DecodeFN RegDecoder = nullptr; 540 if ((tmp & 0x18) == 0x00) { // INSVE_B 541 NSize = 4; 542 RegDecoder = DecodeMSA128BRegisterClass; 543 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 544 NSize = 3; 545 RegDecoder = DecodeMSA128HRegisterClass; 546 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 547 NSize = 2; 548 RegDecoder = DecodeMSA128WRegisterClass; 549 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 550 NSize = 1; 551 RegDecoder = DecodeMSA128DRegisterClass; 552 } else 553 llvm_unreachable("Invalid encoding"); 554 555 assert(NSize != 0 && RegDecoder != nullptr); 556 557 // $wd 558 tmp = fieldFromInstruction(insn, 6, 5); 559 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 560 return MCDisassembler::Fail; 561 // $wd_in 562 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 563 return MCDisassembler::Fail; 564 // $n 565 tmp = fieldFromInstruction(insn, 16, NSize); 566 MI.addOperand(MCOperand::createImm(tmp)); 567 // $ws 568 tmp = fieldFromInstruction(insn, 11, 5); 569 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 570 return MCDisassembler::Fail; 571 // $n2 572 MI.addOperand(MCOperand::createImm(0)); 573 574 return MCDisassembler::Success; 575 } 576 577 template <typename InsnType> 578 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 579 uint64_t Address, 580 const void *Decoder) { 581 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 582 // (otherwise we would have matched the ADDI instruction from the earlier 583 // ISA's instead). 584 // 585 // We have: 586 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 587 // BOVC if rs >= rt 588 // BEQZALC if rs == 0 && rt != 0 589 // BEQC if rs < rt && rs != 0 590 591 InsnType Rs = fieldFromInstruction(insn, 21, 5); 592 InsnType Rt = fieldFromInstruction(insn, 16, 5); 593 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 594 bool HasRs = false; 595 596 if (Rs >= Rt) { 597 MI.setOpcode(Mips::BOVC); 598 HasRs = true; 599 } else if (Rs != 0 && Rs < Rt) { 600 MI.setOpcode(Mips::BEQC); 601 HasRs = true; 602 } else 603 MI.setOpcode(Mips::BEQZALC); 604 605 if (HasRs) 606 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 607 Rs))); 608 609 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 610 Rt))); 611 MI.addOperand(MCOperand::createImm(Imm)); 612 613 return MCDisassembler::Success; 614 } 615 616 template <typename InsnType> 617 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 618 uint64_t Address, 619 const void *Decoder) { 620 InsnType Rt = fieldFromInstruction(insn, 21, 5); 621 InsnType Rs = fieldFromInstruction(insn, 16, 5); 622 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 623 624 if (Rs >= Rt) { 625 MI.setOpcode(Mips::BOVC_MMR6); 626 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 627 Rt))); 628 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 629 Rs))); 630 } else if (Rs != 0 && Rs < Rt) { 631 MI.setOpcode(Mips::BEQC_MMR6); 632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 633 Rs))); 634 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 635 Rt))); 636 } else { 637 MI.setOpcode(Mips::BEQZALC_MMR6); 638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 639 Rt))); 640 } 641 642 MI.addOperand(MCOperand::createImm(Imm)); 643 644 return MCDisassembler::Success; 645 } 646 647 template <typename InsnType> 648 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 649 uint64_t Address, 650 const void *Decoder) { 651 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 652 // (otherwise we would have matched the ADDI instruction from the earlier 653 // ISA's instead). 654 // 655 // We have: 656 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 657 // BNVC if rs >= rt 658 // BNEZALC if rs == 0 && rt != 0 659 // BNEC if rs < rt && rs != 0 660 661 InsnType Rs = fieldFromInstruction(insn, 21, 5); 662 InsnType Rt = fieldFromInstruction(insn, 16, 5); 663 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 664 bool HasRs = false; 665 666 if (Rs >= Rt) { 667 MI.setOpcode(Mips::BNVC); 668 HasRs = true; 669 } else if (Rs != 0 && Rs < Rt) { 670 MI.setOpcode(Mips::BNEC); 671 HasRs = true; 672 } else 673 MI.setOpcode(Mips::BNEZALC); 674 675 if (HasRs) 676 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 677 Rs))); 678 679 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 680 Rt))); 681 MI.addOperand(MCOperand::createImm(Imm)); 682 683 return MCDisassembler::Success; 684 } 685 686 template <typename InsnType> 687 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 688 uint64_t Address, 689 const void *Decoder) { 690 InsnType Rt = fieldFromInstruction(insn, 21, 5); 691 InsnType Rs = fieldFromInstruction(insn, 16, 5); 692 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 693 694 if (Rs >= Rt) { 695 MI.setOpcode(Mips::BNVC_MMR6); 696 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 697 Rt))); 698 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 699 Rs))); 700 } else if (Rs != 0 && Rs < Rt) { 701 MI.setOpcode(Mips::BNEC_MMR6); 702 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 703 Rs))); 704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 705 Rt))); 706 } else { 707 MI.setOpcode(Mips::BNEZALC_MMR6); 708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 709 Rt))); 710 } 711 712 MI.addOperand(MCOperand::createImm(Imm)); 713 714 return MCDisassembler::Success; 715 } 716 717 template <typename InsnType> 718 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 719 uint64_t Address, 720 const void *Decoder) { 721 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 722 // (otherwise we would have matched the BLEZL instruction from the earlier 723 // ISA's instead). 724 // 725 // We have: 726 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 727 // Invalid if rs == 0 728 // BLEZC if rs == 0 && rt != 0 729 // BGEZC if rs == rt && rt != 0 730 // BGEC if rs != rt && rs != 0 && rt != 0 731 732 InsnType Rs = fieldFromInstruction(insn, 21, 5); 733 InsnType Rt = fieldFromInstruction(insn, 16, 5); 734 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 735 bool HasRs = false; 736 737 if (Rt == 0) 738 return MCDisassembler::Fail; 739 else if (Rs == 0) 740 MI.setOpcode(Mips::BLEZC); 741 else if (Rs == Rt) 742 MI.setOpcode(Mips::BGEZC); 743 else { 744 HasRs = true; 745 MI.setOpcode(Mips::BGEC); 746 } 747 748 if (HasRs) 749 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 750 Rs))); 751 752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 753 Rt))); 754 755 MI.addOperand(MCOperand::createImm(Imm)); 756 757 return MCDisassembler::Success; 758 } 759 760 template <typename InsnType> 761 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 762 uint64_t Address, 763 const void *Decoder) { 764 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 765 // (otherwise we would have matched the BGTZL instruction from the earlier 766 // ISA's instead). 767 // 768 // We have: 769 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 770 // Invalid if rs == 0 771 // BGTZC if rs == 0 && rt != 0 772 // BLTZC if rs == rt && rt != 0 773 // BLTC if rs != rt && rs != 0 && rt != 0 774 775 bool HasRs = false; 776 777 InsnType Rs = fieldFromInstruction(insn, 21, 5); 778 InsnType Rt = fieldFromInstruction(insn, 16, 5); 779 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 780 781 if (Rt == 0) 782 return MCDisassembler::Fail; 783 else if (Rs == 0) 784 MI.setOpcode(Mips::BGTZC); 785 else if (Rs == Rt) 786 MI.setOpcode(Mips::BLTZC); 787 else { 788 MI.setOpcode(Mips::BLTC); 789 HasRs = true; 790 } 791 792 if (HasRs) 793 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 794 Rs))); 795 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rt))); 798 799 MI.addOperand(MCOperand::createImm(Imm)); 800 801 return MCDisassembler::Success; 802 } 803 804 template <typename InsnType> 805 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 806 uint64_t Address, 807 const void *Decoder) { 808 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 809 // (otherwise we would have matched the BGTZ instruction from the earlier 810 // ISA's instead). 811 // 812 // We have: 813 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 814 // BGTZ if rt == 0 815 // BGTZALC if rs == 0 && rt != 0 816 // BLTZALC if rs != 0 && rs == rt 817 // BLTUC if rs != 0 && rs != rt 818 819 InsnType Rs = fieldFromInstruction(insn, 21, 5); 820 InsnType Rt = fieldFromInstruction(insn, 16, 5); 821 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 822 bool HasRs = false; 823 bool HasRt = false; 824 825 if (Rt == 0) { 826 MI.setOpcode(Mips::BGTZ); 827 HasRs = true; 828 } else if (Rs == 0) { 829 MI.setOpcode(Mips::BGTZALC); 830 HasRt = true; 831 } else if (Rs == Rt) { 832 MI.setOpcode(Mips::BLTZALC); 833 HasRs = true; 834 } else { 835 MI.setOpcode(Mips::BLTUC); 836 HasRs = true; 837 HasRt = true; 838 } 839 840 if (HasRs) 841 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 842 Rs))); 843 844 if (HasRt) 845 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 846 Rt))); 847 848 MI.addOperand(MCOperand::createImm(Imm)); 849 850 return MCDisassembler::Success; 851 } 852 853 template <typename InsnType> 854 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 855 uint64_t Address, 856 const void *Decoder) { 857 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 858 // (otherwise we would have matched the BLEZL instruction from the earlier 859 // ISA's instead). 860 // 861 // We have: 862 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 863 // Invalid if rs == 0 864 // BLEZALC if rs == 0 && rt != 0 865 // BGEZALC if rs == rt && rt != 0 866 // BGEUC if rs != rt && rs != 0 && rt != 0 867 868 InsnType Rs = fieldFromInstruction(insn, 21, 5); 869 InsnType Rt = fieldFromInstruction(insn, 16, 5); 870 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 871 bool HasRs = false; 872 873 if (Rt == 0) 874 return MCDisassembler::Fail; 875 else if (Rs == 0) 876 MI.setOpcode(Mips::BLEZALC); 877 else if (Rs == Rt) 878 MI.setOpcode(Mips::BGEZALC); 879 else { 880 HasRs = true; 881 MI.setOpcode(Mips::BGEUC); 882 } 883 884 if (HasRs) 885 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 886 Rs))); 887 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 888 Rt))); 889 890 MI.addOperand(MCOperand::createImm(Imm)); 891 892 return MCDisassembler::Success; 893 } 894 895 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 896 /// according to the given endianess. 897 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 898 uint64_t &Size, uint32_t &Insn, 899 bool IsBigEndian) { 900 // We want to read exactly 2 Bytes of data. 901 if (Bytes.size() < 2) { 902 Size = 0; 903 return MCDisassembler::Fail; 904 } 905 906 if (IsBigEndian) { 907 Insn = (Bytes[0] << 8) | Bytes[1]; 908 } else { 909 Insn = (Bytes[1] << 8) | Bytes[0]; 910 } 911 912 return MCDisassembler::Success; 913 } 914 915 /// Read four bytes from the ArrayRef and return 32 bit word sorted 916 /// according to the given endianess 917 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 918 uint64_t &Size, uint32_t &Insn, 919 bool IsBigEndian, bool IsMicroMips) { 920 // We want to read exactly 4 Bytes of data. 921 if (Bytes.size() < 4) { 922 Size = 0; 923 return MCDisassembler::Fail; 924 } 925 926 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 927 // always precede the low 16 bits in the instruction stream (that is, they 928 // are placed at lower addresses in the instruction stream). 929 // 930 // microMIPS byte ordering: 931 // Big-endian: 0 | 1 | 2 | 3 932 // Little-endian: 1 | 0 | 3 | 2 933 934 if (IsBigEndian) { 935 // Encoded as a big-endian 32-bit word in the stream. 936 Insn = 937 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 938 } else { 939 if (IsMicroMips) { 940 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 941 (Bytes[1] << 24); 942 } else { 943 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 944 (Bytes[3] << 24); 945 } 946 } 947 948 return MCDisassembler::Success; 949 } 950 951 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 952 ArrayRef<uint8_t> Bytes, 953 uint64_t Address, 954 raw_ostream &VStream, 955 raw_ostream &CStream) const { 956 uint32_t Insn; 957 DecodeStatus Result; 958 959 if (IsMicroMips) { 960 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 961 if (Result == MCDisassembler::Fail) 962 return MCDisassembler::Fail; 963 964 if (hasMips32r6()) { 965 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 966 // Calling the auto-generated decoder function for microMIPS32R6 967 // (and microMIPS64R6) 16-bit instructions. 968 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 969 Address, this, STI); 970 if (Result != MCDisassembler::Fail) { 971 Size = 2; 972 return Result; 973 } 974 } 975 976 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 977 // Calling the auto-generated decoder function for microMIPS 16-bit 978 // instructions. 979 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 980 this, STI); 981 if (Result != MCDisassembler::Fail) { 982 Size = 2; 983 return Result; 984 } 985 986 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 987 if (Result == MCDisassembler::Fail) 988 return MCDisassembler::Fail; 989 990 if (hasMips32r6()) { 991 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 992 // Calling the auto-generated decoder function. 993 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 994 this, STI); 995 if (Result != MCDisassembler::Fail) { 996 Size = 4; 997 return Result; 998 } 999 } 1000 1001 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1002 // Calling the auto-generated decoder function. 1003 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1004 this, STI); 1005 if (Result != MCDisassembler::Fail) { 1006 Size = 4; 1007 return Result; 1008 } 1009 1010 if (hasMips32r6() && isFP64()) { 1011 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 1012 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 1013 Address, this, STI); 1014 if (Result != MCDisassembler::Fail) { 1015 Size = 4; 1016 return Result; 1017 } 1018 } 1019 1020 // This is an invalid instruction. Let the disassembler move forward by the 1021 // minimum instruction size. 1022 Size = 2; 1023 return MCDisassembler::Fail; 1024 } 1025 1026 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1027 if (Result == MCDisassembler::Fail) { 1028 Size = 4; 1029 return MCDisassembler::Fail; 1030 } 1031 1032 if (hasCOP3()) { 1033 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1034 Result = 1035 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1036 if (Result != MCDisassembler::Fail) { 1037 Size = 4; 1038 return Result; 1039 } 1040 } 1041 1042 if (hasMips32r6() && isGP64()) { 1043 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1044 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1045 Address, this, STI); 1046 if (Result != MCDisassembler::Fail) { 1047 Size = 4; 1048 return Result; 1049 } 1050 } 1051 1052 if (hasMips32r6()) { 1053 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1054 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1055 Address, this, STI); 1056 if (Result != MCDisassembler::Fail) { 1057 Size = 4; 1058 return Result; 1059 } 1060 } 1061 1062 if (hasCnMips()) { 1063 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1064 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1065 Address, this, STI); 1066 if (Result != MCDisassembler::Fail) { 1067 Size = 4; 1068 return Result; 1069 } 1070 } 1071 1072 if (isGP64()) { 1073 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1074 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1075 Address, this, STI); 1076 if (Result != MCDisassembler::Fail) { 1077 Size = 4; 1078 return Result; 1079 } 1080 } 1081 1082 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1083 // Calling the auto-generated decoder function. 1084 Result = 1085 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1086 if (Result != MCDisassembler::Fail) { 1087 Size = 4; 1088 return Result; 1089 } 1090 1091 Size = 4; 1092 return MCDisassembler::Fail; 1093 } 1094 1095 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1096 unsigned RegNo, 1097 uint64_t Address, 1098 const void *Decoder) { 1099 1100 return MCDisassembler::Fail; 1101 1102 } 1103 1104 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1105 unsigned RegNo, 1106 uint64_t Address, 1107 const void *Decoder) { 1108 1109 if (RegNo > 31) 1110 return MCDisassembler::Fail; 1111 1112 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1113 Inst.addOperand(MCOperand::createReg(Reg)); 1114 return MCDisassembler::Success; 1115 } 1116 1117 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1118 unsigned RegNo, 1119 uint64_t Address, 1120 const void *Decoder) { 1121 if (RegNo > 7) 1122 return MCDisassembler::Fail; 1123 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1124 Inst.addOperand(MCOperand::createReg(Reg)); 1125 return MCDisassembler::Success; 1126 } 1127 1128 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1129 unsigned RegNo, 1130 uint64_t Address, 1131 const void *Decoder) { 1132 if (RegNo > 7) 1133 return MCDisassembler::Fail; 1134 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1135 Inst.addOperand(MCOperand::createReg(Reg)); 1136 return MCDisassembler::Success; 1137 } 1138 1139 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1140 unsigned RegNo, 1141 uint64_t Address, 1142 const void *Decoder) { 1143 if (RegNo > 7) 1144 return MCDisassembler::Fail; 1145 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1146 Inst.addOperand(MCOperand::createReg(Reg)); 1147 return MCDisassembler::Success; 1148 } 1149 1150 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1151 unsigned RegNo, 1152 uint64_t Address, 1153 const void *Decoder) { 1154 if (RegNo > 31) 1155 return MCDisassembler::Fail; 1156 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1157 Inst.addOperand(MCOperand::createReg(Reg)); 1158 return MCDisassembler::Success; 1159 } 1160 1161 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1162 unsigned RegNo, 1163 uint64_t Address, 1164 const void *Decoder) { 1165 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1166 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1167 1168 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1169 } 1170 1171 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1172 unsigned RegNo, 1173 uint64_t Address, 1174 const void *Decoder) { 1175 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1176 } 1177 1178 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1179 unsigned RegNo, 1180 uint64_t Address, 1181 const void *Decoder) { 1182 if (RegNo > 31) 1183 return MCDisassembler::Fail; 1184 1185 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1186 Inst.addOperand(MCOperand::createReg(Reg)); 1187 return MCDisassembler::Success; 1188 } 1189 1190 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1191 unsigned RegNo, 1192 uint64_t Address, 1193 const void *Decoder) { 1194 if (RegNo > 31) 1195 return MCDisassembler::Fail; 1196 1197 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1198 Inst.addOperand(MCOperand::createReg(Reg)); 1199 return MCDisassembler::Success; 1200 } 1201 1202 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1203 unsigned RegNo, 1204 uint64_t Address, 1205 const void *Decoder) { 1206 if (RegNo > 31) 1207 return MCDisassembler::Fail; 1208 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1209 Inst.addOperand(MCOperand::createReg(Reg)); 1210 return MCDisassembler::Success; 1211 } 1212 1213 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1214 unsigned RegNo, 1215 uint64_t Address, 1216 const void *Decoder) { 1217 if (RegNo > 7) 1218 return MCDisassembler::Fail; 1219 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1220 Inst.addOperand(MCOperand::createReg(Reg)); 1221 return MCDisassembler::Success; 1222 } 1223 1224 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1225 uint64_t Address, 1226 const void *Decoder) { 1227 if (RegNo > 31) 1228 return MCDisassembler::Fail; 1229 1230 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1231 Inst.addOperand(MCOperand::createReg(Reg)); 1232 return MCDisassembler::Success; 1233 } 1234 1235 static DecodeStatus DecodeMem(MCInst &Inst, 1236 unsigned Insn, 1237 uint64_t Address, 1238 const void *Decoder) { 1239 int Offset = SignExtend32<16>(Insn & 0xffff); 1240 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1241 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1242 1243 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1244 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1245 1246 if (Inst.getOpcode() == Mips::SC || 1247 Inst.getOpcode() == Mips::SCD) 1248 Inst.addOperand(MCOperand::createReg(Reg)); 1249 1250 Inst.addOperand(MCOperand::createReg(Reg)); 1251 Inst.addOperand(MCOperand::createReg(Base)); 1252 Inst.addOperand(MCOperand::createImm(Offset)); 1253 1254 return MCDisassembler::Success; 1255 } 1256 1257 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1258 unsigned Insn, 1259 uint64_t Address, 1260 const void *Decoder) { 1261 int Offset = SignExtend32<9>(Insn >> 7); 1262 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1263 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1264 1265 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1266 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1267 1268 if (Inst.getOpcode() == Mips::SCE) 1269 Inst.addOperand(MCOperand::createReg(Reg)); 1270 1271 Inst.addOperand(MCOperand::createReg(Reg)); 1272 Inst.addOperand(MCOperand::createReg(Base)); 1273 Inst.addOperand(MCOperand::createImm(Offset)); 1274 1275 return MCDisassembler::Success; 1276 } 1277 1278 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1279 unsigned Insn, 1280 uint64_t Address, 1281 const void *Decoder) { 1282 int Offset = SignExtend32<9>(Insn & 0x1ff); 1283 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1284 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1285 1286 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1287 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1288 1289 Inst.addOperand(MCOperand::createReg(Reg)); 1290 Inst.addOperand(MCOperand::createReg(Base)); 1291 Inst.addOperand(MCOperand::createImm(Offset)); 1292 1293 return MCDisassembler::Success; 1294 } 1295 1296 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1297 unsigned Insn, 1298 uint64_t Address, 1299 const void *Decoder) { 1300 int Offset = SignExtend32<16>(Insn & 0xffff); 1301 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1302 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1303 1304 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1305 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1306 1307 Inst.addOperand(MCOperand::createReg(Reg)); 1308 Inst.addOperand(MCOperand::createReg(Base)); 1309 Inst.addOperand(MCOperand::createImm(Offset)); 1310 1311 return MCDisassembler::Success; 1312 } 1313 1314 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1315 unsigned Insn, 1316 uint64_t Address, 1317 const void *Decoder) { 1318 int Offset = SignExtend32<16>(Insn & 0xffff); 1319 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1320 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1321 1322 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1323 1324 Inst.addOperand(MCOperand::createReg(Base)); 1325 Inst.addOperand(MCOperand::createImm(Offset)); 1326 Inst.addOperand(MCOperand::createImm(Hint)); 1327 1328 return MCDisassembler::Success; 1329 } 1330 1331 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1332 unsigned Insn, 1333 uint64_t Address, 1334 const void *Decoder) { 1335 int Offset = SignExtend32<12>(Insn & 0xfff); 1336 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1337 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1338 1339 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1340 1341 Inst.addOperand(MCOperand::createReg(Base)); 1342 Inst.addOperand(MCOperand::createImm(Offset)); 1343 Inst.addOperand(MCOperand::createImm(Hint)); 1344 1345 return MCDisassembler::Success; 1346 } 1347 1348 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1349 unsigned Insn, 1350 uint64_t Address, 1351 const void *Decoder) { 1352 int Offset = SignExtend32<9>(Insn & 0x1ff); 1353 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1354 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1355 1356 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1357 1358 Inst.addOperand(MCOperand::createReg(Base)); 1359 Inst.addOperand(MCOperand::createImm(Offset)); 1360 Inst.addOperand(MCOperand::createImm(Hint)); 1361 1362 return MCDisassembler::Success; 1363 } 1364 1365 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1366 unsigned Insn, 1367 uint64_t Address, 1368 const void *Decoder) { 1369 int Offset = SignExtend32<9>(Insn >> 7); 1370 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1371 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1372 1373 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1374 1375 Inst.addOperand(MCOperand::createReg(Base)); 1376 Inst.addOperand(MCOperand::createImm(Offset)); 1377 Inst.addOperand(MCOperand::createImm(Hint)); 1378 1379 return MCDisassembler::Success; 1380 } 1381 1382 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1383 unsigned Insn, 1384 uint64_t Address, 1385 const void *Decoder) { 1386 int Offset = SignExtend32<9>(Insn & 0x1ff); 1387 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1388 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1389 1390 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1391 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1392 1393 Inst.addOperand(MCOperand::createReg(Reg)); 1394 Inst.addOperand(MCOperand::createReg(Base)); 1395 Inst.addOperand(MCOperand::createImm(Offset)); 1396 1397 return MCDisassembler::Success; 1398 } 1399 1400 static DecodeStatus DecodeSyncI(MCInst &Inst, 1401 unsigned Insn, 1402 uint64_t Address, 1403 const void *Decoder) { 1404 int Offset = SignExtend32<16>(Insn & 0xffff); 1405 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1406 1407 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1408 1409 Inst.addOperand(MCOperand::createReg(Base)); 1410 Inst.addOperand(MCOperand::createImm(Offset)); 1411 1412 return MCDisassembler::Success; 1413 } 1414 1415 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1416 unsigned Insn, 1417 uint64_t Address, 1418 const void *Decoder) { 1419 int Immediate = SignExtend32<16>(Insn & 0xffff); 1420 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1421 1422 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1423 1424 Inst.addOperand(MCOperand::createReg(Base)); 1425 Inst.addOperand(MCOperand::createImm(Immediate)); 1426 1427 return MCDisassembler::Success; 1428 } 1429 1430 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1431 uint64_t Address, const void *Decoder) { 1432 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1433 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1434 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1435 1436 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1437 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1438 1439 Inst.addOperand(MCOperand::createReg(Reg)); 1440 Inst.addOperand(MCOperand::createReg(Base)); 1441 1442 // The immediate field of an LD/ST instruction is scaled which means it must 1443 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1444 // data format. 1445 // .b - 1 byte 1446 // .h - 2 bytes 1447 // .w - 4 bytes 1448 // .d - 8 bytes 1449 switch(Inst.getOpcode()) 1450 { 1451 default: 1452 assert (0 && "Unexpected instruction"); 1453 return MCDisassembler::Fail; 1454 break; 1455 case Mips::LD_B: 1456 case Mips::ST_B: 1457 Inst.addOperand(MCOperand::createImm(Offset)); 1458 break; 1459 case Mips::LD_H: 1460 case Mips::ST_H: 1461 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1462 break; 1463 case Mips::LD_W: 1464 case Mips::ST_W: 1465 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1466 break; 1467 case Mips::LD_D: 1468 case Mips::ST_D: 1469 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1470 break; 1471 } 1472 1473 return MCDisassembler::Success; 1474 } 1475 1476 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1477 unsigned Insn, 1478 uint64_t Address, 1479 const void *Decoder) { 1480 unsigned Offset = Insn & 0xf; 1481 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1482 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1483 1484 switch (Inst.getOpcode()) { 1485 case Mips::LBU16_MM: 1486 case Mips::LHU16_MM: 1487 case Mips::LW16_MM: 1488 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1489 == MCDisassembler::Fail) 1490 return MCDisassembler::Fail; 1491 break; 1492 case Mips::SB16_MM: 1493 case Mips::SB16_MMR6: 1494 case Mips::SH16_MM: 1495 case Mips::SH16_MMR6: 1496 case Mips::SW16_MM: 1497 case Mips::SW16_MMR6: 1498 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1499 == MCDisassembler::Fail) 1500 return MCDisassembler::Fail; 1501 break; 1502 } 1503 1504 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1505 == MCDisassembler::Fail) 1506 return MCDisassembler::Fail; 1507 1508 switch (Inst.getOpcode()) { 1509 case Mips::LBU16_MM: 1510 if (Offset == 0xf) 1511 Inst.addOperand(MCOperand::createImm(-1)); 1512 else 1513 Inst.addOperand(MCOperand::createImm(Offset)); 1514 break; 1515 case Mips::SB16_MM: 1516 case Mips::SB16_MMR6: 1517 Inst.addOperand(MCOperand::createImm(Offset)); 1518 break; 1519 case Mips::LHU16_MM: 1520 case Mips::SH16_MM: 1521 case Mips::SH16_MMR6: 1522 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1523 break; 1524 case Mips::LW16_MM: 1525 case Mips::SW16_MM: 1526 case Mips::SW16_MMR6: 1527 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1528 break; 1529 } 1530 1531 return MCDisassembler::Success; 1532 } 1533 1534 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1535 unsigned Insn, 1536 uint64_t Address, 1537 const void *Decoder) { 1538 unsigned Offset = Insn & 0x1F; 1539 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1540 1541 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1542 1543 Inst.addOperand(MCOperand::createReg(Reg)); 1544 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1545 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1546 1547 return MCDisassembler::Success; 1548 } 1549 1550 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1551 unsigned Insn, 1552 uint64_t Address, 1553 const void *Decoder) { 1554 unsigned Offset = Insn & 0x7F; 1555 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1556 1557 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1558 1559 Inst.addOperand(MCOperand::createReg(Reg)); 1560 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1561 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1562 1563 return MCDisassembler::Success; 1564 } 1565 1566 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1567 unsigned Insn, 1568 uint64_t Address, 1569 const void *Decoder) { 1570 int Offset; 1571 switch (Inst.getOpcode()) { 1572 case Mips::LWM16_MMR6: 1573 case Mips::SWM16_MMR6: 1574 Offset = fieldFromInstruction(Insn, 4, 4); 1575 break; 1576 default: 1577 Offset = SignExtend32<4>(Insn & 0xf); 1578 break; 1579 } 1580 1581 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1582 == MCDisassembler::Fail) 1583 return MCDisassembler::Fail; 1584 1585 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1586 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1587 1588 return MCDisassembler::Success; 1589 } 1590 1591 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1592 unsigned Insn, 1593 uint64_t Address, 1594 const void *Decoder) { 1595 int Offset = SignExtend32<9>(Insn & 0x1ff); 1596 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1597 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1598 1599 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1600 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1601 1602 if (Inst.getOpcode() == Mips::SCE_MM) 1603 Inst.addOperand(MCOperand::createReg(Reg)); 1604 1605 Inst.addOperand(MCOperand::createReg(Reg)); 1606 Inst.addOperand(MCOperand::createReg(Base)); 1607 Inst.addOperand(MCOperand::createImm(Offset)); 1608 1609 return MCDisassembler::Success; 1610 } 1611 1612 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1613 unsigned Insn, 1614 uint64_t Address, 1615 const void *Decoder) { 1616 int Offset = SignExtend32<12>(Insn & 0x0fff); 1617 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1618 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1619 1620 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1621 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1622 1623 switch (Inst.getOpcode()) { 1624 case Mips::SWM32_MM: 1625 case Mips::LWM32_MM: 1626 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1627 == MCDisassembler::Fail) 1628 return MCDisassembler::Fail; 1629 Inst.addOperand(MCOperand::createReg(Base)); 1630 Inst.addOperand(MCOperand::createImm(Offset)); 1631 break; 1632 case Mips::SC_MM: 1633 Inst.addOperand(MCOperand::createReg(Reg)); 1634 // fallthrough 1635 default: 1636 Inst.addOperand(MCOperand::createReg(Reg)); 1637 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1638 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1639 Inst.addOperand(MCOperand::createReg(Reg+1)); 1640 1641 Inst.addOperand(MCOperand::createReg(Base)); 1642 Inst.addOperand(MCOperand::createImm(Offset)); 1643 } 1644 1645 return MCDisassembler::Success; 1646 } 1647 1648 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1649 unsigned Insn, 1650 uint64_t Address, 1651 const void *Decoder) { 1652 int Offset = SignExtend32<16>(Insn & 0xffff); 1653 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1654 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1655 1656 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1657 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1658 1659 Inst.addOperand(MCOperand::createReg(Reg)); 1660 Inst.addOperand(MCOperand::createReg(Base)); 1661 Inst.addOperand(MCOperand::createImm(Offset)); 1662 1663 return MCDisassembler::Success; 1664 } 1665 1666 static DecodeStatus DecodeFMem(MCInst &Inst, 1667 unsigned Insn, 1668 uint64_t Address, 1669 const void *Decoder) { 1670 int Offset = SignExtend32<16>(Insn & 0xffff); 1671 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1672 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1673 1674 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1675 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1676 1677 Inst.addOperand(MCOperand::createReg(Reg)); 1678 Inst.addOperand(MCOperand::createReg(Base)); 1679 Inst.addOperand(MCOperand::createImm(Offset)); 1680 1681 return MCDisassembler::Success; 1682 } 1683 1684 static DecodeStatus DecodeFMem2(MCInst &Inst, 1685 unsigned Insn, 1686 uint64_t Address, 1687 const void *Decoder) { 1688 int Offset = SignExtend32<16>(Insn & 0xffff); 1689 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1690 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1691 1692 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1693 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1694 1695 Inst.addOperand(MCOperand::createReg(Reg)); 1696 Inst.addOperand(MCOperand::createReg(Base)); 1697 Inst.addOperand(MCOperand::createImm(Offset)); 1698 1699 return MCDisassembler::Success; 1700 } 1701 1702 static DecodeStatus DecodeFMem3(MCInst &Inst, 1703 unsigned Insn, 1704 uint64_t Address, 1705 const void *Decoder) { 1706 int Offset = SignExtend32<16>(Insn & 0xffff); 1707 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1708 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1709 1710 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1711 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1712 1713 Inst.addOperand(MCOperand::createReg(Reg)); 1714 Inst.addOperand(MCOperand::createReg(Base)); 1715 Inst.addOperand(MCOperand::createImm(Offset)); 1716 1717 return MCDisassembler::Success; 1718 } 1719 1720 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1721 unsigned Insn, 1722 uint64_t Address, 1723 const void *Decoder) { 1724 int Offset = SignExtend32<11>(Insn & 0x07ff); 1725 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1726 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1727 1728 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1729 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1730 1731 Inst.addOperand(MCOperand::createReg(Reg)); 1732 Inst.addOperand(MCOperand::createReg(Base)); 1733 Inst.addOperand(MCOperand::createImm(Offset)); 1734 1735 return MCDisassembler::Success; 1736 } 1737 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1738 unsigned Insn, 1739 uint64_t Address, 1740 const void *Decoder) { 1741 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1742 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1743 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1744 1745 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1746 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1747 1748 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1749 Inst.addOperand(MCOperand::createReg(Rt)); 1750 } 1751 1752 Inst.addOperand(MCOperand::createReg(Rt)); 1753 Inst.addOperand(MCOperand::createReg(Base)); 1754 Inst.addOperand(MCOperand::createImm(Offset)); 1755 1756 return MCDisassembler::Success; 1757 } 1758 1759 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1760 unsigned RegNo, 1761 uint64_t Address, 1762 const void *Decoder) { 1763 // Currently only hardware register 29 is supported. 1764 if (RegNo != 29) 1765 return MCDisassembler::Fail; 1766 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1767 return MCDisassembler::Success; 1768 } 1769 1770 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1771 unsigned RegNo, 1772 uint64_t Address, 1773 const void *Decoder) { 1774 if (RegNo > 30 || RegNo %2) 1775 return MCDisassembler::Fail; 1776 1777 ; 1778 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1779 Inst.addOperand(MCOperand::createReg(Reg)); 1780 return MCDisassembler::Success; 1781 } 1782 1783 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1784 unsigned RegNo, 1785 uint64_t Address, 1786 const void *Decoder) { 1787 if (RegNo >= 4) 1788 return MCDisassembler::Fail; 1789 1790 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1791 Inst.addOperand(MCOperand::createReg(Reg)); 1792 return MCDisassembler::Success; 1793 } 1794 1795 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1796 unsigned RegNo, 1797 uint64_t Address, 1798 const void *Decoder) { 1799 if (RegNo >= 4) 1800 return MCDisassembler::Fail; 1801 1802 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1803 Inst.addOperand(MCOperand::createReg(Reg)); 1804 return MCDisassembler::Success; 1805 } 1806 1807 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1808 unsigned RegNo, 1809 uint64_t Address, 1810 const void *Decoder) { 1811 if (RegNo >= 4) 1812 return MCDisassembler::Fail; 1813 1814 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1815 Inst.addOperand(MCOperand::createReg(Reg)); 1816 return MCDisassembler::Success; 1817 } 1818 1819 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1820 unsigned RegNo, 1821 uint64_t Address, 1822 const void *Decoder) { 1823 if (RegNo > 31) 1824 return MCDisassembler::Fail; 1825 1826 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1827 Inst.addOperand(MCOperand::createReg(Reg)); 1828 return MCDisassembler::Success; 1829 } 1830 1831 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1832 unsigned RegNo, 1833 uint64_t Address, 1834 const void *Decoder) { 1835 if (RegNo > 31) 1836 return MCDisassembler::Fail; 1837 1838 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1839 Inst.addOperand(MCOperand::createReg(Reg)); 1840 return MCDisassembler::Success; 1841 } 1842 1843 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1844 unsigned RegNo, 1845 uint64_t Address, 1846 const void *Decoder) { 1847 if (RegNo > 31) 1848 return MCDisassembler::Fail; 1849 1850 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1851 Inst.addOperand(MCOperand::createReg(Reg)); 1852 return MCDisassembler::Success; 1853 } 1854 1855 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1856 unsigned RegNo, 1857 uint64_t Address, 1858 const void *Decoder) { 1859 if (RegNo > 31) 1860 return MCDisassembler::Fail; 1861 1862 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1863 Inst.addOperand(MCOperand::createReg(Reg)); 1864 return MCDisassembler::Success; 1865 } 1866 1867 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1868 unsigned RegNo, 1869 uint64_t Address, 1870 const void *Decoder) { 1871 if (RegNo > 7) 1872 return MCDisassembler::Fail; 1873 1874 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1875 Inst.addOperand(MCOperand::createReg(Reg)); 1876 return MCDisassembler::Success; 1877 } 1878 1879 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1880 unsigned RegNo, 1881 uint64_t Address, 1882 const void *Decoder) { 1883 if (RegNo > 31) 1884 return MCDisassembler::Fail; 1885 1886 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1887 Inst.addOperand(MCOperand::createReg(Reg)); 1888 return MCDisassembler::Success; 1889 } 1890 1891 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1892 unsigned RegNo, 1893 uint64_t Address, 1894 const void *Decoder) { 1895 if (RegNo > 31) 1896 return MCDisassembler::Fail; 1897 1898 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1899 Inst.addOperand(MCOperand::createReg(Reg)); 1900 return MCDisassembler::Success; 1901 } 1902 1903 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1904 unsigned Offset, 1905 uint64_t Address, 1906 const void *Decoder) { 1907 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1908 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1909 return MCDisassembler::Success; 1910 } 1911 1912 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 1913 unsigned Offset, 1914 uint64_t Address, 1915 const void *Decoder) { 1916 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 1917 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1918 return MCDisassembler::Success; 1919 } 1920 1921 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1922 unsigned Insn, 1923 uint64_t Address, 1924 const void *Decoder) { 1925 1926 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1927 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1928 return MCDisassembler::Success; 1929 } 1930 1931 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1932 unsigned Offset, 1933 uint64_t Address, 1934 const void *Decoder) { 1935 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 1936 1937 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1938 return MCDisassembler::Success; 1939 } 1940 1941 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 1942 unsigned Offset, 1943 uint64_t Address, 1944 const void *Decoder) { 1945 int32_t BranchOffset = SignExtend32<21>(Offset) << 1; 1946 1947 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1948 return MCDisassembler::Success; 1949 } 1950 1951 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1952 unsigned Offset, 1953 uint64_t Address, 1954 const void *Decoder) { 1955 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 1956 1957 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1958 return MCDisassembler::Success; 1959 } 1960 1961 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1962 unsigned Offset, 1963 uint64_t Address, 1964 const void *Decoder) { 1965 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1966 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1967 return MCDisassembler::Success; 1968 } 1969 1970 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1971 unsigned Offset, 1972 uint64_t Address, 1973 const void *Decoder) { 1974 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1975 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1976 return MCDisassembler::Success; 1977 } 1978 1979 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1980 unsigned Offset, 1981 uint64_t Address, 1982 const void *Decoder) { 1983 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1984 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1985 return MCDisassembler::Success; 1986 } 1987 1988 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 1989 unsigned Offset, 1990 uint64_t Address, 1991 const void *Decoder) { 1992 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 1993 1994 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1995 return MCDisassembler::Success; 1996 } 1997 1998 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1999 unsigned Insn, 2000 uint64_t Address, 2001 const void *Decoder) { 2002 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2003 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2004 return MCDisassembler::Success; 2005 } 2006 2007 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2008 unsigned Value, 2009 uint64_t Address, 2010 const void *Decoder) { 2011 if (Value == 0) 2012 Inst.addOperand(MCOperand::createImm(1)); 2013 else if (Value == 0x7) 2014 Inst.addOperand(MCOperand::createImm(-1)); 2015 else 2016 Inst.addOperand(MCOperand::createImm(Value << 2)); 2017 return MCDisassembler::Success; 2018 } 2019 2020 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2021 unsigned Value, 2022 uint64_t Address, 2023 const void *Decoder) { 2024 if (Value == 0x7F) 2025 Inst.addOperand(MCOperand::createImm(-1)); 2026 else 2027 Inst.addOperand(MCOperand::createImm(Value)); 2028 return MCDisassembler::Success; 2029 } 2030 2031 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2032 unsigned Value, 2033 uint64_t Address, 2034 const void *Decoder) { 2035 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2036 return MCDisassembler::Success; 2037 } 2038 2039 template <unsigned Bits, int Offset, int Scale> 2040 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2041 uint64_t Address, 2042 const void *Decoder) { 2043 Value &= ((1 << Bits) - 1); 2044 Value *= Scale; 2045 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2046 return MCDisassembler::Success; 2047 } 2048 2049 template <unsigned Bits, int Offset, int ScaleBy> 2050 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2051 uint64_t Address, 2052 const void *Decoder) { 2053 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2054 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2055 return MCDisassembler::Success; 2056 } 2057 2058 static DecodeStatus DecodeInsSize(MCInst &Inst, 2059 unsigned Insn, 2060 uint64_t Address, 2061 const void *Decoder) { 2062 // First we need to grab the pos(lsb) from MCInst. 2063 int Pos = Inst.getOperand(2).getImm(); 2064 int Size = (int) Insn - Pos + 1; 2065 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2066 return MCDisassembler::Success; 2067 } 2068 2069 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2070 uint64_t Address, const void *Decoder) { 2071 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2072 return MCDisassembler::Success; 2073 } 2074 2075 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2076 uint64_t Address, const void *Decoder) { 2077 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2078 return MCDisassembler::Success; 2079 } 2080 2081 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2082 uint64_t Address, const void *Decoder) { 2083 int32_t DecodedValue; 2084 switch (Insn) { 2085 case 0: DecodedValue = 256; break; 2086 case 1: DecodedValue = 257; break; 2087 case 510: DecodedValue = -258; break; 2088 case 511: DecodedValue = -257; break; 2089 default: DecodedValue = SignExtend32<9>(Insn); break; 2090 } 2091 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2092 return MCDisassembler::Success; 2093 } 2094 2095 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2096 uint64_t Address, const void *Decoder) { 2097 // Insn must be >= 0, since it is unsigned that condition is always true. 2098 assert(Insn < 16); 2099 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2100 255, 32768, 65535}; 2101 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2102 return MCDisassembler::Success; 2103 } 2104 2105 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2106 unsigned Insn, 2107 uint64_t Address, 2108 const void *Decoder) { 2109 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2110 Mips::S6, Mips::S7, Mips::FP}; 2111 unsigned RegNum; 2112 2113 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2114 2115 // Empty register lists are not allowed. 2116 if (RegLst == 0) 2117 return MCDisassembler::Fail; 2118 2119 RegNum = RegLst & 0xf; 2120 2121 // RegLst values 10-15, and 26-31 are reserved. 2122 if (RegNum > 9) 2123 return MCDisassembler::Fail; 2124 2125 for (unsigned i = 0; i < RegNum; i++) 2126 Inst.addOperand(MCOperand::createReg(Regs[i])); 2127 2128 if (RegLst & 0x10) 2129 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2130 2131 return MCDisassembler::Success; 2132 } 2133 2134 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2135 uint64_t Address, 2136 const void *Decoder) { 2137 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2138 unsigned RegLst; 2139 switch(Inst.getOpcode()) { 2140 default: 2141 RegLst = fieldFromInstruction(Insn, 4, 2); 2142 break; 2143 case Mips::LWM16_MMR6: 2144 case Mips::SWM16_MMR6: 2145 RegLst = fieldFromInstruction(Insn, 8, 2); 2146 break; 2147 } 2148 unsigned RegNum = RegLst & 0x3; 2149 2150 for (unsigned i = 0; i <= RegNum; i++) 2151 Inst.addOperand(MCOperand::createReg(Regs[i])); 2152 2153 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2154 2155 return MCDisassembler::Success; 2156 } 2157 2158 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2159 uint64_t Address, const void *Decoder) { 2160 2161 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2162 2163 switch (RegPair) { 2164 default: 2165 return MCDisassembler::Fail; 2166 case 0: 2167 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2168 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2169 break; 2170 case 1: 2171 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2172 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2173 break; 2174 case 2: 2175 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2176 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2177 break; 2178 case 3: 2179 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2180 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2181 break; 2182 case 4: 2183 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2184 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2185 break; 2186 case 5: 2187 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2188 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2189 break; 2190 case 6: 2191 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2192 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2193 break; 2194 case 7: 2195 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2196 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2197 break; 2198 } 2199 2200 return MCDisassembler::Success; 2201 } 2202 2203 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2204 uint64_t Address, const void *Decoder) { 2205 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2206 return MCDisassembler::Success; 2207 } 2208 2209 template <typename InsnType> 2210 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2211 uint64_t Address, 2212 const void *Decoder) { 2213 // We have: 2214 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2215 // Invalid if rt == 0 2216 // BGTZALC_MMR6 if rs == 0 && rt != 0 2217 // BLTZALC_MMR6 if rs != 0 && rs == rt 2218 // BLTUC_MMR6 if rs != 0 && rs != rt 2219 2220 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2221 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2222 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2223 bool HasRs = false; 2224 bool HasRt = false; 2225 2226 if (Rt == 0) 2227 return MCDisassembler::Fail; 2228 else if (Rs == 0) { 2229 MI.setOpcode(Mips::BGTZALC_MMR6); 2230 HasRt = true; 2231 } 2232 else if (Rs == Rt) { 2233 MI.setOpcode(Mips::BLTZALC_MMR6); 2234 HasRs = true; 2235 } 2236 else { 2237 MI.setOpcode(Mips::BLTUC_MMR6); 2238 HasRs = true; 2239 HasRt = true; 2240 } 2241 2242 if (HasRs) 2243 MI.addOperand( 2244 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2245 2246 if (HasRt) 2247 MI.addOperand( 2248 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2249 2250 MI.addOperand(MCOperand::createImm(Imm)); 2251 2252 return MCDisassembler::Success; 2253 } 2254 2255 template <typename InsnType> 2256 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2257 uint64_t Address, 2258 const void *Decoder) { 2259 // We have: 2260 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2261 // Invalid if rs == 0 2262 // BLEZALC_MMR6 if rs == 0 && rt != 0 2263 // BGEZALC_MMR6 if rs == rt && rt != 0 2264 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2265 2266 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2267 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2268 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2269 bool HasRs = false; 2270 2271 if (Rt == 0) 2272 return MCDisassembler::Fail; 2273 else if (Rs == 0) 2274 MI.setOpcode(Mips::BLEZALC_MMR6); 2275 else if (Rs == Rt) 2276 MI.setOpcode(Mips::BGEZALC_MMR6); 2277 else { 2278 HasRs = true; 2279 MI.setOpcode(Mips::BGEUC_MMR6); 2280 } 2281 2282 if (HasRs) 2283 MI.addOperand( 2284 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2285 MI.addOperand( 2286 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2287 2288 MI.addOperand(MCOperand::createImm(Imm)); 2289 2290 return MCDisassembler::Success; 2291 } 2292