1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Mips Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "Mips.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } 67 68 bool hasCOP3() const { 69 // Only present in MIPS-I and MIPS-II 70 return !hasMips32() && !hasMips3(); 71 } 72 73 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 74 ArrayRef<uint8_t> Bytes, uint64_t Address, 75 raw_ostream &VStream, 76 raw_ostream &CStream) const override; 77 }; 78 79 } // end anonymous namespace 80 81 // Forward declare these because the autogenerated code will reference them. 82 // Definitions are further down. 83 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 99 unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 114 unsigned Insn, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 129 unsigned RegNo, 130 uint64_t Address, 131 const void *Decoder); 132 133 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 134 unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder); 137 138 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 139 unsigned RegNo, 140 uint64_t Address, 141 const void *Decoder); 142 143 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 193 unsigned RegNo, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 198 unsigned RegNo, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 203 unsigned RegNo, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 213 unsigned Offset, 214 uint64_t Address, 215 const void *Decoder); 216 217 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 218 unsigned Insn, 219 uint64_t Address, 220 const void *Decoder); 221 222 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 223 unsigned Offset, 224 uint64_t Address, 225 const void *Decoder); 226 227 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 233 unsigned Offset, 234 uint64_t Address, 235 const void *Decoder); 236 237 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 238 // shifted left by 1 bit. 239 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 240 unsigned Offset, 241 uint64_t Address, 242 const void *Decoder); 243 244 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 245 // shifted left by 1 bit. 246 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 247 unsigned Offset, 248 uint64_t Address, 249 const void *Decoder); 250 251 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 252 // shifted left by 1 bit. 253 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 254 unsigned Offset, 255 uint64_t Address, 256 const void *Decoder); 257 258 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 259 // shifted left by 1 bit. 260 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 261 unsigned Offset, 262 uint64_t Address, 263 const void *Decoder); 264 265 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 266 // shifted left by 1 bit. 267 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, 273 // which is shifted left by 2 bit. 274 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodeMem(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeMemEVA(MCInst &Inst, 285 unsigned Insn, 286 uint64_t Address, 287 const void *Decoder); 288 289 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 290 unsigned Insn, 291 uint64_t Address, 292 const void *Decoder); 293 294 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeSyncI(MCInst &Inst, 313 unsigned Insn, 314 uint64_t Address, 315 const void *Decoder); 316 317 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 318 unsigned Insn, 319 uint64_t Address, 320 const void *Decoder); 321 322 static DecodeStatus DecodeSynciR6(MCInst &Inst, 323 unsigned Insn, 324 uint64_t Address, 325 const void *Decoder); 326 327 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 328 uint64_t Address, const void *Decoder); 329 330 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 331 unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 336 unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 341 unsigned Insn, 342 uint64_t Address, 343 const void *Decoder); 344 345 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 346 unsigned Insn, 347 uint64_t Address, 348 const void *Decoder); 349 350 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 351 unsigned Insn, 352 uint64_t Address, 353 const void *Decoder); 354 355 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 356 unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 361 unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 374 const void *Decoder); 375 376 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 377 const void *Decoder); 378 379 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 382 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 383 uint64_t Address, 384 const void *Decoder); 385 386 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 387 unsigned Insn, 388 uint64_t Address, 389 const void *Decoder); 390 391 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 392 unsigned Value, 393 uint64_t Address, 394 const void *Decoder); 395 396 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 397 unsigned Value, 398 uint64_t Address, 399 const void *Decoder); 400 401 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 402 unsigned Value, 403 uint64_t Address, 404 const void *Decoder); 405 406 template <unsigned Bits, int Offset, int Scale> 407 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 408 uint64_t Address, 409 const void *Decoder); 410 411 template <unsigned Bits, int Offset> 412 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 413 uint64_t Address, 414 const void *Decoder) { 415 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 416 Decoder); 417 } 418 419 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 420 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 421 uint64_t Address, 422 const void *Decoder); 423 424 static DecodeStatus DecodeInsSize(MCInst &Inst, 425 unsigned Insn, 426 uint64_t Address, 427 const void *Decoder); 428 429 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 436 uint64_t Address, const void *Decoder); 437 438 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 439 uint64_t Address, const void *Decoder); 440 441 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 442 uint64_t Address, const void *Decoder); 443 444 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 445 /// handle. 446 template <typename InsnType> 447 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 452 uint64_t Address, const void *Decoder); 453 454 template <typename InsnType> 455 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 460 uint64_t Address, const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 464 const void *Decoder); 465 466 template <typename InsnType> 467 static DecodeStatus 468 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 469 const void *Decoder); 470 471 template <typename InsnType> 472 static DecodeStatus 473 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 474 const void *Decoder); 475 476 template <typename InsnType> 477 static DecodeStatus 478 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 479 const void *Decoder); 480 481 template <typename InsnType> 482 static DecodeStatus 483 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 484 const void *Decoder); 485 486 template <typename InsnType> 487 static DecodeStatus 488 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 489 const void *Decoder); 490 491 template <typename InsnType> 492 static DecodeStatus 493 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 494 const void *Decoder); 495 496 template <typename InsnType> 497 static DecodeStatus 498 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 499 const void *Decoder); 500 501 template <typename InsnType> 502 static DecodeStatus 503 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 504 const void *Decoder); 505 506 template <typename InsnType> 507 static DecodeStatus 508 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 509 const void *Decoder); 510 511 template <typename InsnType> 512 static DecodeStatus 513 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 514 const void *Decoder); 515 516 template <typename InsnType> 517 static DecodeStatus 518 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 519 const void *Decoder); 520 521 template <typename InsnType> 522 static DecodeStatus 523 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 524 const void *Decoder); 525 526 template <typename InsnType> 527 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 528 const void *Decoder); 529 530 template <typename InsnType> 531 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 532 const void *Decoder); 533 534 template <typename InsnType> 535 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 536 const void *Decoder); 537 538 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 539 uint64_t Address, 540 const void *Decoder); 541 542 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 543 uint64_t Address, 544 const void *Decoder); 545 546 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 547 uint64_t Address, 548 const void *Decoder); 549 550 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 551 uint64_t Address, const void *Decoder); 552 553 static MCDisassembler *createMipsDisassembler( 554 const Target &T, 555 const MCSubtargetInfo &STI, 556 MCContext &Ctx) { 557 return new MipsDisassembler(STI, Ctx, true); 558 } 559 560 static MCDisassembler *createMipselDisassembler( 561 const Target &T, 562 const MCSubtargetInfo &STI, 563 MCContext &Ctx) { 564 return new MipsDisassembler(STI, Ctx, false); 565 } 566 567 extern "C" void LLVMInitializeMipsDisassembler() { 568 // Register the disassembler. 569 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 570 createMipsDisassembler); 571 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 572 createMipselDisassembler); 573 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 574 createMipsDisassembler); 575 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 576 createMipselDisassembler); 577 } 578 579 #include "MipsGenDisassemblerTables.inc" 580 581 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 582 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 583 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 584 return *(RegInfo->getRegClass(RC).begin() + RegNo); 585 } 586 587 template <typename InsnType> 588 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 589 const void *Decoder) { 590 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 591 592 // The size of the n field depends on the element size 593 // The register class also depends on this. 594 InsnType tmp = fieldFromInstruction(insn, 17, 5); 595 unsigned NSize = 0; 596 DecodeFN RegDecoder = nullptr; 597 if ((tmp & 0x18) == 0x00) { // INSVE_B 598 NSize = 4; 599 RegDecoder = DecodeMSA128BRegisterClass; 600 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 601 NSize = 3; 602 RegDecoder = DecodeMSA128HRegisterClass; 603 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 604 NSize = 2; 605 RegDecoder = DecodeMSA128WRegisterClass; 606 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 607 NSize = 1; 608 RegDecoder = DecodeMSA128DRegisterClass; 609 } else 610 llvm_unreachable("Invalid encoding"); 611 612 assert(NSize != 0 && RegDecoder != nullptr); 613 614 // $wd 615 tmp = fieldFromInstruction(insn, 6, 5); 616 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 617 return MCDisassembler::Fail; 618 // $wd_in 619 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 620 return MCDisassembler::Fail; 621 // $n 622 tmp = fieldFromInstruction(insn, 16, NSize); 623 MI.addOperand(MCOperand::createImm(tmp)); 624 // $ws 625 tmp = fieldFromInstruction(insn, 11, 5); 626 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 627 return MCDisassembler::Fail; 628 // $n2 629 MI.addOperand(MCOperand::createImm(0)); 630 631 return MCDisassembler::Success; 632 } 633 634 template <typename InsnType> 635 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 636 uint64_t Address, const void *Decoder) { 637 InsnType Rs = fieldFromInstruction(insn, 16, 5); 638 InsnType Imm = fieldFromInstruction(insn, 0, 16); 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 640 Rs))); 641 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 642 Rs))); 643 MI.addOperand(MCOperand::createImm(Imm)); 644 645 return MCDisassembler::Success; 646 } 647 648 template <typename InsnType> 649 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 650 const void *Decoder) { 651 InsnType Rs = fieldFromInstruction(insn, 21, 5); 652 InsnType Imm = fieldFromInstruction(insn, 0, 16); 653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 654 Rs))); 655 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 656 Rs))); 657 MI.addOperand(MCOperand::createImm(Imm)); 658 659 return MCDisassembler::Success; 660 } 661 662 template <typename InsnType> 663 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 664 uint64_t Address, 665 const void *Decoder) { 666 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 667 // (otherwise we would have matched the ADDI instruction from the earlier 668 // ISA's instead). 669 // 670 // We have: 671 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 672 // BOVC if rs >= rt 673 // BEQZALC if rs == 0 && rt != 0 674 // BEQC if rs < rt && rs != 0 675 676 InsnType Rs = fieldFromInstruction(insn, 21, 5); 677 InsnType Rt = fieldFromInstruction(insn, 16, 5); 678 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 679 bool HasRs = false; 680 681 if (Rs >= Rt) { 682 MI.setOpcode(Mips::BOVC); 683 HasRs = true; 684 } else if (Rs != 0 && Rs < Rt) { 685 MI.setOpcode(Mips::BEQC); 686 HasRs = true; 687 } else 688 MI.setOpcode(Mips::BEQZALC); 689 690 if (HasRs) 691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 692 Rs))); 693 694 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 695 Rt))); 696 MI.addOperand(MCOperand::createImm(Imm)); 697 698 return MCDisassembler::Success; 699 } 700 701 template <typename InsnType> 702 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 703 uint64_t Address, 704 const void *Decoder) { 705 InsnType Rt = fieldFromInstruction(insn, 21, 5); 706 InsnType Rs = fieldFromInstruction(insn, 16, 5); 707 int64_t Imm = 0; 708 709 if (Rs >= Rt) { 710 MI.setOpcode(Mips::BOVC_MMR6); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rt))); 713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 714 Rs))); 715 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 716 } else if (Rs != 0 && Rs < Rt) { 717 MI.setOpcode(Mips::BEQC_MMR6); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rs))); 720 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 721 Rt))); 722 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 723 } else { 724 MI.setOpcode(Mips::BEQZALC_MMR6); 725 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 726 Rt))); 727 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 728 } 729 730 MI.addOperand(MCOperand::createImm(Imm)); 731 732 return MCDisassembler::Success; 733 } 734 735 template <typename InsnType> 736 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 737 uint64_t Address, 738 const void *Decoder) { 739 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 740 // (otherwise we would have matched the ADDI instruction from the earlier 741 // ISA's instead). 742 // 743 // We have: 744 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 745 // BNVC if rs >= rt 746 // BNEZALC if rs == 0 && rt != 0 747 // BNEC if rs < rt && rs != 0 748 749 InsnType Rs = fieldFromInstruction(insn, 21, 5); 750 InsnType Rt = fieldFromInstruction(insn, 16, 5); 751 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 752 bool HasRs = false; 753 754 if (Rs >= Rt) { 755 MI.setOpcode(Mips::BNVC); 756 HasRs = true; 757 } else if (Rs != 0 && Rs < Rt) { 758 MI.setOpcode(Mips::BNEC); 759 HasRs = true; 760 } else 761 MI.setOpcode(Mips::BNEZALC); 762 763 if (HasRs) 764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 765 Rs))); 766 767 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 768 Rt))); 769 MI.addOperand(MCOperand::createImm(Imm)); 770 771 return MCDisassembler::Success; 772 } 773 774 template <typename InsnType> 775 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 776 uint64_t Address, 777 const void *Decoder) { 778 InsnType Rt = fieldFromInstruction(insn, 21, 5); 779 InsnType Rs = fieldFromInstruction(insn, 16, 5); 780 int64_t Imm = 0; 781 782 if (Rs >= Rt) { 783 MI.setOpcode(Mips::BNVC_MMR6); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rt))); 786 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 787 Rs))); 788 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 789 } else if (Rs != 0 && Rs < Rt) { 790 MI.setOpcode(Mips::BNEC_MMR6); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rs))); 793 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 794 Rt))); 795 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 796 } else { 797 MI.setOpcode(Mips::BNEZALC_MMR6); 798 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 799 Rt))); 800 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 801 } 802 803 MI.addOperand(MCOperand::createImm(Imm)); 804 805 return MCDisassembler::Success; 806 } 807 808 template <typename InsnType> 809 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 810 uint64_t Address, 811 const void *Decoder) { 812 // We have: 813 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 814 // Invalid if rt == 0 815 // BGTZC_MMR6 if rs == 0 && rt != 0 816 // BLTZC_MMR6 if rs == rt && rt != 0 817 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 818 819 InsnType Rt = fieldFromInstruction(insn, 21, 5); 820 InsnType Rs = fieldFromInstruction(insn, 16, 5); 821 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 822 bool HasRs = false; 823 824 if (Rt == 0) 825 return MCDisassembler::Fail; 826 else if (Rs == 0) 827 MI.setOpcode(Mips::BGTZC_MMR6); 828 else if (Rs == Rt) 829 MI.setOpcode(Mips::BLTZC_MMR6); 830 else { 831 MI.setOpcode(Mips::BLTC_MMR6); 832 HasRs = true; 833 } 834 835 if (HasRs) 836 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 837 Rs))); 838 839 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 840 Rt))); 841 842 MI.addOperand(MCOperand::createImm(Imm)); 843 844 return MCDisassembler::Success; 845 } 846 847 template <typename InsnType> 848 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 849 uint64_t Address, 850 const void *Decoder) { 851 // We have: 852 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 853 // Invalid if rt == 0 854 // BLEZC_MMR6 if rs == 0 && rt != 0 855 // BGEZC_MMR6 if rs == rt && rt != 0 856 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 857 858 InsnType Rt = fieldFromInstruction(insn, 21, 5); 859 InsnType Rs = fieldFromInstruction(insn, 16, 5); 860 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 861 bool HasRs = false; 862 863 if (Rt == 0) 864 return MCDisassembler::Fail; 865 else if (Rs == 0) 866 MI.setOpcode(Mips::BLEZC_MMR6); 867 else if (Rs == Rt) 868 MI.setOpcode(Mips::BGEZC_MMR6); 869 else { 870 HasRs = true; 871 MI.setOpcode(Mips::BGEC_MMR6); 872 } 873 874 if (HasRs) 875 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 876 Rs))); 877 878 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 879 Rt))); 880 881 MI.addOperand(MCOperand::createImm(Imm)); 882 883 return MCDisassembler::Success; 884 } 885 886 template <typename InsnType> 887 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 888 uint64_t Address, 889 const void *Decoder) { 890 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 891 // (otherwise we would have matched the BLEZL instruction from the earlier 892 // ISA's instead). 893 // 894 // We have: 895 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 896 // Invalid if rs == 0 897 // BLEZC if rs == 0 && rt != 0 898 // BGEZC if rs == rt && rt != 0 899 // BGEC if rs != rt && rs != 0 && rt != 0 900 901 InsnType Rs = fieldFromInstruction(insn, 21, 5); 902 InsnType Rt = fieldFromInstruction(insn, 16, 5); 903 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 904 bool HasRs = false; 905 906 if (Rt == 0) 907 return MCDisassembler::Fail; 908 else if (Rs == 0) 909 MI.setOpcode(Mips::BLEZC); 910 else if (Rs == Rt) 911 MI.setOpcode(Mips::BGEZC); 912 else { 913 HasRs = true; 914 MI.setOpcode(Mips::BGEC); 915 } 916 917 if (HasRs) 918 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 919 Rs))); 920 921 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 922 Rt))); 923 924 MI.addOperand(MCOperand::createImm(Imm)); 925 926 return MCDisassembler::Success; 927 } 928 929 template <typename InsnType> 930 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 931 uint64_t Address, 932 const void *Decoder) { 933 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 934 // (otherwise we would have matched the BGTZL instruction from the earlier 935 // ISA's instead). 936 // 937 // We have: 938 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 939 // Invalid if rs == 0 940 // BGTZC if rs == 0 && rt != 0 941 // BLTZC if rs == rt && rt != 0 942 // BLTC if rs != rt && rs != 0 && rt != 0 943 944 bool HasRs = false; 945 946 InsnType Rs = fieldFromInstruction(insn, 21, 5); 947 InsnType Rt = fieldFromInstruction(insn, 16, 5); 948 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 949 950 if (Rt == 0) 951 return MCDisassembler::Fail; 952 else if (Rs == 0) 953 MI.setOpcode(Mips::BGTZC); 954 else if (Rs == Rt) 955 MI.setOpcode(Mips::BLTZC); 956 else { 957 MI.setOpcode(Mips::BLTC); 958 HasRs = true; 959 } 960 961 if (HasRs) 962 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 963 Rs))); 964 965 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 966 Rt))); 967 968 MI.addOperand(MCOperand::createImm(Imm)); 969 970 return MCDisassembler::Success; 971 } 972 973 template <typename InsnType> 974 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 975 uint64_t Address, 976 const void *Decoder) { 977 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 978 // (otherwise we would have matched the BGTZ instruction from the earlier 979 // ISA's instead). 980 // 981 // We have: 982 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 983 // BGTZ if rt == 0 984 // BGTZALC if rs == 0 && rt != 0 985 // BLTZALC if rs != 0 && rs == rt 986 // BLTUC if rs != 0 && rs != rt 987 988 InsnType Rs = fieldFromInstruction(insn, 21, 5); 989 InsnType Rt = fieldFromInstruction(insn, 16, 5); 990 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 991 bool HasRs = false; 992 bool HasRt = false; 993 994 if (Rt == 0) { 995 MI.setOpcode(Mips::BGTZ); 996 HasRs = true; 997 } else if (Rs == 0) { 998 MI.setOpcode(Mips::BGTZALC); 999 HasRt = true; 1000 } else if (Rs == Rt) { 1001 MI.setOpcode(Mips::BLTZALC); 1002 HasRs = true; 1003 } else { 1004 MI.setOpcode(Mips::BLTUC); 1005 HasRs = true; 1006 HasRt = true; 1007 } 1008 1009 if (HasRs) 1010 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1011 Rs))); 1012 1013 if (HasRt) 1014 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1015 Rt))); 1016 1017 MI.addOperand(MCOperand::createImm(Imm)); 1018 1019 return MCDisassembler::Success; 1020 } 1021 1022 template <typename InsnType> 1023 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1024 uint64_t Address, 1025 const void *Decoder) { 1026 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1027 // (otherwise we would have matched the BLEZL instruction from the earlier 1028 // ISA's instead). 1029 // 1030 // We have: 1031 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1032 // Invalid if rs == 0 1033 // BLEZALC if rs == 0 && rt != 0 1034 // BGEZALC if rs == rt && rt != 0 1035 // BGEUC if rs != rt && rs != 0 && rt != 0 1036 1037 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1038 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1039 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1040 bool HasRs = false; 1041 1042 if (Rt == 0) 1043 return MCDisassembler::Fail; 1044 else if (Rs == 0) 1045 MI.setOpcode(Mips::BLEZALC); 1046 else if (Rs == Rt) 1047 MI.setOpcode(Mips::BGEZALC); 1048 else { 1049 HasRs = true; 1050 MI.setOpcode(Mips::BGEUC); 1051 } 1052 1053 if (HasRs) 1054 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1055 Rs))); 1056 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1057 Rt))); 1058 1059 MI.addOperand(MCOperand::createImm(Imm)); 1060 1061 return MCDisassembler::Success; 1062 } 1063 1064 // Override the generated disassembler to produce DEXT all the time. This is 1065 // for feature / behaviour parity with binutils. 1066 template <typename InsnType> 1067 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1068 const void *Decoder) { 1069 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1070 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1071 unsigned Size = 0; 1072 unsigned Pos = 0; 1073 1074 switch (MI.getOpcode()) { 1075 case Mips::DEXT: 1076 Pos = Lsb; 1077 Size = Msbd + 1; 1078 break; 1079 case Mips::DEXTM: 1080 Pos = Lsb; 1081 Size = Msbd + 1 + 32; 1082 break; 1083 case Mips::DEXTU: 1084 Pos = Lsb + 32; 1085 Size = Msbd + 1; 1086 break; 1087 default: 1088 llvm_unreachable("Unknown DEXT instruction!"); 1089 } 1090 1091 MI.setOpcode(Mips::DEXT); 1092 1093 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1094 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1095 1096 MI.addOperand( 1097 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1098 MI.addOperand( 1099 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1100 MI.addOperand(MCOperand::createImm(Pos)); 1101 MI.addOperand(MCOperand::createImm(Size)); 1102 1103 return MCDisassembler::Success; 1104 } 1105 1106 // Override the generated disassembler to produce DINS all the time. This is 1107 // for feature / behaviour parity with binutils. 1108 template <typename InsnType> 1109 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1110 const void *Decoder) { 1111 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1112 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1113 unsigned Size = 0; 1114 unsigned Pos = 0; 1115 1116 switch (MI.getOpcode()) { 1117 case Mips::DINS: 1118 Pos = Lsb; 1119 Size = Msbd + 1 - Pos; 1120 break; 1121 case Mips::DINSM: 1122 Pos = Lsb; 1123 Size = Msbd + 33 - Pos; 1124 break; 1125 case Mips::DINSU: 1126 Pos = Lsb + 32; 1127 // mbsd = pos + size - 33 1128 // mbsd - pos + 33 = size 1129 Size = Msbd + 33 - Pos; 1130 break; 1131 default: 1132 llvm_unreachable("Unknown DINS instruction!"); 1133 } 1134 1135 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1136 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1137 1138 MI.setOpcode(Mips::DINS); 1139 MI.addOperand( 1140 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1141 MI.addOperand( 1142 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1143 MI.addOperand(MCOperand::createImm(Pos)); 1144 MI.addOperand(MCOperand::createImm(Size)); 1145 1146 return MCDisassembler::Success; 1147 } 1148 1149 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1150 template <typename InsnType> 1151 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1152 const void *Decoder) { 1153 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1154 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1155 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1156 Rt))); 1157 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1158 Rs))); 1159 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1160 Rt))); 1161 return MCDisassembler::Success; 1162 } 1163 1164 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1165 /// according to the given endianness. 1166 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1167 uint64_t &Size, uint32_t &Insn, 1168 bool IsBigEndian) { 1169 // We want to read exactly 2 Bytes of data. 1170 if (Bytes.size() < 2) { 1171 Size = 0; 1172 return MCDisassembler::Fail; 1173 } 1174 1175 if (IsBigEndian) { 1176 Insn = (Bytes[0] << 8) | Bytes[1]; 1177 } else { 1178 Insn = (Bytes[1] << 8) | Bytes[0]; 1179 } 1180 1181 return MCDisassembler::Success; 1182 } 1183 1184 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1185 /// according to the given endianness. 1186 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1187 uint64_t &Size, uint32_t &Insn, 1188 bool IsBigEndian, bool IsMicroMips) { 1189 // We want to read exactly 4 Bytes of data. 1190 if (Bytes.size() < 4) { 1191 Size = 0; 1192 return MCDisassembler::Fail; 1193 } 1194 1195 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1196 // always precede the low 16 bits in the instruction stream (that is, they 1197 // are placed at lower addresses in the instruction stream). 1198 // 1199 // microMIPS byte ordering: 1200 // Big-endian: 0 | 1 | 2 | 3 1201 // Little-endian: 1 | 0 | 3 | 2 1202 1203 if (IsBigEndian) { 1204 // Encoded as a big-endian 32-bit word in the stream. 1205 Insn = 1206 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1207 } else { 1208 if (IsMicroMips) { 1209 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1210 (Bytes[1] << 24); 1211 } else { 1212 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1213 (Bytes[3] << 24); 1214 } 1215 } 1216 1217 return MCDisassembler::Success; 1218 } 1219 1220 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1221 ArrayRef<uint8_t> Bytes, 1222 uint64_t Address, 1223 raw_ostream &VStream, 1224 raw_ostream &CStream) const { 1225 uint32_t Insn; 1226 DecodeStatus Result; 1227 Size = 0; 1228 1229 if (IsMicroMips) { 1230 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1231 if (Result == MCDisassembler::Fail) 1232 return MCDisassembler::Fail; 1233 1234 if (hasMips32r6()) { 1235 LLVM_DEBUG( 1236 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1237 // Calling the auto-generated decoder function for microMIPS32R6 1238 // 16-bit instructions. 1239 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1240 Address, this, STI); 1241 if (Result != MCDisassembler::Fail) { 1242 Size = 2; 1243 return Result; 1244 } 1245 } 1246 1247 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1248 // Calling the auto-generated decoder function for microMIPS 16-bit 1249 // instructions. 1250 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1251 this, STI); 1252 if (Result != MCDisassembler::Fail) { 1253 Size = 2; 1254 return Result; 1255 } 1256 1257 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1258 if (Result == MCDisassembler::Fail) 1259 return MCDisassembler::Fail; 1260 1261 if (hasMips32r6()) { 1262 LLVM_DEBUG( 1263 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1264 // Calling the auto-generated decoder function. 1265 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, 1266 Address, this, STI); 1267 if (Result != MCDisassembler::Fail) { 1268 Size = 4; 1269 return Result; 1270 } 1271 } 1272 1273 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1274 // Calling the auto-generated decoder function. 1275 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1276 this, STI); 1277 if (Result != MCDisassembler::Fail) { 1278 Size = 4; 1279 return Result; 1280 } 1281 1282 if (isFP64()) { 1283 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1284 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1285 Address, this, STI); 1286 if (Result != MCDisassembler::Fail) { 1287 Size = 4; 1288 return Result; 1289 } 1290 } 1291 1292 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1293 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1294 // could form a valid instruction. The two bytes we rejected as an 1295 // instruction could have actually beeen an inline constant pool that is 1296 // unconditionally branched over. 1297 Size = 2; 1298 return MCDisassembler::Fail; 1299 } 1300 1301 // Attempt to read the instruction so that we can attempt to decode it. If 1302 // the buffer is not 4 bytes long, let the higher level logic figure out 1303 // what to do with a size of zero and MCDisassembler::Fail. 1304 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1305 if (Result == MCDisassembler::Fail) 1306 return MCDisassembler::Fail; 1307 1308 // The only instruction size for standard encoded MIPS. 1309 Size = 4; 1310 1311 if (hasCOP3()) { 1312 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1313 Result = 1314 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1315 if (Result != MCDisassembler::Fail) 1316 return Result; 1317 } 1318 1319 if (hasMips32r6() && isGP64()) { 1320 LLVM_DEBUG( 1321 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1322 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1323 Address, this, STI); 1324 if (Result != MCDisassembler::Fail) 1325 return Result; 1326 } 1327 1328 if (hasMips32r6() && isPTR64()) { 1329 LLVM_DEBUG( 1330 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1331 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1332 Address, this, STI); 1333 if (Result != MCDisassembler::Fail) 1334 return Result; 1335 } 1336 1337 if (hasMips32r6()) { 1338 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1339 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1340 Address, this, STI); 1341 if (Result != MCDisassembler::Fail) 1342 return Result; 1343 } 1344 1345 if (hasMips2() && isPTR64()) { 1346 LLVM_DEBUG( 1347 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1348 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1349 Address, this, STI); 1350 if (Result != MCDisassembler::Fail) 1351 return Result; 1352 } 1353 1354 if (hasCnMips()) { 1355 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1356 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1357 Address, this, STI); 1358 if (Result != MCDisassembler::Fail) 1359 return Result; 1360 } 1361 1362 if (hasCnMipsP()) { 1363 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); 1364 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, 1365 Address, this, STI); 1366 if (Result != MCDisassembler::Fail) 1367 return Result; 1368 } 1369 1370 if (isGP64()) { 1371 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1372 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1373 Address, this, STI); 1374 if (Result != MCDisassembler::Fail) 1375 return Result; 1376 } 1377 1378 if (isFP64()) { 1379 LLVM_DEBUG( 1380 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1381 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1382 Address, this, STI); 1383 if (Result != MCDisassembler::Fail) 1384 return Result; 1385 } 1386 1387 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1388 // Calling the auto-generated decoder function. 1389 Result = 1390 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1391 if (Result != MCDisassembler::Fail) 1392 return Result; 1393 1394 return MCDisassembler::Fail; 1395 } 1396 1397 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1398 unsigned RegNo, 1399 uint64_t Address, 1400 const void *Decoder) { 1401 return MCDisassembler::Fail; 1402 } 1403 1404 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1405 unsigned RegNo, 1406 uint64_t Address, 1407 const void *Decoder) { 1408 if (RegNo > 31) 1409 return MCDisassembler::Fail; 1410 1411 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1412 Inst.addOperand(MCOperand::createReg(Reg)); 1413 return MCDisassembler::Success; 1414 } 1415 1416 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1417 unsigned RegNo, 1418 uint64_t Address, 1419 const void *Decoder) { 1420 if (RegNo > 7) 1421 return MCDisassembler::Fail; 1422 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1423 Inst.addOperand(MCOperand::createReg(Reg)); 1424 return MCDisassembler::Success; 1425 } 1426 1427 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1428 unsigned RegNo, 1429 uint64_t Address, 1430 const void *Decoder) { 1431 if (RegNo > 7) 1432 return MCDisassembler::Fail; 1433 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1434 Inst.addOperand(MCOperand::createReg(Reg)); 1435 return MCDisassembler::Success; 1436 } 1437 1438 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1439 unsigned RegNo, 1440 uint64_t Address, 1441 const void *Decoder) { 1442 if (RegNo > 7) 1443 return MCDisassembler::Fail; 1444 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1445 Inst.addOperand(MCOperand::createReg(Reg)); 1446 return MCDisassembler::Success; 1447 } 1448 1449 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1450 unsigned RegNo, 1451 uint64_t Address, 1452 const void *Decoder) { 1453 if (RegNo > 31) 1454 return MCDisassembler::Fail; 1455 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1456 Inst.addOperand(MCOperand::createReg(Reg)); 1457 return MCDisassembler::Success; 1458 } 1459 1460 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1461 unsigned RegNo, 1462 uint64_t Address, 1463 const void *Decoder) { 1464 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1465 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1466 1467 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1468 } 1469 1470 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1471 unsigned RegNo, 1472 uint64_t Address, 1473 const void *Decoder) { 1474 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1475 } 1476 1477 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1478 unsigned RegNo, 1479 uint64_t Address, 1480 const void *Decoder) { 1481 if (RegNo > 31) 1482 return MCDisassembler::Fail; 1483 1484 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1485 Inst.addOperand(MCOperand::createReg(Reg)); 1486 return MCDisassembler::Success; 1487 } 1488 1489 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1490 unsigned RegNo, 1491 uint64_t Address, 1492 const void *Decoder) { 1493 if (RegNo > 31) 1494 return MCDisassembler::Fail; 1495 1496 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1497 Inst.addOperand(MCOperand::createReg(Reg)); 1498 return MCDisassembler::Success; 1499 } 1500 1501 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1502 unsigned RegNo, 1503 uint64_t Address, 1504 const void *Decoder) { 1505 if (RegNo > 31) 1506 return MCDisassembler::Fail; 1507 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1508 Inst.addOperand(MCOperand::createReg(Reg)); 1509 return MCDisassembler::Success; 1510 } 1511 1512 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1513 unsigned RegNo, 1514 uint64_t Address, 1515 const void *Decoder) { 1516 if (RegNo > 7) 1517 return MCDisassembler::Fail; 1518 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1519 Inst.addOperand(MCOperand::createReg(Reg)); 1520 return MCDisassembler::Success; 1521 } 1522 1523 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1524 uint64_t Address, 1525 const void *Decoder) { 1526 if (RegNo > 31) 1527 return MCDisassembler::Fail; 1528 1529 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1530 Inst.addOperand(MCOperand::createReg(Reg)); 1531 return MCDisassembler::Success; 1532 } 1533 1534 static DecodeStatus DecodeMem(MCInst &Inst, 1535 unsigned Insn, 1536 uint64_t Address, 1537 const void *Decoder) { 1538 int Offset = SignExtend32<16>(Insn & 0xffff); 1539 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1540 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1541 1542 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1543 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1544 1545 if (Inst.getOpcode() == Mips::SC || 1546 Inst.getOpcode() == Mips::SCD) 1547 Inst.addOperand(MCOperand::createReg(Reg)); 1548 1549 Inst.addOperand(MCOperand::createReg(Reg)); 1550 Inst.addOperand(MCOperand::createReg(Base)); 1551 Inst.addOperand(MCOperand::createImm(Offset)); 1552 1553 return MCDisassembler::Success; 1554 } 1555 1556 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1557 unsigned Insn, 1558 uint64_t Address, 1559 const void *Decoder) { 1560 int Offset = SignExtend32<9>(Insn >> 7); 1561 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1562 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1563 1564 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1565 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1566 1567 if (Inst.getOpcode() == Mips::SCE) 1568 Inst.addOperand(MCOperand::createReg(Reg)); 1569 1570 Inst.addOperand(MCOperand::createReg(Reg)); 1571 Inst.addOperand(MCOperand::createReg(Base)); 1572 Inst.addOperand(MCOperand::createImm(Offset)); 1573 1574 return MCDisassembler::Success; 1575 } 1576 1577 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1578 unsigned Insn, 1579 uint64_t Address, 1580 const void *Decoder) { 1581 int Offset = SignExtend32<16>(Insn & 0xffff); 1582 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1583 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1584 1585 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1586 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1587 1588 Inst.addOperand(MCOperand::createReg(Reg)); 1589 Inst.addOperand(MCOperand::createReg(Base)); 1590 Inst.addOperand(MCOperand::createImm(Offset)); 1591 1592 return MCDisassembler::Success; 1593 } 1594 1595 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1596 unsigned Insn, 1597 uint64_t Address, 1598 const void *Decoder) { 1599 int Offset = SignExtend32<16>(Insn & 0xffff); 1600 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1601 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1602 1603 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1604 1605 Inst.addOperand(MCOperand::createReg(Base)); 1606 Inst.addOperand(MCOperand::createImm(Offset)); 1607 Inst.addOperand(MCOperand::createImm(Hint)); 1608 1609 return MCDisassembler::Success; 1610 } 1611 1612 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1613 unsigned Insn, 1614 uint64_t Address, 1615 const void *Decoder) { 1616 int Offset = SignExtend32<12>(Insn & 0xfff); 1617 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1618 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1619 1620 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1621 1622 Inst.addOperand(MCOperand::createReg(Base)); 1623 Inst.addOperand(MCOperand::createImm(Offset)); 1624 Inst.addOperand(MCOperand::createImm(Hint)); 1625 1626 return MCDisassembler::Success; 1627 } 1628 1629 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1630 unsigned Insn, 1631 uint64_t Address, 1632 const void *Decoder) { 1633 int Offset = SignExtend32<9>(Insn & 0x1ff); 1634 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1635 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1636 1637 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1638 1639 Inst.addOperand(MCOperand::createReg(Base)); 1640 Inst.addOperand(MCOperand::createImm(Offset)); 1641 Inst.addOperand(MCOperand::createImm(Hint)); 1642 1643 return MCDisassembler::Success; 1644 } 1645 1646 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1647 unsigned Insn, 1648 uint64_t Address, 1649 const void *Decoder) { 1650 int Offset = SignExtend32<9>(Insn >> 7); 1651 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1652 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1653 1654 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1655 1656 Inst.addOperand(MCOperand::createReg(Base)); 1657 Inst.addOperand(MCOperand::createImm(Offset)); 1658 Inst.addOperand(MCOperand::createImm(Hint)); 1659 1660 return MCDisassembler::Success; 1661 } 1662 1663 static DecodeStatus DecodeSyncI(MCInst &Inst, 1664 unsigned Insn, 1665 uint64_t Address, 1666 const void *Decoder) { 1667 int Offset = SignExtend32<16>(Insn & 0xffff); 1668 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1669 1670 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1671 1672 Inst.addOperand(MCOperand::createReg(Base)); 1673 Inst.addOperand(MCOperand::createImm(Offset)); 1674 1675 return MCDisassembler::Success; 1676 } 1677 1678 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1679 uint64_t Address, const void *Decoder) { 1680 int Offset = SignExtend32<16>(Insn & 0xffff); 1681 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1682 1683 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1684 1685 Inst.addOperand(MCOperand::createReg(Base)); 1686 Inst.addOperand(MCOperand::createImm(Offset)); 1687 1688 return MCDisassembler::Success; 1689 } 1690 1691 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1692 unsigned Insn, 1693 uint64_t Address, 1694 const void *Decoder) { 1695 int Immediate = SignExtend32<16>(Insn & 0xffff); 1696 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1697 1698 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1699 1700 Inst.addOperand(MCOperand::createReg(Base)); 1701 Inst.addOperand(MCOperand::createImm(Immediate)); 1702 1703 return MCDisassembler::Success; 1704 } 1705 1706 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1707 uint64_t Address, const void *Decoder) { 1708 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1709 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1710 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1711 1712 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1713 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1714 1715 Inst.addOperand(MCOperand::createReg(Reg)); 1716 Inst.addOperand(MCOperand::createReg(Base)); 1717 1718 // The immediate field of an LD/ST instruction is scaled which means it must 1719 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1720 // data format. 1721 // .b - 1 byte 1722 // .h - 2 bytes 1723 // .w - 4 bytes 1724 // .d - 8 bytes 1725 switch(Inst.getOpcode()) 1726 { 1727 default: 1728 assert(false && "Unexpected instruction"); 1729 return MCDisassembler::Fail; 1730 break; 1731 case Mips::LD_B: 1732 case Mips::ST_B: 1733 Inst.addOperand(MCOperand::createImm(Offset)); 1734 break; 1735 case Mips::LD_H: 1736 case Mips::ST_H: 1737 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1738 break; 1739 case Mips::LD_W: 1740 case Mips::ST_W: 1741 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1742 break; 1743 case Mips::LD_D: 1744 case Mips::ST_D: 1745 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1746 break; 1747 } 1748 1749 return MCDisassembler::Success; 1750 } 1751 1752 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1753 unsigned Insn, 1754 uint64_t Address, 1755 const void *Decoder) { 1756 unsigned Offset = Insn & 0xf; 1757 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1758 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1759 1760 switch (Inst.getOpcode()) { 1761 case Mips::LBU16_MM: 1762 case Mips::LHU16_MM: 1763 case Mips::LW16_MM: 1764 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1765 == MCDisassembler::Fail) 1766 return MCDisassembler::Fail; 1767 break; 1768 case Mips::SB16_MM: 1769 case Mips::SB16_MMR6: 1770 case Mips::SH16_MM: 1771 case Mips::SH16_MMR6: 1772 case Mips::SW16_MM: 1773 case Mips::SW16_MMR6: 1774 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1775 == MCDisassembler::Fail) 1776 return MCDisassembler::Fail; 1777 break; 1778 } 1779 1780 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1781 == MCDisassembler::Fail) 1782 return MCDisassembler::Fail; 1783 1784 switch (Inst.getOpcode()) { 1785 case Mips::LBU16_MM: 1786 if (Offset == 0xf) 1787 Inst.addOperand(MCOperand::createImm(-1)); 1788 else 1789 Inst.addOperand(MCOperand::createImm(Offset)); 1790 break; 1791 case Mips::SB16_MM: 1792 case Mips::SB16_MMR6: 1793 Inst.addOperand(MCOperand::createImm(Offset)); 1794 break; 1795 case Mips::LHU16_MM: 1796 case Mips::SH16_MM: 1797 case Mips::SH16_MMR6: 1798 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1799 break; 1800 case Mips::LW16_MM: 1801 case Mips::SW16_MM: 1802 case Mips::SW16_MMR6: 1803 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1804 break; 1805 } 1806 1807 return MCDisassembler::Success; 1808 } 1809 1810 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1811 unsigned Insn, 1812 uint64_t Address, 1813 const void *Decoder) { 1814 unsigned Offset = Insn & 0x1F; 1815 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1816 1817 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1818 1819 Inst.addOperand(MCOperand::createReg(Reg)); 1820 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1821 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1822 1823 return MCDisassembler::Success; 1824 } 1825 1826 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1827 unsigned Insn, 1828 uint64_t Address, 1829 const void *Decoder) { 1830 unsigned Offset = Insn & 0x7F; 1831 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1832 1833 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1834 1835 Inst.addOperand(MCOperand::createReg(Reg)); 1836 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1837 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1838 1839 return MCDisassembler::Success; 1840 } 1841 1842 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1843 unsigned Insn, 1844 uint64_t Address, 1845 const void *Decoder) { 1846 int Offset; 1847 switch (Inst.getOpcode()) { 1848 case Mips::LWM16_MMR6: 1849 case Mips::SWM16_MMR6: 1850 Offset = fieldFromInstruction(Insn, 4, 4); 1851 break; 1852 default: 1853 Offset = SignExtend32<4>(Insn & 0xf); 1854 break; 1855 } 1856 1857 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1858 == MCDisassembler::Fail) 1859 return MCDisassembler::Fail; 1860 1861 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1862 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1863 1864 return MCDisassembler::Success; 1865 } 1866 1867 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1868 unsigned Insn, 1869 uint64_t Address, 1870 const void *Decoder) { 1871 int Offset = SignExtend32<9>(Insn & 0x1ff); 1872 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1873 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1874 1875 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1876 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1877 1878 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) 1879 Inst.addOperand(MCOperand::createReg(Reg)); 1880 1881 Inst.addOperand(MCOperand::createReg(Reg)); 1882 Inst.addOperand(MCOperand::createReg(Base)); 1883 Inst.addOperand(MCOperand::createImm(Offset)); 1884 1885 return MCDisassembler::Success; 1886 } 1887 1888 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1889 unsigned Insn, 1890 uint64_t Address, 1891 const void *Decoder) { 1892 int Offset = SignExtend32<12>(Insn & 0x0fff); 1893 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1894 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1895 1896 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1897 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1898 1899 switch (Inst.getOpcode()) { 1900 case Mips::SWM32_MM: 1901 case Mips::LWM32_MM: 1902 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1903 == MCDisassembler::Fail) 1904 return MCDisassembler::Fail; 1905 Inst.addOperand(MCOperand::createReg(Base)); 1906 Inst.addOperand(MCOperand::createImm(Offset)); 1907 break; 1908 case Mips::SC_MM: 1909 Inst.addOperand(MCOperand::createReg(Reg)); 1910 LLVM_FALLTHROUGH; 1911 default: 1912 Inst.addOperand(MCOperand::createReg(Reg)); 1913 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1914 Inst.addOperand(MCOperand::createReg(Reg+1)); 1915 1916 Inst.addOperand(MCOperand::createReg(Base)); 1917 Inst.addOperand(MCOperand::createImm(Offset)); 1918 } 1919 1920 return MCDisassembler::Success; 1921 } 1922 1923 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1924 unsigned Insn, 1925 uint64_t Address, 1926 const void *Decoder) { 1927 int Offset = SignExtend32<16>(Insn & 0xffff); 1928 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1929 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1930 1931 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1932 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1933 1934 Inst.addOperand(MCOperand::createReg(Reg)); 1935 Inst.addOperand(MCOperand::createReg(Base)); 1936 Inst.addOperand(MCOperand::createImm(Offset)); 1937 1938 return MCDisassembler::Success; 1939 } 1940 1941 static DecodeStatus DecodeFMem(MCInst &Inst, 1942 unsigned Insn, 1943 uint64_t Address, 1944 const void *Decoder) { 1945 int Offset = SignExtend32<16>(Insn & 0xffff); 1946 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1947 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1948 1949 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1950 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1951 1952 Inst.addOperand(MCOperand::createReg(Reg)); 1953 Inst.addOperand(MCOperand::createReg(Base)); 1954 Inst.addOperand(MCOperand::createImm(Offset)); 1955 1956 return MCDisassembler::Success; 1957 } 1958 1959 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1960 uint64_t Address, const void *Decoder) { 1961 // This function is the same as DecodeFMem but with the Reg and Base fields 1962 // swapped according to microMIPS spec. 1963 int Offset = SignExtend32<16>(Insn & 0xffff); 1964 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1965 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1966 1967 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1968 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1969 1970 Inst.addOperand(MCOperand::createReg(Reg)); 1971 Inst.addOperand(MCOperand::createReg(Base)); 1972 Inst.addOperand(MCOperand::createImm(Offset)); 1973 1974 return MCDisassembler::Success; 1975 } 1976 1977 static DecodeStatus DecodeFMem2(MCInst &Inst, 1978 unsigned Insn, 1979 uint64_t Address, 1980 const void *Decoder) { 1981 int Offset = SignExtend32<16>(Insn & 0xffff); 1982 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1983 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1984 1985 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1986 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1987 1988 Inst.addOperand(MCOperand::createReg(Reg)); 1989 Inst.addOperand(MCOperand::createReg(Base)); 1990 Inst.addOperand(MCOperand::createImm(Offset)); 1991 1992 return MCDisassembler::Success; 1993 } 1994 1995 static DecodeStatus DecodeFMem3(MCInst &Inst, 1996 unsigned Insn, 1997 uint64_t Address, 1998 const void *Decoder) { 1999 int Offset = SignExtend32<16>(Insn & 0xffff); 2000 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2001 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2002 2003 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 2004 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2005 2006 Inst.addOperand(MCOperand::createReg(Reg)); 2007 Inst.addOperand(MCOperand::createReg(Base)); 2008 Inst.addOperand(MCOperand::createImm(Offset)); 2009 2010 return MCDisassembler::Success; 2011 } 2012 2013 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2014 unsigned Insn, 2015 uint64_t Address, 2016 const void *Decoder) { 2017 int Offset = SignExtend32<11>(Insn & 0x07ff); 2018 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2019 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2020 2021 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2022 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2023 2024 Inst.addOperand(MCOperand::createReg(Reg)); 2025 Inst.addOperand(MCOperand::createReg(Base)); 2026 Inst.addOperand(MCOperand::createImm(Offset)); 2027 2028 return MCDisassembler::Success; 2029 } 2030 2031 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2032 uint64_t Address, const void *Decoder) { 2033 int Offset = SignExtend32<11>(Insn & 0x07ff); 2034 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2035 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2036 2037 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2038 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2039 2040 Inst.addOperand(MCOperand::createReg(Reg)); 2041 Inst.addOperand(MCOperand::createReg(Base)); 2042 Inst.addOperand(MCOperand::createImm(Offset)); 2043 2044 return MCDisassembler::Success; 2045 } 2046 2047 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2048 unsigned Insn, 2049 uint64_t Address, 2050 const void *Decoder) { 2051 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2052 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2053 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2054 2055 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2056 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2057 2058 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2059 Inst.addOperand(MCOperand::createReg(Rt)); 2060 } 2061 2062 Inst.addOperand(MCOperand::createReg(Rt)); 2063 Inst.addOperand(MCOperand::createReg(Base)); 2064 Inst.addOperand(MCOperand::createImm(Offset)); 2065 2066 return MCDisassembler::Success; 2067 } 2068 2069 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2070 unsigned RegNo, 2071 uint64_t Address, 2072 const void *Decoder) { 2073 // Currently only hardware register 29 is supported. 2074 if (RegNo != 29) 2075 return MCDisassembler::Fail; 2076 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2077 return MCDisassembler::Success; 2078 } 2079 2080 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2081 unsigned RegNo, 2082 uint64_t Address, 2083 const void *Decoder) { 2084 if (RegNo > 30 || RegNo %2) 2085 return MCDisassembler::Fail; 2086 2087 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2088 Inst.addOperand(MCOperand::createReg(Reg)); 2089 return MCDisassembler::Success; 2090 } 2091 2092 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2093 unsigned RegNo, 2094 uint64_t Address, 2095 const void *Decoder) { 2096 if (RegNo >= 4) 2097 return MCDisassembler::Fail; 2098 2099 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2100 Inst.addOperand(MCOperand::createReg(Reg)); 2101 return MCDisassembler::Success; 2102 } 2103 2104 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2105 unsigned RegNo, 2106 uint64_t Address, 2107 const void *Decoder) { 2108 if (RegNo >= 4) 2109 return MCDisassembler::Fail; 2110 2111 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2112 Inst.addOperand(MCOperand::createReg(Reg)); 2113 return MCDisassembler::Success; 2114 } 2115 2116 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2117 unsigned RegNo, 2118 uint64_t Address, 2119 const void *Decoder) { 2120 if (RegNo >= 4) 2121 return MCDisassembler::Fail; 2122 2123 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2124 Inst.addOperand(MCOperand::createReg(Reg)); 2125 return MCDisassembler::Success; 2126 } 2127 2128 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2129 unsigned RegNo, 2130 uint64_t Address, 2131 const void *Decoder) { 2132 if (RegNo > 31) 2133 return MCDisassembler::Fail; 2134 2135 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2136 Inst.addOperand(MCOperand::createReg(Reg)); 2137 return MCDisassembler::Success; 2138 } 2139 2140 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2141 unsigned RegNo, 2142 uint64_t Address, 2143 const void *Decoder) { 2144 if (RegNo > 31) 2145 return MCDisassembler::Fail; 2146 2147 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2148 Inst.addOperand(MCOperand::createReg(Reg)); 2149 return MCDisassembler::Success; 2150 } 2151 2152 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2153 unsigned RegNo, 2154 uint64_t Address, 2155 const void *Decoder) { 2156 if (RegNo > 31) 2157 return MCDisassembler::Fail; 2158 2159 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2160 Inst.addOperand(MCOperand::createReg(Reg)); 2161 return MCDisassembler::Success; 2162 } 2163 2164 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2165 unsigned RegNo, 2166 uint64_t Address, 2167 const void *Decoder) { 2168 if (RegNo > 31) 2169 return MCDisassembler::Fail; 2170 2171 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2172 Inst.addOperand(MCOperand::createReg(Reg)); 2173 return MCDisassembler::Success; 2174 } 2175 2176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2177 unsigned RegNo, 2178 uint64_t Address, 2179 const void *Decoder) { 2180 if (RegNo > 7) 2181 return MCDisassembler::Fail; 2182 2183 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2184 Inst.addOperand(MCOperand::createReg(Reg)); 2185 return MCDisassembler::Success; 2186 } 2187 2188 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2189 unsigned RegNo, 2190 uint64_t Address, 2191 const void *Decoder) { 2192 if (RegNo > 31) 2193 return MCDisassembler::Fail; 2194 2195 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2196 Inst.addOperand(MCOperand::createReg(Reg)); 2197 return MCDisassembler::Success; 2198 } 2199 2200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2201 unsigned RegNo, 2202 uint64_t Address, 2203 const void *Decoder) { 2204 if (RegNo > 31) 2205 return MCDisassembler::Fail; 2206 2207 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2208 Inst.addOperand(MCOperand::createReg(Reg)); 2209 return MCDisassembler::Success; 2210 } 2211 2212 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2213 unsigned Offset, 2214 uint64_t Address, 2215 const void *Decoder) { 2216 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2217 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2218 return MCDisassembler::Success; 2219 } 2220 2221 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2222 unsigned Offset, 2223 uint64_t Address, 2224 const void *Decoder) { 2225 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2226 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2227 return MCDisassembler::Success; 2228 } 2229 2230 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2231 unsigned Insn, 2232 uint64_t Address, 2233 const void *Decoder) { 2234 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2235 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2236 return MCDisassembler::Success; 2237 } 2238 2239 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2240 unsigned Offset, 2241 uint64_t Address, 2242 const void *Decoder) { 2243 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2244 2245 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2246 return MCDisassembler::Success; 2247 } 2248 2249 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2250 unsigned Offset, 2251 uint64_t Address, 2252 const void *Decoder) { 2253 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2254 2255 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2256 return MCDisassembler::Success; 2257 } 2258 2259 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2260 unsigned Offset, 2261 uint64_t Address, 2262 const void *Decoder) { 2263 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2264 2265 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2266 return MCDisassembler::Success; 2267 } 2268 2269 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2270 unsigned Offset, 2271 uint64_t Address, 2272 const void *Decoder) { 2273 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2274 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2275 return MCDisassembler::Success; 2276 } 2277 2278 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2279 unsigned Offset, 2280 uint64_t Address, 2281 const void *Decoder) { 2282 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2283 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2284 return MCDisassembler::Success; 2285 } 2286 2287 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2288 unsigned Offset, 2289 uint64_t Address, 2290 const void *Decoder) { 2291 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2292 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2293 return MCDisassembler::Success; 2294 } 2295 2296 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2297 unsigned Offset, 2298 uint64_t Address, 2299 const void *Decoder) { 2300 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2301 2302 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2303 return MCDisassembler::Success; 2304 } 2305 2306 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2307 unsigned Insn, 2308 uint64_t Address, 2309 const void *Decoder) { 2310 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2311 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2312 return MCDisassembler::Success; 2313 } 2314 2315 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 2316 unsigned Insn, 2317 uint64_t Address, 2318 const void *Decoder) { 2319 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2320 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2321 return MCDisassembler::Success; 2322 } 2323 2324 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2325 unsigned Value, 2326 uint64_t Address, 2327 const void *Decoder) { 2328 if (Value == 0) 2329 Inst.addOperand(MCOperand::createImm(1)); 2330 else if (Value == 0x7) 2331 Inst.addOperand(MCOperand::createImm(-1)); 2332 else 2333 Inst.addOperand(MCOperand::createImm(Value << 2)); 2334 return MCDisassembler::Success; 2335 } 2336 2337 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2338 unsigned Value, 2339 uint64_t Address, 2340 const void *Decoder) { 2341 if (Value == 0x7F) 2342 Inst.addOperand(MCOperand::createImm(-1)); 2343 else 2344 Inst.addOperand(MCOperand::createImm(Value)); 2345 return MCDisassembler::Success; 2346 } 2347 2348 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2349 unsigned Value, 2350 uint64_t Address, 2351 const void *Decoder) { 2352 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2353 return MCDisassembler::Success; 2354 } 2355 2356 template <unsigned Bits, int Offset, int Scale> 2357 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2358 uint64_t Address, 2359 const void *Decoder) { 2360 Value &= ((1 << Bits) - 1); 2361 Value *= Scale; 2362 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2363 return MCDisassembler::Success; 2364 } 2365 2366 template <unsigned Bits, int Offset, int ScaleBy> 2367 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2368 uint64_t Address, 2369 const void *Decoder) { 2370 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2371 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2372 return MCDisassembler::Success; 2373 } 2374 2375 static DecodeStatus DecodeInsSize(MCInst &Inst, 2376 unsigned Insn, 2377 uint64_t Address, 2378 const void *Decoder) { 2379 // First we need to grab the pos(lsb) from MCInst. 2380 // This function only handles the 32 bit variants of ins, as dins 2381 // variants are handled differently. 2382 int Pos = Inst.getOperand(2).getImm(); 2383 int Size = (int) Insn - Pos + 1; 2384 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2385 return MCDisassembler::Success; 2386 } 2387 2388 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2389 uint64_t Address, const void *Decoder) { 2390 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2391 return MCDisassembler::Success; 2392 } 2393 2394 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2395 uint64_t Address, const void *Decoder) { 2396 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2397 return MCDisassembler::Success; 2398 } 2399 2400 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2401 uint64_t Address, const void *Decoder) { 2402 int32_t DecodedValue; 2403 switch (Insn) { 2404 case 0: DecodedValue = 256; break; 2405 case 1: DecodedValue = 257; break; 2406 case 510: DecodedValue = -258; break; 2407 case 511: DecodedValue = -257; break; 2408 default: DecodedValue = SignExtend32<9>(Insn); break; 2409 } 2410 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2411 return MCDisassembler::Success; 2412 } 2413 2414 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2415 uint64_t Address, const void *Decoder) { 2416 // Insn must be >= 0, since it is unsigned that condition is always true. 2417 assert(Insn < 16); 2418 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2419 255, 32768, 65535}; 2420 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2421 return MCDisassembler::Success; 2422 } 2423 2424 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2425 unsigned Insn, 2426 uint64_t Address, 2427 const void *Decoder) { 2428 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2429 Mips::S6, Mips::S7, Mips::FP}; 2430 unsigned RegNum; 2431 2432 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2433 2434 // Empty register lists are not allowed. 2435 if (RegLst == 0) 2436 return MCDisassembler::Fail; 2437 2438 RegNum = RegLst & 0xf; 2439 2440 // RegLst values 10-15, and 26-31 are reserved. 2441 if (RegNum > 9) 2442 return MCDisassembler::Fail; 2443 2444 for (unsigned i = 0; i < RegNum; i++) 2445 Inst.addOperand(MCOperand::createReg(Regs[i])); 2446 2447 if (RegLst & 0x10) 2448 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2449 2450 return MCDisassembler::Success; 2451 } 2452 2453 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2454 uint64_t Address, 2455 const void *Decoder) { 2456 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2457 unsigned RegLst; 2458 switch(Inst.getOpcode()) { 2459 default: 2460 RegLst = fieldFromInstruction(Insn, 4, 2); 2461 break; 2462 case Mips::LWM16_MMR6: 2463 case Mips::SWM16_MMR6: 2464 RegLst = fieldFromInstruction(Insn, 8, 2); 2465 break; 2466 } 2467 unsigned RegNum = RegLst & 0x3; 2468 2469 for (unsigned i = 0; i <= RegNum; i++) 2470 Inst.addOperand(MCOperand::createReg(Regs[i])); 2471 2472 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2473 2474 return MCDisassembler::Success; 2475 } 2476 2477 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 2478 uint64_t Address, 2479 const void *Decoder) { 2480 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2481 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == 2482 MCDisassembler::Fail) 2483 return MCDisassembler::Fail; 2484 2485 unsigned RegRs; 2486 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) 2487 RegRs = fieldFromInstruction(Insn, 0, 2) | 2488 (fieldFromInstruction(Insn, 3, 1) << 2); 2489 else 2490 RegRs = fieldFromInstruction(Insn, 1, 3); 2491 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == 2492 MCDisassembler::Fail) 2493 return MCDisassembler::Fail; 2494 2495 unsigned RegRt = fieldFromInstruction(Insn, 4, 3); 2496 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == 2497 MCDisassembler::Fail) 2498 return MCDisassembler::Fail; 2499 2500 return MCDisassembler::Success; 2501 } 2502 2503 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2504 uint64_t Address, const void *Decoder) { 2505 switch (RegPair) { 2506 default: 2507 return MCDisassembler::Fail; 2508 case 0: 2509 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2510 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2511 break; 2512 case 1: 2513 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2514 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2515 break; 2516 case 2: 2517 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2518 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2519 break; 2520 case 3: 2521 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2522 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2523 break; 2524 case 4: 2525 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2526 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2527 break; 2528 case 5: 2529 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2530 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2531 break; 2532 case 6: 2533 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2534 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2535 break; 2536 case 7: 2537 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2538 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2539 break; 2540 } 2541 2542 return MCDisassembler::Success; 2543 } 2544 2545 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2546 uint64_t Address, const void *Decoder) { 2547 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2548 return MCDisassembler::Success; 2549 } 2550 2551 template <typename InsnType> 2552 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2553 uint64_t Address, 2554 const void *Decoder) { 2555 // We have: 2556 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2557 // Invalid if rt == 0 2558 // BGTZALC_MMR6 if rs == 0 && rt != 0 2559 // BLTZALC_MMR6 if rs != 0 && rs == rt 2560 // BLTUC_MMR6 if rs != 0 && rs != rt 2561 2562 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2563 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2564 InsnType Imm = 0; 2565 bool HasRs = false; 2566 bool HasRt = false; 2567 2568 if (Rt == 0) 2569 return MCDisassembler::Fail; 2570 else if (Rs == 0) { 2571 MI.setOpcode(Mips::BGTZALC_MMR6); 2572 HasRt = true; 2573 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2574 } 2575 else if (Rs == Rt) { 2576 MI.setOpcode(Mips::BLTZALC_MMR6); 2577 HasRs = true; 2578 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2579 } 2580 else { 2581 MI.setOpcode(Mips::BLTUC_MMR6); 2582 HasRs = true; 2583 HasRt = true; 2584 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2585 } 2586 2587 if (HasRs) 2588 MI.addOperand( 2589 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2590 2591 if (HasRt) 2592 MI.addOperand( 2593 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2594 2595 MI.addOperand(MCOperand::createImm(Imm)); 2596 2597 return MCDisassembler::Success; 2598 } 2599 2600 template <typename InsnType> 2601 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2602 uint64_t Address, 2603 const void *Decoder) { 2604 // We have: 2605 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2606 // Invalid if rt == 0 2607 // BLEZALC_MMR6 if rs == 0 && rt != 0 2608 // BGEZALC_MMR6 if rs == rt && rt != 0 2609 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2610 2611 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2612 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2613 InsnType Imm = 0; 2614 bool HasRs = false; 2615 2616 if (Rt == 0) 2617 return MCDisassembler::Fail; 2618 else if (Rs == 0) { 2619 MI.setOpcode(Mips::BLEZALC_MMR6); 2620 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2621 } 2622 else if (Rs == Rt) { 2623 MI.setOpcode(Mips::BGEZALC_MMR6); 2624 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2625 } 2626 else { 2627 HasRs = true; 2628 MI.setOpcode(Mips::BGEUC_MMR6); 2629 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2630 } 2631 2632 if (HasRs) 2633 MI.addOperand( 2634 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2635 MI.addOperand( 2636 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2637 2638 MI.addOperand(MCOperand::createImm(Imm)); 2639 2640 return MCDisassembler::Success; 2641 } 2642