1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 /// A disasembler class for Mips. 34 class MipsDisassemblerBase : public MCDisassembler { 35 public: 36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, 37 bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit), 40 IsBigEndian(IsBigEndian) {} 41 42 virtual ~MipsDisassemblerBase() {} 43 44 bool isGP64Bit() const { return IsGP64Bit; } 45 46 private: 47 bool IsGP64Bit; 48 protected: 49 bool IsBigEndian; 50 }; 51 52 /// A disasembler class for Mips32. 53 class MipsDisassembler : public MipsDisassemblerBase { 54 bool IsMicroMips; 55 public: 56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) 57 : MipsDisassemblerBase(STI, Ctx, bigEndian) { 58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 59 } 60 61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } 62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } 63 bool hasMips32r6() const { 64 return STI.getFeatureBits() & Mips::FeatureMips32r6; 65 } 66 67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } 68 69 bool hasCOP3() const { 70 // Only present in MIPS-I and MIPS-II 71 return !hasMips32() && !hasMips3(); 72 } 73 74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 75 ArrayRef<uint8_t> Bytes, uint64_t Address, 76 raw_ostream &VStream, 77 raw_ostream &CStream) const override; 78 }; 79 80 /// A disasembler class for Mips64. 81 class Mips64Disassembler : public MipsDisassemblerBase { 82 public: 83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 84 bool bigEndian) : 85 MipsDisassemblerBase(STI, Ctx, bigEndian) {} 86 87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 88 ArrayRef<uint8_t> Bytes, uint64_t Address, 89 raw_ostream &VStream, 90 raw_ostream &CStream) const override; 91 }; 92 93 } // end anonymous namespace 94 95 // Forward declare these because the autogenerated code will reference them. 96 // Definitions are further down. 97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 98 unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 123 unsigned Insn, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 128 unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 133 unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 157 unsigned Insn, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 192 unsigned RegNo, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 197 unsigned RegNo, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 202 unsigned RegNo, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 207 unsigned RegNo, 208 uint64_t Address, 209 const void *Decoder); 210 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 212 unsigned Offset, 213 uint64_t Address, 214 const void *Decoder); 215 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 217 unsigned Insn, 218 uint64_t Address, 219 const void *Decoder); 220 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 222 unsigned Offset, 223 uint64_t Address, 224 const void *Decoder); 225 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 227 unsigned Offset, 228 uint64_t Address, 229 const void *Decoder); 230 231 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 232 // shifted left by 1 bit. 233 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 234 unsigned Offset, 235 uint64_t Address, 236 const void *Decoder); 237 238 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 239 // shifted left by 1 bit. 240 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 241 unsigned Insn, 242 uint64_t Address, 243 const void *Decoder); 244 245 static DecodeStatus DecodeMem(MCInst &Inst, 246 unsigned Insn, 247 uint64_t Address, 248 const void *Decoder); 249 250 static DecodeStatus DecodeCacheOp(MCInst &Inst, 251 unsigned Insn, 252 uint64_t Address, 253 const void *Decoder); 254 255 static DecodeStatus DecodeSyncI(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 260 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 261 uint64_t Address, const void *Decoder); 262 263 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 264 unsigned Insn, 265 uint64_t Address, 266 const void *Decoder); 267 268 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 269 unsigned Insn, 270 uint64_t Address, 271 const void *Decoder); 272 273 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 274 unsigned Insn, 275 uint64_t Address, 276 const void *Decoder); 277 278 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 283 uint64_t Address, 284 const void *Decoder); 285 286 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 291 unsigned Insn, 292 uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 296 unsigned Value, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 301 unsigned Value, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 306 unsigned Value, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSimm4(MCInst &Inst, 311 unsigned Value, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeSimm16(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 // Decode the immediate field of an LSA instruction which 321 // is off by one. 322 static DecodeStatus DecodeLSAImm(MCInst &Inst, 323 unsigned Insn, 324 uint64_t Address, 325 const void *Decoder); 326 327 static DecodeStatus DecodeInsSize(MCInst &Inst, 328 unsigned Insn, 329 uint64_t Address, 330 const void *Decoder); 331 332 static DecodeStatus DecodeExtSize(MCInst &Inst, 333 unsigned Insn, 334 uint64_t Address, 335 const void *Decoder); 336 337 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 340 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 343 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 346 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void *Decoder); 348 349 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 352 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 353 /// handle. 354 template <typename InsnType> 355 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 356 const void *Decoder); 357 358 template <typename InsnType> 359 static DecodeStatus 360 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 361 const void *Decoder); 362 363 template <typename InsnType> 364 static DecodeStatus 365 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 366 const void *Decoder); 367 368 template <typename InsnType> 369 static DecodeStatus 370 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 371 const void *Decoder); 372 373 template <typename InsnType> 374 static DecodeStatus 375 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 376 const void *Decoder); 377 378 template <typename InsnType> 379 static DecodeStatus 380 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 381 const void *Decoder); 382 383 template <typename InsnType> 384 static DecodeStatus 385 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 386 const void *Decoder); 387 388 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 393 uint64_t Address, 394 const void *Decoder); 395 396 namespace llvm { 397 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 398 TheMips64elTarget; 399 } 400 401 static MCDisassembler *createMipsDisassembler( 402 const Target &T, 403 const MCSubtargetInfo &STI, 404 MCContext &Ctx) { 405 return new MipsDisassembler(STI, Ctx, true); 406 } 407 408 static MCDisassembler *createMipselDisassembler( 409 const Target &T, 410 const MCSubtargetInfo &STI, 411 MCContext &Ctx) { 412 return new MipsDisassembler(STI, Ctx, false); 413 } 414 415 static MCDisassembler *createMips64Disassembler( 416 const Target &T, 417 const MCSubtargetInfo &STI, 418 MCContext &Ctx) { 419 return new Mips64Disassembler(STI, Ctx, true); 420 } 421 422 static MCDisassembler *createMips64elDisassembler( 423 const Target &T, 424 const MCSubtargetInfo &STI, 425 MCContext &Ctx) { 426 return new Mips64Disassembler(STI, Ctx, false); 427 } 428 429 extern "C" void LLVMInitializeMipsDisassembler() { 430 // Register the disassembler. 431 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 432 createMipsDisassembler); 433 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 434 createMipselDisassembler); 435 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 436 createMips64Disassembler); 437 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 438 createMips64elDisassembler); 439 } 440 441 #include "MipsGenDisassemblerTables.inc" 442 443 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 444 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); 445 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 446 return *(RegInfo->getRegClass(RC).begin() + RegNo); 447 } 448 449 template <typename InsnType> 450 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 451 const void *Decoder) { 452 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 453 // The size of the n field depends on the element size 454 // The register class also depends on this. 455 InsnType tmp = fieldFromInstruction(insn, 17, 5); 456 unsigned NSize = 0; 457 DecodeFN RegDecoder = nullptr; 458 if ((tmp & 0x18) == 0x00) { // INSVE_B 459 NSize = 4; 460 RegDecoder = DecodeMSA128BRegisterClass; 461 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 462 NSize = 3; 463 RegDecoder = DecodeMSA128HRegisterClass; 464 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 465 NSize = 2; 466 RegDecoder = DecodeMSA128WRegisterClass; 467 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 468 NSize = 1; 469 RegDecoder = DecodeMSA128DRegisterClass; 470 } else 471 llvm_unreachable("Invalid encoding"); 472 473 assert(NSize != 0 && RegDecoder != nullptr); 474 475 // $wd 476 tmp = fieldFromInstruction(insn, 6, 5); 477 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 478 return MCDisassembler::Fail; 479 // $wd_in 480 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 481 return MCDisassembler::Fail; 482 // $n 483 tmp = fieldFromInstruction(insn, 16, NSize); 484 MI.addOperand(MCOperand::CreateImm(tmp)); 485 // $ws 486 tmp = fieldFromInstruction(insn, 11, 5); 487 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 488 return MCDisassembler::Fail; 489 // $n2 490 MI.addOperand(MCOperand::CreateImm(0)); 491 492 return MCDisassembler::Success; 493 } 494 495 template <typename InsnType> 496 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 497 uint64_t Address, 498 const void *Decoder) { 499 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 500 // (otherwise we would have matched the ADDI instruction from the earlier 501 // ISA's instead). 502 // 503 // We have: 504 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 505 // BOVC if rs >= rt 506 // BEQZALC if rs == 0 && rt != 0 507 // BEQC if rs < rt && rs != 0 508 509 InsnType Rs = fieldFromInstruction(insn, 21, 5); 510 InsnType Rt = fieldFromInstruction(insn, 16, 5); 511 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 512 bool HasRs = false; 513 514 if (Rs >= Rt) { 515 MI.setOpcode(Mips::BOVC); 516 HasRs = true; 517 } else if (Rs != 0 && Rs < Rt) { 518 MI.setOpcode(Mips::BEQC); 519 HasRs = true; 520 } else 521 MI.setOpcode(Mips::BEQZALC); 522 523 if (HasRs) 524 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 525 Rs))); 526 527 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 528 Rt))); 529 MI.addOperand(MCOperand::CreateImm(Imm)); 530 531 return MCDisassembler::Success; 532 } 533 534 template <typename InsnType> 535 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 536 uint64_t Address, 537 const void *Decoder) { 538 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 539 // (otherwise we would have matched the ADDI instruction from the earlier 540 // ISA's instead). 541 // 542 // We have: 543 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 544 // BNVC if rs >= rt 545 // BNEZALC if rs == 0 && rt != 0 546 // BNEC if rs < rt && rs != 0 547 548 InsnType Rs = fieldFromInstruction(insn, 21, 5); 549 InsnType Rt = fieldFromInstruction(insn, 16, 5); 550 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 551 bool HasRs = false; 552 553 if (Rs >= Rt) { 554 MI.setOpcode(Mips::BNVC); 555 HasRs = true; 556 } else if (Rs != 0 && Rs < Rt) { 557 MI.setOpcode(Mips::BNEC); 558 HasRs = true; 559 } else 560 MI.setOpcode(Mips::BNEZALC); 561 562 if (HasRs) 563 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 564 Rs))); 565 566 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 567 Rt))); 568 MI.addOperand(MCOperand::CreateImm(Imm)); 569 570 return MCDisassembler::Success; 571 } 572 573 template <typename InsnType> 574 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 575 uint64_t Address, 576 const void *Decoder) { 577 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 578 // (otherwise we would have matched the BLEZL instruction from the earlier 579 // ISA's instead). 580 // 581 // We have: 582 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 583 // Invalid if rs == 0 584 // BLEZC if rs == 0 && rt != 0 585 // BGEZC if rs == rt && rt != 0 586 // BGEC if rs != rt && rs != 0 && rt != 0 587 588 InsnType Rs = fieldFromInstruction(insn, 21, 5); 589 InsnType Rt = fieldFromInstruction(insn, 16, 5); 590 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 591 bool HasRs = false; 592 593 if (Rt == 0) 594 return MCDisassembler::Fail; 595 else if (Rs == 0) 596 MI.setOpcode(Mips::BLEZC); 597 else if (Rs == Rt) 598 MI.setOpcode(Mips::BGEZC); 599 else { 600 HasRs = true; 601 MI.setOpcode(Mips::BGEC); 602 } 603 604 if (HasRs) 605 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 606 Rs))); 607 608 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 609 Rt))); 610 611 MI.addOperand(MCOperand::CreateImm(Imm)); 612 613 return MCDisassembler::Success; 614 } 615 616 template <typename InsnType> 617 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 618 uint64_t Address, 619 const void *Decoder) { 620 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 621 // (otherwise we would have matched the BGTZL instruction from the earlier 622 // ISA's instead). 623 // 624 // We have: 625 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 626 // Invalid if rs == 0 627 // BGTZC if rs == 0 && rt != 0 628 // BLTZC if rs == rt && rt != 0 629 // BLTC if rs != rt && rs != 0 && rt != 0 630 631 bool HasRs = false; 632 633 InsnType Rs = fieldFromInstruction(insn, 21, 5); 634 InsnType Rt = fieldFromInstruction(insn, 16, 5); 635 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 636 637 if (Rt == 0) 638 return MCDisassembler::Fail; 639 else if (Rs == 0) 640 MI.setOpcode(Mips::BGTZC); 641 else if (Rs == Rt) 642 MI.setOpcode(Mips::BLTZC); 643 else { 644 MI.setOpcode(Mips::BLTC); 645 HasRs = true; 646 } 647 648 if (HasRs) 649 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 650 Rs))); 651 652 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 653 Rt))); 654 655 MI.addOperand(MCOperand::CreateImm(Imm)); 656 657 return MCDisassembler::Success; 658 } 659 660 template <typename InsnType> 661 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 662 uint64_t Address, 663 const void *Decoder) { 664 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 665 // (otherwise we would have matched the BGTZ instruction from the earlier 666 // ISA's instead). 667 // 668 // We have: 669 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 670 // BGTZ if rt == 0 671 // BGTZALC if rs == 0 && rt != 0 672 // BLTZALC if rs != 0 && rs == rt 673 // BLTUC if rs != 0 && rs != rt 674 675 InsnType Rs = fieldFromInstruction(insn, 21, 5); 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); 677 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 678 bool HasRs = false; 679 bool HasRt = false; 680 681 if (Rt == 0) { 682 MI.setOpcode(Mips::BGTZ); 683 HasRs = true; 684 } else if (Rs == 0) { 685 MI.setOpcode(Mips::BGTZALC); 686 HasRt = true; 687 } else if (Rs == Rt) { 688 MI.setOpcode(Mips::BLTZALC); 689 HasRs = true; 690 } else { 691 MI.setOpcode(Mips::BLTUC); 692 HasRs = true; 693 HasRt = true; 694 } 695 696 if (HasRs) 697 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 698 Rs))); 699 700 if (HasRt) 701 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 702 Rt))); 703 704 MI.addOperand(MCOperand::CreateImm(Imm)); 705 706 return MCDisassembler::Success; 707 } 708 709 template <typename InsnType> 710 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 711 uint64_t Address, 712 const void *Decoder) { 713 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 714 // (otherwise we would have matched the BLEZL instruction from the earlier 715 // ISA's instead). 716 // 717 // We have: 718 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 719 // Invalid if rs == 0 720 // BLEZALC if rs == 0 && rt != 0 721 // BGEZALC if rs == rt && rt != 0 722 // BGEUC if rs != rt && rs != 0 && rt != 0 723 724 InsnType Rs = fieldFromInstruction(insn, 21, 5); 725 InsnType Rt = fieldFromInstruction(insn, 16, 5); 726 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 727 bool HasRs = false; 728 729 if (Rt == 0) 730 return MCDisassembler::Fail; 731 else if (Rs == 0) 732 MI.setOpcode(Mips::BLEZALC); 733 else if (Rs == Rt) 734 MI.setOpcode(Mips::BGEZALC); 735 else { 736 HasRs = true; 737 MI.setOpcode(Mips::BGEUC); 738 } 739 740 if (HasRs) 741 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 742 Rs))); 743 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 744 Rt))); 745 746 MI.addOperand(MCOperand::CreateImm(Imm)); 747 748 return MCDisassembler::Success; 749 } 750 751 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 752 /// according to the given endianess. 753 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 754 uint64_t &Size, uint32_t &Insn, 755 bool IsBigEndian) { 756 // We want to read exactly 2 Bytes of data. 757 if (Bytes.size() < 2) { 758 Size = 0; 759 return MCDisassembler::Fail; 760 } 761 762 if (IsBigEndian) { 763 Insn = (Bytes[0] << 8) | Bytes[1]; 764 } else { 765 Insn = (Bytes[1] << 8) | Bytes[0]; 766 } 767 768 return MCDisassembler::Success; 769 } 770 771 /// Read four bytes from the ArrayRef and return 32 bit word sorted 772 /// according to the given endianess 773 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 774 uint64_t &Size, uint32_t &Insn, 775 bool IsBigEndian, bool IsMicroMips) { 776 // We want to read exactly 4 Bytes of data. 777 if (Bytes.size() < 4) { 778 Size = 0; 779 return MCDisassembler::Fail; 780 } 781 782 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 783 // always precede the low 16 bits in the instruction stream (that is, they 784 // are placed at lower addresses in the instruction stream). 785 // 786 // microMIPS byte ordering: 787 // Big-endian: 0 | 1 | 2 | 3 788 // Little-endian: 1 | 0 | 3 | 2 789 790 if (IsBigEndian) { 791 // Encoded as a big-endian 32-bit word in the stream. 792 Insn = 793 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 794 } else { 795 if (IsMicroMips) { 796 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 797 (Bytes[1] << 24); 798 } else { 799 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 800 (Bytes[3] << 24); 801 } 802 } 803 804 return MCDisassembler::Success; 805 } 806 807 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 808 ArrayRef<uint8_t> Bytes, 809 uint64_t Address, 810 raw_ostream &VStream, 811 raw_ostream &CStream) const { 812 uint32_t Insn; 813 DecodeStatus Result; 814 815 if (IsMicroMips) { 816 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 817 818 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 819 // Calling the auto-generated decoder function. 820 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 821 this, STI); 822 if (Result != MCDisassembler::Fail) { 823 Size = 2; 824 return Result; 825 } 826 827 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 828 if (Result == MCDisassembler::Fail) 829 return MCDisassembler::Fail; 830 831 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 832 // Calling the auto-generated decoder function. 833 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 834 this, STI); 835 if (Result != MCDisassembler::Fail) { 836 Size = 4; 837 return Result; 838 } 839 return MCDisassembler::Fail; 840 } 841 842 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 843 if (Result == MCDisassembler::Fail) 844 return MCDisassembler::Fail; 845 846 if (hasCOP3()) { 847 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 848 Result = 849 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 850 if (Result != MCDisassembler::Fail) { 851 Size = 4; 852 return Result; 853 } 854 } 855 856 if (hasMips32r6() && isGP64()) { 857 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 858 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 859 Address, this, STI); 860 if (Result != MCDisassembler::Fail) { 861 Size = 4; 862 return Result; 863 } 864 } 865 866 if (hasMips32r6()) { 867 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 868 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 869 Address, this, STI); 870 if (Result != MCDisassembler::Fail) { 871 Size = 4; 872 return Result; 873 } 874 } 875 876 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 877 // Calling the auto-generated decoder function. 878 Result = 879 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 880 if (Result != MCDisassembler::Fail) { 881 Size = 4; 882 return Result; 883 } 884 885 return MCDisassembler::Fail; 886 } 887 888 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size, 889 ArrayRef<uint8_t> Bytes, 890 uint64_t Address, 891 raw_ostream &VStream, 892 raw_ostream &CStream) const { 893 uint32_t Insn; 894 895 DecodeStatus Result = 896 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 897 if (Result == MCDisassembler::Fail) 898 return MCDisassembler::Fail; 899 900 // Calling the auto-generated decoder function. 901 Result = 902 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); 903 if (Result != MCDisassembler::Fail) { 904 Size = 4; 905 return Result; 906 } 907 // If we fail to decode in Mips64 decoder space we can try in Mips32 908 Result = 909 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 910 if (Result != MCDisassembler::Fail) { 911 Size = 4; 912 return Result; 913 } 914 915 return MCDisassembler::Fail; 916 } 917 918 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 919 unsigned RegNo, 920 uint64_t Address, 921 const void *Decoder) { 922 923 return MCDisassembler::Fail; 924 925 } 926 927 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 928 unsigned RegNo, 929 uint64_t Address, 930 const void *Decoder) { 931 932 if (RegNo > 31) 933 return MCDisassembler::Fail; 934 935 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 936 Inst.addOperand(MCOperand::CreateReg(Reg)); 937 return MCDisassembler::Success; 938 } 939 940 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 941 unsigned RegNo, 942 uint64_t Address, 943 const void *Decoder) { 944 if (RegNo > 7) 945 return MCDisassembler::Fail; 946 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 947 Inst.addOperand(MCOperand::CreateReg(Reg)); 948 return MCDisassembler::Success; 949 } 950 951 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 952 unsigned RegNo, 953 uint64_t Address, 954 const void *Decoder) { 955 if (RegNo > 7) 956 return MCDisassembler::Fail; 957 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 958 Inst.addOperand(MCOperand::CreateReg(Reg)); 959 return MCDisassembler::Success; 960 } 961 962 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 963 unsigned RegNo, 964 uint64_t Address, 965 const void *Decoder) { 966 if (RegNo > 31) 967 return MCDisassembler::Fail; 968 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 969 Inst.addOperand(MCOperand::CreateReg(Reg)); 970 return MCDisassembler::Success; 971 } 972 973 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 974 unsigned RegNo, 975 uint64_t Address, 976 const void *Decoder) { 977 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit()) 978 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 979 980 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 981 } 982 983 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 984 unsigned RegNo, 985 uint64_t Address, 986 const void *Decoder) { 987 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 988 } 989 990 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 991 unsigned RegNo, 992 uint64_t Address, 993 const void *Decoder) { 994 if (RegNo > 31) 995 return MCDisassembler::Fail; 996 997 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 998 Inst.addOperand(MCOperand::CreateReg(Reg)); 999 return MCDisassembler::Success; 1000 } 1001 1002 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1003 unsigned RegNo, 1004 uint64_t Address, 1005 const void *Decoder) { 1006 if (RegNo > 31) 1007 return MCDisassembler::Fail; 1008 1009 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1010 Inst.addOperand(MCOperand::CreateReg(Reg)); 1011 return MCDisassembler::Success; 1012 } 1013 1014 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1015 unsigned RegNo, 1016 uint64_t Address, 1017 const void *Decoder) { 1018 if (RegNo > 31) 1019 return MCDisassembler::Fail; 1020 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1021 Inst.addOperand(MCOperand::CreateReg(Reg)); 1022 return MCDisassembler::Success; 1023 } 1024 1025 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1026 unsigned RegNo, 1027 uint64_t Address, 1028 const void *Decoder) { 1029 if (RegNo > 7) 1030 return MCDisassembler::Fail; 1031 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1032 Inst.addOperand(MCOperand::CreateReg(Reg)); 1033 return MCDisassembler::Success; 1034 } 1035 1036 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1037 uint64_t Address, 1038 const void *Decoder) { 1039 if (RegNo > 31) 1040 return MCDisassembler::Fail; 1041 1042 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1043 Inst.addOperand(MCOperand::CreateReg(Reg)); 1044 return MCDisassembler::Success; 1045 } 1046 1047 static DecodeStatus DecodeMem(MCInst &Inst, 1048 unsigned Insn, 1049 uint64_t Address, 1050 const void *Decoder) { 1051 int Offset = SignExtend32<16>(Insn & 0xffff); 1052 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1053 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1054 1055 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1056 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1057 1058 if(Inst.getOpcode() == Mips::SC || 1059 Inst.getOpcode() == Mips::SCD){ 1060 Inst.addOperand(MCOperand::CreateReg(Reg)); 1061 } 1062 1063 Inst.addOperand(MCOperand::CreateReg(Reg)); 1064 Inst.addOperand(MCOperand::CreateReg(Base)); 1065 Inst.addOperand(MCOperand::CreateImm(Offset)); 1066 1067 return MCDisassembler::Success; 1068 } 1069 1070 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1071 unsigned Insn, 1072 uint64_t Address, 1073 const void *Decoder) { 1074 int Offset = SignExtend32<16>(Insn & 0xffff); 1075 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1076 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1077 1078 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1079 1080 Inst.addOperand(MCOperand::CreateReg(Base)); 1081 Inst.addOperand(MCOperand::CreateImm(Offset)); 1082 Inst.addOperand(MCOperand::CreateImm(Hint)); 1083 1084 return MCDisassembler::Success; 1085 } 1086 1087 static DecodeStatus DecodeSyncI(MCInst &Inst, 1088 unsigned Insn, 1089 uint64_t Address, 1090 const void *Decoder) { 1091 int Offset = SignExtend32<16>(Insn & 0xffff); 1092 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1093 1094 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1095 1096 Inst.addOperand(MCOperand::CreateReg(Base)); 1097 Inst.addOperand(MCOperand::CreateImm(Offset)); 1098 1099 return MCDisassembler::Success; 1100 } 1101 1102 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1103 uint64_t Address, const void *Decoder) { 1104 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1105 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1106 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1107 1108 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1109 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1110 1111 Inst.addOperand(MCOperand::CreateReg(Reg)); 1112 Inst.addOperand(MCOperand::CreateReg(Base)); 1113 1114 // The immediate field of an LD/ST instruction is scaled which means it must 1115 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1116 // data format. 1117 // .b - 1 byte 1118 // .h - 2 bytes 1119 // .w - 4 bytes 1120 // .d - 8 bytes 1121 switch(Inst.getOpcode()) 1122 { 1123 default: 1124 assert (0 && "Unexpected instruction"); 1125 return MCDisassembler::Fail; 1126 break; 1127 case Mips::LD_B: 1128 case Mips::ST_B: 1129 Inst.addOperand(MCOperand::CreateImm(Offset)); 1130 break; 1131 case Mips::LD_H: 1132 case Mips::ST_H: 1133 Inst.addOperand(MCOperand::CreateImm(Offset * 2)); 1134 break; 1135 case Mips::LD_W: 1136 case Mips::ST_W: 1137 Inst.addOperand(MCOperand::CreateImm(Offset * 4)); 1138 break; 1139 case Mips::LD_D: 1140 case Mips::ST_D: 1141 Inst.addOperand(MCOperand::CreateImm(Offset * 8)); 1142 break; 1143 } 1144 1145 return MCDisassembler::Success; 1146 } 1147 1148 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1149 unsigned Insn, 1150 uint64_t Address, 1151 const void *Decoder) { 1152 unsigned Offset = Insn & 0xf; 1153 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1154 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1155 1156 switch (Inst.getOpcode()) { 1157 case Mips::LBU16_MM: 1158 case Mips::LHU16_MM: 1159 case Mips::LW16_MM: 1160 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1161 == MCDisassembler::Fail) 1162 return MCDisassembler::Fail; 1163 break; 1164 case Mips::SB16_MM: 1165 case Mips::SH16_MM: 1166 case Mips::SW16_MM: 1167 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1168 == MCDisassembler::Fail) 1169 return MCDisassembler::Fail; 1170 break; 1171 } 1172 1173 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1174 == MCDisassembler::Fail) 1175 return MCDisassembler::Fail; 1176 1177 switch (Inst.getOpcode()) { 1178 case Mips::LBU16_MM: 1179 if (Offset == 0xf) 1180 Inst.addOperand(MCOperand::CreateImm(-1)); 1181 else 1182 Inst.addOperand(MCOperand::CreateImm(Offset)); 1183 break; 1184 case Mips::SB16_MM: 1185 Inst.addOperand(MCOperand::CreateImm(Offset)); 1186 break; 1187 case Mips::LHU16_MM: 1188 case Mips::SH16_MM: 1189 Inst.addOperand(MCOperand::CreateImm(Offset << 1)); 1190 break; 1191 case Mips::LW16_MM: 1192 case Mips::SW16_MM: 1193 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1194 break; 1195 } 1196 1197 return MCDisassembler::Success; 1198 } 1199 1200 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1201 unsigned Insn, 1202 uint64_t Address, 1203 const void *Decoder) { 1204 int Offset = SignExtend32<12>(Insn & 0x0fff); 1205 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1206 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1207 1208 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1209 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1210 1211 switch (Inst.getOpcode()) { 1212 case Mips::SWM32_MM: 1213 case Mips::LWM32_MM: 1214 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1215 == MCDisassembler::Fail) 1216 return MCDisassembler::Fail; 1217 Inst.addOperand(MCOperand::CreateReg(Base)); 1218 Inst.addOperand(MCOperand::CreateImm(Offset)); 1219 break; 1220 case Mips::SC_MM: 1221 Inst.addOperand(MCOperand::CreateReg(Reg)); 1222 // fallthrough 1223 default: 1224 Inst.addOperand(MCOperand::CreateReg(Reg)); 1225 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1226 Inst.addOperand(MCOperand::CreateReg(Reg+1)); 1227 1228 Inst.addOperand(MCOperand::CreateReg(Base)); 1229 Inst.addOperand(MCOperand::CreateImm(Offset)); 1230 } 1231 1232 return MCDisassembler::Success; 1233 } 1234 1235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1236 unsigned Insn, 1237 uint64_t Address, 1238 const void *Decoder) { 1239 int Offset = SignExtend32<16>(Insn & 0xffff); 1240 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1241 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1242 1243 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1244 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1245 1246 Inst.addOperand(MCOperand::CreateReg(Reg)); 1247 Inst.addOperand(MCOperand::CreateReg(Base)); 1248 Inst.addOperand(MCOperand::CreateImm(Offset)); 1249 1250 return MCDisassembler::Success; 1251 } 1252 1253 static DecodeStatus DecodeFMem(MCInst &Inst, 1254 unsigned Insn, 1255 uint64_t Address, 1256 const void *Decoder) { 1257 int Offset = SignExtend32<16>(Insn & 0xffff); 1258 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1259 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1260 1261 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1262 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1263 1264 Inst.addOperand(MCOperand::CreateReg(Reg)); 1265 Inst.addOperand(MCOperand::CreateReg(Base)); 1266 Inst.addOperand(MCOperand::CreateImm(Offset)); 1267 1268 return MCDisassembler::Success; 1269 } 1270 1271 static DecodeStatus DecodeFMem2(MCInst &Inst, 1272 unsigned Insn, 1273 uint64_t Address, 1274 const void *Decoder) { 1275 int Offset = SignExtend32<16>(Insn & 0xffff); 1276 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1277 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1278 1279 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1280 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1281 1282 Inst.addOperand(MCOperand::CreateReg(Reg)); 1283 Inst.addOperand(MCOperand::CreateReg(Base)); 1284 Inst.addOperand(MCOperand::CreateImm(Offset)); 1285 1286 return MCDisassembler::Success; 1287 } 1288 1289 static DecodeStatus DecodeFMem3(MCInst &Inst, 1290 unsigned Insn, 1291 uint64_t Address, 1292 const void *Decoder) { 1293 int Offset = SignExtend32<16>(Insn & 0xffff); 1294 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1295 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1296 1297 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1298 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1299 1300 Inst.addOperand(MCOperand::CreateReg(Reg)); 1301 Inst.addOperand(MCOperand::CreateReg(Base)); 1302 Inst.addOperand(MCOperand::CreateImm(Offset)); 1303 1304 return MCDisassembler::Success; 1305 } 1306 1307 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1308 unsigned Insn, 1309 uint64_t Address, 1310 const void *Decoder) { 1311 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1312 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1313 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1314 1315 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1316 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1317 1318 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1319 Inst.addOperand(MCOperand::CreateReg(Rt)); 1320 } 1321 1322 Inst.addOperand(MCOperand::CreateReg(Rt)); 1323 Inst.addOperand(MCOperand::CreateReg(Base)); 1324 Inst.addOperand(MCOperand::CreateImm(Offset)); 1325 1326 return MCDisassembler::Success; 1327 } 1328 1329 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1330 unsigned RegNo, 1331 uint64_t Address, 1332 const void *Decoder) { 1333 // Currently only hardware register 29 is supported. 1334 if (RegNo != 29) 1335 return MCDisassembler::Fail; 1336 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); 1337 return MCDisassembler::Success; 1338 } 1339 1340 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1341 unsigned RegNo, 1342 uint64_t Address, 1343 const void *Decoder) { 1344 if (RegNo > 30 || RegNo %2) 1345 return MCDisassembler::Fail; 1346 1347 ; 1348 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1349 Inst.addOperand(MCOperand::CreateReg(Reg)); 1350 return MCDisassembler::Success; 1351 } 1352 1353 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1354 unsigned RegNo, 1355 uint64_t Address, 1356 const void *Decoder) { 1357 if (RegNo >= 4) 1358 return MCDisassembler::Fail; 1359 1360 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1361 Inst.addOperand(MCOperand::CreateReg(Reg)); 1362 return MCDisassembler::Success; 1363 } 1364 1365 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1366 unsigned RegNo, 1367 uint64_t Address, 1368 const void *Decoder) { 1369 if (RegNo >= 4) 1370 return MCDisassembler::Fail; 1371 1372 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1373 Inst.addOperand(MCOperand::CreateReg(Reg)); 1374 return MCDisassembler::Success; 1375 } 1376 1377 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1378 unsigned RegNo, 1379 uint64_t Address, 1380 const void *Decoder) { 1381 if (RegNo >= 4) 1382 return MCDisassembler::Fail; 1383 1384 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1385 Inst.addOperand(MCOperand::CreateReg(Reg)); 1386 return MCDisassembler::Success; 1387 } 1388 1389 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1390 unsigned RegNo, 1391 uint64_t Address, 1392 const void *Decoder) { 1393 if (RegNo > 31) 1394 return MCDisassembler::Fail; 1395 1396 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1397 Inst.addOperand(MCOperand::CreateReg(Reg)); 1398 return MCDisassembler::Success; 1399 } 1400 1401 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1402 unsigned RegNo, 1403 uint64_t Address, 1404 const void *Decoder) { 1405 if (RegNo > 31) 1406 return MCDisassembler::Fail; 1407 1408 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1409 Inst.addOperand(MCOperand::CreateReg(Reg)); 1410 return MCDisassembler::Success; 1411 } 1412 1413 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1414 unsigned RegNo, 1415 uint64_t Address, 1416 const void *Decoder) { 1417 if (RegNo > 31) 1418 return MCDisassembler::Fail; 1419 1420 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1421 Inst.addOperand(MCOperand::CreateReg(Reg)); 1422 return MCDisassembler::Success; 1423 } 1424 1425 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1426 unsigned RegNo, 1427 uint64_t Address, 1428 const void *Decoder) { 1429 if (RegNo > 31) 1430 return MCDisassembler::Fail; 1431 1432 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1433 Inst.addOperand(MCOperand::CreateReg(Reg)); 1434 return MCDisassembler::Success; 1435 } 1436 1437 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1438 unsigned RegNo, 1439 uint64_t Address, 1440 const void *Decoder) { 1441 if (RegNo > 7) 1442 return MCDisassembler::Fail; 1443 1444 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1445 Inst.addOperand(MCOperand::CreateReg(Reg)); 1446 return MCDisassembler::Success; 1447 } 1448 1449 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1450 unsigned RegNo, 1451 uint64_t Address, 1452 const void *Decoder) { 1453 if (RegNo > 31) 1454 return MCDisassembler::Fail; 1455 1456 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1457 Inst.addOperand(MCOperand::CreateReg(Reg)); 1458 return MCDisassembler::Success; 1459 } 1460 1461 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1462 unsigned Offset, 1463 uint64_t Address, 1464 const void *Decoder) { 1465 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1466 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1467 return MCDisassembler::Success; 1468 } 1469 1470 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1471 unsigned Insn, 1472 uint64_t Address, 1473 const void *Decoder) { 1474 1475 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1476 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1477 return MCDisassembler::Success; 1478 } 1479 1480 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1481 unsigned Offset, 1482 uint64_t Address, 1483 const void *Decoder) { 1484 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1485 1486 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1487 return MCDisassembler::Success; 1488 } 1489 1490 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1491 unsigned Offset, 1492 uint64_t Address, 1493 const void *Decoder) { 1494 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1495 1496 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1497 return MCDisassembler::Success; 1498 } 1499 1500 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1501 unsigned Offset, 1502 uint64_t Address, 1503 const void *Decoder) { 1504 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1505 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1506 return MCDisassembler::Success; 1507 } 1508 1509 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1510 unsigned Insn, 1511 uint64_t Address, 1512 const void *Decoder) { 1513 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1514 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1515 return MCDisassembler::Success; 1516 } 1517 1518 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1519 unsigned Value, 1520 uint64_t Address, 1521 const void *Decoder) { 1522 if (Value == 0) 1523 Inst.addOperand(MCOperand::CreateImm(1)); 1524 else if (Value == 0x7) 1525 Inst.addOperand(MCOperand::CreateImm(-1)); 1526 else 1527 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1528 return MCDisassembler::Success; 1529 } 1530 1531 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1532 unsigned Value, 1533 uint64_t Address, 1534 const void *Decoder) { 1535 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1536 return MCDisassembler::Success; 1537 } 1538 1539 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1540 unsigned Value, 1541 uint64_t Address, 1542 const void *Decoder) { 1543 if (Value == 0x7F) 1544 Inst.addOperand(MCOperand::CreateImm(-1)); 1545 else 1546 Inst.addOperand(MCOperand::CreateImm(Value)); 1547 return MCDisassembler::Success; 1548 } 1549 1550 static DecodeStatus DecodeSimm4(MCInst &Inst, 1551 unsigned Value, 1552 uint64_t Address, 1553 const void *Decoder) { 1554 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value))); 1555 return MCDisassembler::Success; 1556 } 1557 1558 static DecodeStatus DecodeSimm16(MCInst &Inst, 1559 unsigned Insn, 1560 uint64_t Address, 1561 const void *Decoder) { 1562 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 1563 return MCDisassembler::Success; 1564 } 1565 1566 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1567 unsigned Insn, 1568 uint64_t Address, 1569 const void *Decoder) { 1570 // We add one to the immediate field as it was encoded as 'imm - 1'. 1571 Inst.addOperand(MCOperand::CreateImm(Insn + 1)); 1572 return MCDisassembler::Success; 1573 } 1574 1575 static DecodeStatus DecodeInsSize(MCInst &Inst, 1576 unsigned Insn, 1577 uint64_t Address, 1578 const void *Decoder) { 1579 // First we need to grab the pos(lsb) from MCInst. 1580 int Pos = Inst.getOperand(2).getImm(); 1581 int Size = (int) Insn - Pos + 1; 1582 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1583 return MCDisassembler::Success; 1584 } 1585 1586 static DecodeStatus DecodeExtSize(MCInst &Inst, 1587 unsigned Insn, 1588 uint64_t Address, 1589 const void *Decoder) { 1590 int Size = (int) Insn + 1; 1591 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1592 return MCDisassembler::Success; 1593 } 1594 1595 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1596 uint64_t Address, const void *Decoder) { 1597 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4)); 1598 return MCDisassembler::Success; 1599 } 1600 1601 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1602 uint64_t Address, const void *Decoder) { 1603 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8)); 1604 return MCDisassembler::Success; 1605 } 1606 1607 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1608 uint64_t Address, const void *Decoder) { 1609 int32_t DecodedValue; 1610 switch (Insn) { 1611 case 0: DecodedValue = 256; break; 1612 case 1: DecodedValue = 257; break; 1613 case 510: DecodedValue = -258; break; 1614 case 511: DecodedValue = -257; break; 1615 default: DecodedValue = SignExtend32<9>(Insn); break; 1616 } 1617 Inst.addOperand(MCOperand::CreateImm(DecodedValue << 2)); 1618 return MCDisassembler::Success; 1619 } 1620 1621 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1622 uint64_t Address, const void *Decoder) { 1623 // Insn must be >= 0, since it is unsigned that condition is always true. 1624 assert(Insn < 16); 1625 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1626 255, 32768, 65535}; 1627 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn])); 1628 return MCDisassembler::Success; 1629 } 1630 1631 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1632 uint64_t Address, const void *Decoder) { 1633 Inst.addOperand(MCOperand::CreateImm(Insn << 2)); 1634 return MCDisassembler::Success; 1635 } 1636 1637 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1638 unsigned Insn, 1639 uint64_t Address, 1640 const void *Decoder) { 1641 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1642 Mips::S6, Mips::FP}; 1643 unsigned RegNum; 1644 1645 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1646 // Empty register lists are not allowed. 1647 if (RegLst == 0) 1648 return MCDisassembler::Fail; 1649 1650 RegNum = RegLst & 0xf; 1651 for (unsigned i = 0; i < RegNum; i++) 1652 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1653 1654 if (RegLst & 0x10) 1655 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1656 1657 return MCDisassembler::Success; 1658 } 1659 1660 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 1661 uint64_t Address, 1662 const void *Decoder) { 1663 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 1664 unsigned RegNum; 1665 1666 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 1667 // Empty register lists are not allowed. 1668 if (RegLst == 0) 1669 return MCDisassembler::Fail; 1670 1671 RegNum = RegLst & 0x3; 1672 for (unsigned i = 0; i < RegNum - 1; i++) 1673 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1674 1675 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1676 1677 return MCDisassembler::Success; 1678 } 1679