1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 48 49 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 50 51 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 52 53 bool hasCOP3() const { 54 // Only present in MIPS-I and MIPS-II 55 return !hasMips32() && !hasMips3(); 56 } 57 58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 59 ArrayRef<uint8_t> Bytes, uint64_t Address, 60 raw_ostream &VStream, 61 raw_ostream &CStream) const override; 62 }; 63 64 } // end anonymous namespace 65 66 // Forward declare these because the autogenerated code will reference them. 67 // Definitions are further down. 68 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 69 unsigned RegNo, 70 uint64_t Address, 71 const void *Decoder); 72 73 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 74 unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 78 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 79 unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 83 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 99 unsigned Insn, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 114 unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 133 unsigned Insn, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 193 unsigned Offset, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 198 unsigned Offset, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 203 unsigned Insn, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 213 unsigned Offset, 214 uint64_t Address, 215 const void *Decoder); 216 217 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 218 unsigned Offset, 219 uint64_t Address, 220 const void *Decoder); 221 222 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 223 // shifted left by 1 bit. 224 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 225 unsigned Offset, 226 uint64_t Address, 227 const void *Decoder); 228 229 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 230 // shifted left by 1 bit. 231 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 232 unsigned Offset, 233 uint64_t Address, 234 const void *Decoder); 235 236 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 237 // shifted left by 1 bit. 238 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 239 unsigned Offset, 240 uint64_t Address, 241 const void *Decoder); 242 243 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 244 // shifted left by 1 bit. 245 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 246 unsigned Offset, 247 uint64_t Address, 248 const void *Decoder); 249 250 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 251 // shifted left by 1 bit. 252 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 253 unsigned Insn, 254 uint64_t Address, 255 const void *Decoder); 256 257 static DecodeStatus DecodeMem(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 262 static DecodeStatus DecodeMemEVA(MCInst &Inst, 263 unsigned Insn, 264 uint64_t Address, 265 const void *Decoder); 266 267 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeCacheOp(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeSyncI(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeSynciR6(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 315 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 321 unsigned Insn, 322 uint64_t Address, 323 const void *Decoder); 324 325 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 326 unsigned Insn, 327 uint64_t Address, 328 const void *Decoder); 329 330 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 331 unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 336 unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 341 unsigned Insn, 342 uint64_t Address, 343 const void *Decoder); 344 345 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 346 unsigned Insn, 347 uint64_t Address, 348 const void *Decoder); 349 350 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 351 uint64_t Address, 352 const void *Decoder); 353 354 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 359 uint64_t Address, 360 const void *Decoder); 361 362 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 363 uint64_t Address, 364 const void *Decoder); 365 366 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 367 unsigned Insn, 368 uint64_t Address, 369 const void *Decoder); 370 371 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 372 unsigned Value, 373 uint64_t Address, 374 const void *Decoder); 375 376 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 377 unsigned Value, 378 uint64_t Address, 379 const void *Decoder); 380 381 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 382 unsigned Value, 383 uint64_t Address, 384 const void *Decoder); 385 386 template <unsigned Bits, int Offset, int Scale> 387 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 388 uint64_t Address, 389 const void *Decoder); 390 391 template <unsigned Bits, int Offset> 392 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 393 uint64_t Address, 394 const void *Decoder) { 395 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 396 Decoder); 397 } 398 399 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 400 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 401 uint64_t Address, 402 const void *Decoder); 403 404 static DecodeStatus DecodeInsSize(MCInst &Inst, 405 unsigned Insn, 406 uint64_t Address, 407 const void *Decoder); 408 409 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 410 uint64_t Address, const void *Decoder); 411 412 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void *Decoder); 414 415 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 416 uint64_t Address, const void *Decoder); 417 418 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 419 uint64_t Address, const void *Decoder); 420 421 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void *Decoder); 423 424 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 425 /// handle. 426 template <typename InsnType> 427 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 428 const void *Decoder); 429 430 template <typename InsnType> 431 static DecodeStatus 432 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 433 const void *Decoder); 434 435 template <typename InsnType> 436 static DecodeStatus 437 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 438 const void *Decoder); 439 440 template <typename InsnType> 441 static DecodeStatus 442 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus 447 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus 452 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 453 const void *Decoder); 454 455 template <typename InsnType> 456 static DecodeStatus 457 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 458 const void *Decoder); 459 460 template <typename InsnType> 461 static DecodeStatus 462 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 463 const void *Decoder); 464 465 template <typename InsnType> 466 static DecodeStatus 467 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 468 const void *Decoder); 469 470 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 471 uint64_t Address, 472 const void *Decoder); 473 474 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 475 uint64_t Address, 476 const void *Decoder); 477 478 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 479 uint64_t Address, 480 const void *Decoder); 481 482 namespace llvm { 483 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 484 TheMips64elTarget; 485 } 486 487 static MCDisassembler *createMipsDisassembler( 488 const Target &T, 489 const MCSubtargetInfo &STI, 490 MCContext &Ctx) { 491 return new MipsDisassembler(STI, Ctx, true); 492 } 493 494 static MCDisassembler *createMipselDisassembler( 495 const Target &T, 496 const MCSubtargetInfo &STI, 497 MCContext &Ctx) { 498 return new MipsDisassembler(STI, Ctx, false); 499 } 500 501 extern "C" void LLVMInitializeMipsDisassembler() { 502 // Register the disassembler. 503 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 504 createMipsDisassembler); 505 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 506 createMipselDisassembler); 507 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 508 createMipsDisassembler); 509 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 510 createMipselDisassembler); 511 } 512 513 #include "MipsGenDisassemblerTables.inc" 514 515 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 516 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 517 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 518 return *(RegInfo->getRegClass(RC).begin() + RegNo); 519 } 520 521 template <typename InsnType> 522 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 523 const void *Decoder) { 524 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 525 // The size of the n field depends on the element size 526 // The register class also depends on this. 527 InsnType tmp = fieldFromInstruction(insn, 17, 5); 528 unsigned NSize = 0; 529 DecodeFN RegDecoder = nullptr; 530 if ((tmp & 0x18) == 0x00) { // INSVE_B 531 NSize = 4; 532 RegDecoder = DecodeMSA128BRegisterClass; 533 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 534 NSize = 3; 535 RegDecoder = DecodeMSA128HRegisterClass; 536 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 537 NSize = 2; 538 RegDecoder = DecodeMSA128WRegisterClass; 539 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 540 NSize = 1; 541 RegDecoder = DecodeMSA128DRegisterClass; 542 } else 543 llvm_unreachable("Invalid encoding"); 544 545 assert(NSize != 0 && RegDecoder != nullptr); 546 547 // $wd 548 tmp = fieldFromInstruction(insn, 6, 5); 549 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 550 return MCDisassembler::Fail; 551 // $wd_in 552 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 553 return MCDisassembler::Fail; 554 // $n 555 tmp = fieldFromInstruction(insn, 16, NSize); 556 MI.addOperand(MCOperand::createImm(tmp)); 557 // $ws 558 tmp = fieldFromInstruction(insn, 11, 5); 559 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 560 return MCDisassembler::Fail; 561 // $n2 562 MI.addOperand(MCOperand::createImm(0)); 563 564 return MCDisassembler::Success; 565 } 566 567 template <typename InsnType> 568 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 569 uint64_t Address, 570 const void *Decoder) { 571 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 572 // (otherwise we would have matched the ADDI instruction from the earlier 573 // ISA's instead). 574 // 575 // We have: 576 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 577 // BOVC if rs >= rt 578 // BEQZALC if rs == 0 && rt != 0 579 // BEQC if rs < rt && rs != 0 580 581 InsnType Rs = fieldFromInstruction(insn, 21, 5); 582 InsnType Rt = fieldFromInstruction(insn, 16, 5); 583 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 584 bool HasRs = false; 585 586 if (Rs >= Rt) { 587 MI.setOpcode(Mips::BOVC); 588 HasRs = true; 589 } else if (Rs != 0 && Rs < Rt) { 590 MI.setOpcode(Mips::BEQC); 591 HasRs = true; 592 } else 593 MI.setOpcode(Mips::BEQZALC); 594 595 if (HasRs) 596 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 597 Rs))); 598 599 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 600 Rt))); 601 MI.addOperand(MCOperand::createImm(Imm)); 602 603 return MCDisassembler::Success; 604 } 605 606 template <typename InsnType> 607 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 608 uint64_t Address, 609 const void *Decoder) { 610 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 611 // (otherwise we would have matched the ADDI instruction from the earlier 612 // ISA's instead). 613 // 614 // We have: 615 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 616 // BNVC if rs >= rt 617 // BNEZALC if rs == 0 && rt != 0 618 // BNEC if rs < rt && rs != 0 619 620 InsnType Rs = fieldFromInstruction(insn, 21, 5); 621 InsnType Rt = fieldFromInstruction(insn, 16, 5); 622 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 623 bool HasRs = false; 624 625 if (Rs >= Rt) { 626 MI.setOpcode(Mips::BNVC); 627 HasRs = true; 628 } else if (Rs != 0 && Rs < Rt) { 629 MI.setOpcode(Mips::BNEC); 630 HasRs = true; 631 } else 632 MI.setOpcode(Mips::BNEZALC); 633 634 if (HasRs) 635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 636 Rs))); 637 638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 639 Rt))); 640 MI.addOperand(MCOperand::createImm(Imm)); 641 642 return MCDisassembler::Success; 643 } 644 645 template <typename InsnType> 646 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 647 uint64_t Address, 648 const void *Decoder) { 649 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 650 // (otherwise we would have matched the BLEZL instruction from the earlier 651 // ISA's instead). 652 // 653 // We have: 654 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 655 // Invalid if rs == 0 656 // BLEZC if rs == 0 && rt != 0 657 // BGEZC if rs == rt && rt != 0 658 // BGEC if rs != rt && rs != 0 && rt != 0 659 660 InsnType Rs = fieldFromInstruction(insn, 21, 5); 661 InsnType Rt = fieldFromInstruction(insn, 16, 5); 662 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 663 bool HasRs = false; 664 665 if (Rt == 0) 666 return MCDisassembler::Fail; 667 else if (Rs == 0) 668 MI.setOpcode(Mips::BLEZC); 669 else if (Rs == Rt) 670 MI.setOpcode(Mips::BGEZC); 671 else { 672 HasRs = true; 673 MI.setOpcode(Mips::BGEC); 674 } 675 676 if (HasRs) 677 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 678 Rs))); 679 680 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 681 Rt))); 682 683 MI.addOperand(MCOperand::createImm(Imm)); 684 685 return MCDisassembler::Success; 686 } 687 688 template <typename InsnType> 689 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 690 uint64_t Address, 691 const void *Decoder) { 692 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 693 // (otherwise we would have matched the BGTZL instruction from the earlier 694 // ISA's instead). 695 // 696 // We have: 697 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 698 // Invalid if rs == 0 699 // BGTZC if rs == 0 && rt != 0 700 // BLTZC if rs == rt && rt != 0 701 // BLTC if rs != rt && rs != 0 && rt != 0 702 703 bool HasRs = false; 704 705 InsnType Rs = fieldFromInstruction(insn, 21, 5); 706 InsnType Rt = fieldFromInstruction(insn, 16, 5); 707 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 708 709 if (Rt == 0) 710 return MCDisassembler::Fail; 711 else if (Rs == 0) 712 MI.setOpcode(Mips::BGTZC); 713 else if (Rs == Rt) 714 MI.setOpcode(Mips::BLTZC); 715 else { 716 MI.setOpcode(Mips::BLTC); 717 HasRs = true; 718 } 719 720 if (HasRs) 721 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 722 Rs))); 723 724 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 725 Rt))); 726 727 MI.addOperand(MCOperand::createImm(Imm)); 728 729 return MCDisassembler::Success; 730 } 731 732 template <typename InsnType> 733 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 734 uint64_t Address, 735 const void *Decoder) { 736 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 737 // (otherwise we would have matched the BGTZ instruction from the earlier 738 // ISA's instead). 739 // 740 // We have: 741 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 742 // BGTZ if rt == 0 743 // BGTZALC if rs == 0 && rt != 0 744 // BLTZALC if rs != 0 && rs == rt 745 // BLTUC if rs != 0 && rs != rt 746 747 InsnType Rs = fieldFromInstruction(insn, 21, 5); 748 InsnType Rt = fieldFromInstruction(insn, 16, 5); 749 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 750 bool HasRs = false; 751 bool HasRt = false; 752 753 if (Rt == 0) { 754 MI.setOpcode(Mips::BGTZ); 755 HasRs = true; 756 } else if (Rs == 0) { 757 MI.setOpcode(Mips::BGTZALC); 758 HasRt = true; 759 } else if (Rs == Rt) { 760 MI.setOpcode(Mips::BLTZALC); 761 HasRs = true; 762 } else { 763 MI.setOpcode(Mips::BLTUC); 764 HasRs = true; 765 HasRt = true; 766 } 767 768 if (HasRs) 769 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 770 Rs))); 771 772 if (HasRt) 773 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 774 Rt))); 775 776 MI.addOperand(MCOperand::createImm(Imm)); 777 778 return MCDisassembler::Success; 779 } 780 781 template <typename InsnType> 782 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 783 uint64_t Address, 784 const void *Decoder) { 785 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 786 // (otherwise we would have matched the BLEZL instruction from the earlier 787 // ISA's instead). 788 // 789 // We have: 790 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 791 // Invalid if rs == 0 792 // BLEZALC if rs == 0 && rt != 0 793 // BGEZALC if rs == rt && rt != 0 794 // BGEUC if rs != rt && rs != 0 && rt != 0 795 796 InsnType Rs = fieldFromInstruction(insn, 21, 5); 797 InsnType Rt = fieldFromInstruction(insn, 16, 5); 798 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 799 bool HasRs = false; 800 801 if (Rt == 0) 802 return MCDisassembler::Fail; 803 else if (Rs == 0) 804 MI.setOpcode(Mips::BLEZALC); 805 else if (Rs == Rt) 806 MI.setOpcode(Mips::BGEZALC); 807 else { 808 HasRs = true; 809 MI.setOpcode(Mips::BGEUC); 810 } 811 812 if (HasRs) 813 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 814 Rs))); 815 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 816 Rt))); 817 818 MI.addOperand(MCOperand::createImm(Imm)); 819 820 return MCDisassembler::Success; 821 } 822 823 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 824 /// according to the given endianess. 825 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 826 uint64_t &Size, uint32_t &Insn, 827 bool IsBigEndian) { 828 // We want to read exactly 2 Bytes of data. 829 if (Bytes.size() < 2) { 830 Size = 0; 831 return MCDisassembler::Fail; 832 } 833 834 if (IsBigEndian) { 835 Insn = (Bytes[0] << 8) | Bytes[1]; 836 } else { 837 Insn = (Bytes[1] << 8) | Bytes[0]; 838 } 839 840 return MCDisassembler::Success; 841 } 842 843 /// Read four bytes from the ArrayRef and return 32 bit word sorted 844 /// according to the given endianess 845 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 846 uint64_t &Size, uint32_t &Insn, 847 bool IsBigEndian, bool IsMicroMips) { 848 // We want to read exactly 4 Bytes of data. 849 if (Bytes.size() < 4) { 850 Size = 0; 851 return MCDisassembler::Fail; 852 } 853 854 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 855 // always precede the low 16 bits in the instruction stream (that is, they 856 // are placed at lower addresses in the instruction stream). 857 // 858 // microMIPS byte ordering: 859 // Big-endian: 0 | 1 | 2 | 3 860 // Little-endian: 1 | 0 | 3 | 2 861 862 if (IsBigEndian) { 863 // Encoded as a big-endian 32-bit word in the stream. 864 Insn = 865 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 866 } else { 867 if (IsMicroMips) { 868 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 869 (Bytes[1] << 24); 870 } else { 871 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 872 (Bytes[3] << 24); 873 } 874 } 875 876 return MCDisassembler::Success; 877 } 878 879 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 880 ArrayRef<uint8_t> Bytes, 881 uint64_t Address, 882 raw_ostream &VStream, 883 raw_ostream &CStream) const { 884 uint32_t Insn; 885 DecodeStatus Result; 886 887 if (IsMicroMips) { 888 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 889 if (Result == MCDisassembler::Fail) 890 return MCDisassembler::Fail; 891 892 if (hasMips32r6()) { 893 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 894 // Calling the auto-generated decoder function for microMIPS32R6 895 // (and microMIPS64R6) 16-bit instructions. 896 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 897 Address, this, STI); 898 if (Result != MCDisassembler::Fail) { 899 Size = 2; 900 return Result; 901 } 902 } 903 904 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 905 // Calling the auto-generated decoder function for microMIPS 16-bit 906 // instructions. 907 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 908 this, STI); 909 if (Result != MCDisassembler::Fail) { 910 Size = 2; 911 return Result; 912 } 913 914 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 915 if (Result == MCDisassembler::Fail) 916 return MCDisassembler::Fail; 917 918 if (hasMips32r6()) { 919 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 920 // Calling the auto-generated decoder function. 921 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 922 this, STI); 923 if (Result != MCDisassembler::Fail) { 924 Size = 4; 925 return Result; 926 } 927 } 928 929 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 930 // Calling the auto-generated decoder function. 931 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 932 this, STI); 933 if (Result != MCDisassembler::Fail) { 934 Size = 4; 935 return Result; 936 } 937 938 if (hasMips32r6() && isFP64()) { 939 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 940 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 941 Address, this, STI); 942 if (Result != MCDisassembler::Fail) { 943 Size = 4; 944 return Result; 945 } 946 } 947 948 // This is an invalid instruction. Let the disassembler move forward by the 949 // minimum instruction size. 950 Size = 2; 951 return MCDisassembler::Fail; 952 } 953 954 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 955 if (Result == MCDisassembler::Fail) { 956 Size = 4; 957 return MCDisassembler::Fail; 958 } 959 960 if (hasCOP3()) { 961 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 962 Result = 963 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 964 if (Result != MCDisassembler::Fail) { 965 Size = 4; 966 return Result; 967 } 968 } 969 970 if (hasMips32r6() && isGP64()) { 971 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 972 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 973 Address, this, STI); 974 if (Result != MCDisassembler::Fail) { 975 Size = 4; 976 return Result; 977 } 978 } 979 980 if (hasMips32r6()) { 981 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 982 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 983 Address, this, STI); 984 if (Result != MCDisassembler::Fail) { 985 Size = 4; 986 return Result; 987 } 988 } 989 990 if (hasCnMips()) { 991 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 992 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 993 Address, this, STI); 994 if (Result != MCDisassembler::Fail) { 995 Size = 4; 996 return Result; 997 } 998 } 999 1000 if (isGP64()) { 1001 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1002 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1003 Address, this, STI); 1004 if (Result != MCDisassembler::Fail) { 1005 Size = 4; 1006 return Result; 1007 } 1008 } 1009 1010 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1011 // Calling the auto-generated decoder function. 1012 Result = 1013 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1014 if (Result != MCDisassembler::Fail) { 1015 Size = 4; 1016 return Result; 1017 } 1018 1019 Size = 4; 1020 return MCDisassembler::Fail; 1021 } 1022 1023 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1024 unsigned RegNo, 1025 uint64_t Address, 1026 const void *Decoder) { 1027 1028 return MCDisassembler::Fail; 1029 1030 } 1031 1032 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1033 unsigned RegNo, 1034 uint64_t Address, 1035 const void *Decoder) { 1036 1037 if (RegNo > 31) 1038 return MCDisassembler::Fail; 1039 1040 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1041 Inst.addOperand(MCOperand::createReg(Reg)); 1042 return MCDisassembler::Success; 1043 } 1044 1045 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1046 unsigned RegNo, 1047 uint64_t Address, 1048 const void *Decoder) { 1049 if (RegNo > 7) 1050 return MCDisassembler::Fail; 1051 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1052 Inst.addOperand(MCOperand::createReg(Reg)); 1053 return MCDisassembler::Success; 1054 } 1055 1056 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1057 unsigned RegNo, 1058 uint64_t Address, 1059 const void *Decoder) { 1060 if (RegNo > 7) 1061 return MCDisassembler::Fail; 1062 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1063 Inst.addOperand(MCOperand::createReg(Reg)); 1064 return MCDisassembler::Success; 1065 } 1066 1067 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1068 unsigned RegNo, 1069 uint64_t Address, 1070 const void *Decoder) { 1071 if (RegNo > 7) 1072 return MCDisassembler::Fail; 1073 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1074 Inst.addOperand(MCOperand::createReg(Reg)); 1075 return MCDisassembler::Success; 1076 } 1077 1078 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1079 unsigned RegNo, 1080 uint64_t Address, 1081 const void *Decoder) { 1082 if (RegNo > 31) 1083 return MCDisassembler::Fail; 1084 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1085 Inst.addOperand(MCOperand::createReg(Reg)); 1086 return MCDisassembler::Success; 1087 } 1088 1089 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1090 unsigned RegNo, 1091 uint64_t Address, 1092 const void *Decoder) { 1093 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1094 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1095 1096 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1097 } 1098 1099 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1100 unsigned RegNo, 1101 uint64_t Address, 1102 const void *Decoder) { 1103 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1104 } 1105 1106 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1107 unsigned RegNo, 1108 uint64_t Address, 1109 const void *Decoder) { 1110 if (RegNo > 31) 1111 return MCDisassembler::Fail; 1112 1113 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1114 Inst.addOperand(MCOperand::createReg(Reg)); 1115 return MCDisassembler::Success; 1116 } 1117 1118 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1119 unsigned RegNo, 1120 uint64_t Address, 1121 const void *Decoder) { 1122 if (RegNo > 31) 1123 return MCDisassembler::Fail; 1124 1125 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1126 Inst.addOperand(MCOperand::createReg(Reg)); 1127 return MCDisassembler::Success; 1128 } 1129 1130 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1131 unsigned RegNo, 1132 uint64_t Address, 1133 const void *Decoder) { 1134 if (RegNo > 31) 1135 return MCDisassembler::Fail; 1136 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1137 Inst.addOperand(MCOperand::createReg(Reg)); 1138 return MCDisassembler::Success; 1139 } 1140 1141 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1142 unsigned RegNo, 1143 uint64_t Address, 1144 const void *Decoder) { 1145 if (RegNo > 7) 1146 return MCDisassembler::Fail; 1147 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1148 Inst.addOperand(MCOperand::createReg(Reg)); 1149 return MCDisassembler::Success; 1150 } 1151 1152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1153 uint64_t Address, 1154 const void *Decoder) { 1155 if (RegNo > 31) 1156 return MCDisassembler::Fail; 1157 1158 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1159 Inst.addOperand(MCOperand::createReg(Reg)); 1160 return MCDisassembler::Success; 1161 } 1162 1163 static DecodeStatus DecodeMem(MCInst &Inst, 1164 unsigned Insn, 1165 uint64_t Address, 1166 const void *Decoder) { 1167 int Offset = SignExtend32<16>(Insn & 0xffff); 1168 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1169 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1170 1171 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1172 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1173 1174 if (Inst.getOpcode() == Mips::SC || 1175 Inst.getOpcode() == Mips::SCD) 1176 Inst.addOperand(MCOperand::createReg(Reg)); 1177 1178 Inst.addOperand(MCOperand::createReg(Reg)); 1179 Inst.addOperand(MCOperand::createReg(Base)); 1180 Inst.addOperand(MCOperand::createImm(Offset)); 1181 1182 return MCDisassembler::Success; 1183 } 1184 1185 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1186 unsigned Insn, 1187 uint64_t Address, 1188 const void *Decoder) { 1189 int Offset = SignExtend32<9>(Insn >> 7); 1190 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1191 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1192 1193 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1194 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1195 1196 if (Inst.getOpcode() == Mips::SCE) 1197 Inst.addOperand(MCOperand::createReg(Reg)); 1198 1199 Inst.addOperand(MCOperand::createReg(Reg)); 1200 Inst.addOperand(MCOperand::createReg(Base)); 1201 Inst.addOperand(MCOperand::createImm(Offset)); 1202 1203 return MCDisassembler::Success; 1204 } 1205 1206 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1207 unsigned Insn, 1208 uint64_t Address, 1209 const void *Decoder) { 1210 int Offset = SignExtend32<9>(Insn & 0x1ff); 1211 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1212 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1213 1214 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1215 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1216 1217 Inst.addOperand(MCOperand::createReg(Reg)); 1218 Inst.addOperand(MCOperand::createReg(Base)); 1219 Inst.addOperand(MCOperand::createImm(Offset)); 1220 1221 return MCDisassembler::Success; 1222 } 1223 1224 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1225 unsigned Insn, 1226 uint64_t Address, 1227 const void *Decoder) { 1228 int Offset = SignExtend32<16>(Insn & 0xffff); 1229 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1230 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1231 1232 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1233 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1234 1235 Inst.addOperand(MCOperand::createReg(Reg)); 1236 Inst.addOperand(MCOperand::createReg(Base)); 1237 Inst.addOperand(MCOperand::createImm(Offset)); 1238 1239 return MCDisassembler::Success; 1240 } 1241 1242 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1243 unsigned Insn, 1244 uint64_t Address, 1245 const void *Decoder) { 1246 int Offset = SignExtend32<16>(Insn & 0xffff); 1247 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1248 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1249 1250 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1251 1252 Inst.addOperand(MCOperand::createReg(Base)); 1253 Inst.addOperand(MCOperand::createImm(Offset)); 1254 Inst.addOperand(MCOperand::createImm(Hint)); 1255 1256 return MCDisassembler::Success; 1257 } 1258 1259 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1260 unsigned Insn, 1261 uint64_t Address, 1262 const void *Decoder) { 1263 int Offset = SignExtend32<12>(Insn & 0xfff); 1264 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1265 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1266 1267 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1268 1269 Inst.addOperand(MCOperand::createReg(Base)); 1270 Inst.addOperand(MCOperand::createImm(Offset)); 1271 Inst.addOperand(MCOperand::createImm(Hint)); 1272 1273 return MCDisassembler::Success; 1274 } 1275 1276 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1277 unsigned Insn, 1278 uint64_t Address, 1279 const void *Decoder) { 1280 int Offset = SignExtend32<9>(Insn & 0x1ff); 1281 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1282 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1283 1284 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1285 1286 Inst.addOperand(MCOperand::createReg(Base)); 1287 Inst.addOperand(MCOperand::createImm(Offset)); 1288 Inst.addOperand(MCOperand::createImm(Hint)); 1289 1290 return MCDisassembler::Success; 1291 } 1292 1293 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1294 unsigned Insn, 1295 uint64_t Address, 1296 const void *Decoder) { 1297 int Offset = SignExtend32<9>(Insn >> 7); 1298 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1299 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1300 1301 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1302 1303 Inst.addOperand(MCOperand::createReg(Base)); 1304 Inst.addOperand(MCOperand::createImm(Offset)); 1305 Inst.addOperand(MCOperand::createImm(Hint)); 1306 1307 return MCDisassembler::Success; 1308 } 1309 1310 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1311 unsigned Insn, 1312 uint64_t Address, 1313 const void *Decoder) { 1314 int Offset = SignExtend32<9>(Insn & 0x1ff); 1315 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1316 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1317 1318 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1319 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1320 1321 Inst.addOperand(MCOperand::createReg(Reg)); 1322 Inst.addOperand(MCOperand::createReg(Base)); 1323 Inst.addOperand(MCOperand::createImm(Offset)); 1324 1325 return MCDisassembler::Success; 1326 } 1327 1328 static DecodeStatus DecodeSyncI(MCInst &Inst, 1329 unsigned Insn, 1330 uint64_t Address, 1331 const void *Decoder) { 1332 int Offset = SignExtend32<16>(Insn & 0xffff); 1333 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1334 1335 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1336 1337 Inst.addOperand(MCOperand::createReg(Base)); 1338 Inst.addOperand(MCOperand::createImm(Offset)); 1339 1340 return MCDisassembler::Success; 1341 } 1342 1343 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1344 unsigned Insn, 1345 uint64_t Address, 1346 const void *Decoder) { 1347 int Immediate = SignExtend32<16>(Insn & 0xffff); 1348 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1349 1350 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1351 1352 Inst.addOperand(MCOperand::createReg(Base)); 1353 Inst.addOperand(MCOperand::createImm(Immediate)); 1354 1355 return MCDisassembler::Success; 1356 } 1357 1358 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1359 uint64_t Address, const void *Decoder) { 1360 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1361 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1362 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1363 1364 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1365 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1366 1367 Inst.addOperand(MCOperand::createReg(Reg)); 1368 Inst.addOperand(MCOperand::createReg(Base)); 1369 1370 // The immediate field of an LD/ST instruction is scaled which means it must 1371 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1372 // data format. 1373 // .b - 1 byte 1374 // .h - 2 bytes 1375 // .w - 4 bytes 1376 // .d - 8 bytes 1377 switch(Inst.getOpcode()) 1378 { 1379 default: 1380 assert (0 && "Unexpected instruction"); 1381 return MCDisassembler::Fail; 1382 break; 1383 case Mips::LD_B: 1384 case Mips::ST_B: 1385 Inst.addOperand(MCOperand::createImm(Offset)); 1386 break; 1387 case Mips::LD_H: 1388 case Mips::ST_H: 1389 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1390 break; 1391 case Mips::LD_W: 1392 case Mips::ST_W: 1393 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1394 break; 1395 case Mips::LD_D: 1396 case Mips::ST_D: 1397 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1398 break; 1399 } 1400 1401 return MCDisassembler::Success; 1402 } 1403 1404 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1405 unsigned Insn, 1406 uint64_t Address, 1407 const void *Decoder) { 1408 unsigned Offset = Insn & 0xf; 1409 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1410 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1411 1412 switch (Inst.getOpcode()) { 1413 case Mips::LBU16_MM: 1414 case Mips::LHU16_MM: 1415 case Mips::LW16_MM: 1416 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1417 == MCDisassembler::Fail) 1418 return MCDisassembler::Fail; 1419 break; 1420 case Mips::SB16_MM: 1421 case Mips::SB16_MMR6: 1422 case Mips::SH16_MM: 1423 case Mips::SH16_MMR6: 1424 case Mips::SW16_MM: 1425 case Mips::SW16_MMR6: 1426 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1427 == MCDisassembler::Fail) 1428 return MCDisassembler::Fail; 1429 break; 1430 } 1431 1432 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1433 == MCDisassembler::Fail) 1434 return MCDisassembler::Fail; 1435 1436 switch (Inst.getOpcode()) { 1437 case Mips::LBU16_MM: 1438 if (Offset == 0xf) 1439 Inst.addOperand(MCOperand::createImm(-1)); 1440 else 1441 Inst.addOperand(MCOperand::createImm(Offset)); 1442 break; 1443 case Mips::SB16_MM: 1444 case Mips::SB16_MMR6: 1445 Inst.addOperand(MCOperand::createImm(Offset)); 1446 break; 1447 case Mips::LHU16_MM: 1448 case Mips::SH16_MM: 1449 case Mips::SH16_MMR6: 1450 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1451 break; 1452 case Mips::LW16_MM: 1453 case Mips::SW16_MM: 1454 case Mips::SW16_MMR6: 1455 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1456 break; 1457 } 1458 1459 return MCDisassembler::Success; 1460 } 1461 1462 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1463 unsigned Insn, 1464 uint64_t Address, 1465 const void *Decoder) { 1466 unsigned Offset = Insn & 0x1F; 1467 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1468 1469 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1470 1471 Inst.addOperand(MCOperand::createReg(Reg)); 1472 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1473 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1474 1475 return MCDisassembler::Success; 1476 } 1477 1478 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1479 unsigned Insn, 1480 uint64_t Address, 1481 const void *Decoder) { 1482 unsigned Offset = Insn & 0x7F; 1483 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1484 1485 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1486 1487 Inst.addOperand(MCOperand::createReg(Reg)); 1488 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1489 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1490 1491 return MCDisassembler::Success; 1492 } 1493 1494 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1495 unsigned Insn, 1496 uint64_t Address, 1497 const void *Decoder) { 1498 int Offset; 1499 switch (Inst.getOpcode()) { 1500 case Mips::LWM16_MMR6: 1501 case Mips::SWM16_MMR6: 1502 Offset = fieldFromInstruction(Insn, 4, 4); 1503 break; 1504 default: 1505 Offset = SignExtend32<4>(Insn & 0xf); 1506 break; 1507 } 1508 1509 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1510 == MCDisassembler::Fail) 1511 return MCDisassembler::Fail; 1512 1513 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1514 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1515 1516 return MCDisassembler::Success; 1517 } 1518 1519 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1520 unsigned Insn, 1521 uint64_t Address, 1522 const void *Decoder) { 1523 int Offset = SignExtend32<9>(Insn & 0x1ff); 1524 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1525 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1526 1527 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1528 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1529 1530 if (Inst.getOpcode() == Mips::SCE_MM) 1531 Inst.addOperand(MCOperand::createReg(Reg)); 1532 1533 Inst.addOperand(MCOperand::createReg(Reg)); 1534 Inst.addOperand(MCOperand::createReg(Base)); 1535 Inst.addOperand(MCOperand::createImm(Offset)); 1536 1537 return MCDisassembler::Success; 1538 } 1539 1540 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1541 unsigned Insn, 1542 uint64_t Address, 1543 const void *Decoder) { 1544 int Offset = SignExtend32<12>(Insn & 0x0fff); 1545 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1546 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1547 1548 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1549 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1550 1551 switch (Inst.getOpcode()) { 1552 case Mips::SWM32_MM: 1553 case Mips::LWM32_MM: 1554 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1555 == MCDisassembler::Fail) 1556 return MCDisassembler::Fail; 1557 Inst.addOperand(MCOperand::createReg(Base)); 1558 Inst.addOperand(MCOperand::createImm(Offset)); 1559 break; 1560 case Mips::SC_MM: 1561 Inst.addOperand(MCOperand::createReg(Reg)); 1562 // fallthrough 1563 default: 1564 Inst.addOperand(MCOperand::createReg(Reg)); 1565 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1566 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1567 Inst.addOperand(MCOperand::createReg(Reg+1)); 1568 1569 Inst.addOperand(MCOperand::createReg(Base)); 1570 Inst.addOperand(MCOperand::createImm(Offset)); 1571 } 1572 1573 return MCDisassembler::Success; 1574 } 1575 1576 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1577 unsigned Insn, 1578 uint64_t Address, 1579 const void *Decoder) { 1580 int Offset = SignExtend32<16>(Insn & 0xffff); 1581 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1582 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1583 1584 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1585 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1586 1587 Inst.addOperand(MCOperand::createReg(Reg)); 1588 Inst.addOperand(MCOperand::createReg(Base)); 1589 Inst.addOperand(MCOperand::createImm(Offset)); 1590 1591 return MCDisassembler::Success; 1592 } 1593 1594 static DecodeStatus DecodeFMem(MCInst &Inst, 1595 unsigned Insn, 1596 uint64_t Address, 1597 const void *Decoder) { 1598 int Offset = SignExtend32<16>(Insn & 0xffff); 1599 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1600 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1601 1602 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1603 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1604 1605 Inst.addOperand(MCOperand::createReg(Reg)); 1606 Inst.addOperand(MCOperand::createReg(Base)); 1607 Inst.addOperand(MCOperand::createImm(Offset)); 1608 1609 return MCDisassembler::Success; 1610 } 1611 1612 static DecodeStatus DecodeFMem2(MCInst &Inst, 1613 unsigned Insn, 1614 uint64_t Address, 1615 const void *Decoder) { 1616 int Offset = SignExtend32<16>(Insn & 0xffff); 1617 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1618 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1619 1620 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1621 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1622 1623 Inst.addOperand(MCOperand::createReg(Reg)); 1624 Inst.addOperand(MCOperand::createReg(Base)); 1625 Inst.addOperand(MCOperand::createImm(Offset)); 1626 1627 return MCDisassembler::Success; 1628 } 1629 1630 static DecodeStatus DecodeFMem3(MCInst &Inst, 1631 unsigned Insn, 1632 uint64_t Address, 1633 const void *Decoder) { 1634 int Offset = SignExtend32<16>(Insn & 0xffff); 1635 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1636 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1637 1638 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1639 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1640 1641 Inst.addOperand(MCOperand::createReg(Reg)); 1642 Inst.addOperand(MCOperand::createReg(Base)); 1643 Inst.addOperand(MCOperand::createImm(Offset)); 1644 1645 return MCDisassembler::Success; 1646 } 1647 1648 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1649 unsigned Insn, 1650 uint64_t Address, 1651 const void *Decoder) { 1652 int Offset = SignExtend32<11>(Insn & 0x07ff); 1653 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1654 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1655 1656 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1657 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1658 1659 Inst.addOperand(MCOperand::createReg(Reg)); 1660 Inst.addOperand(MCOperand::createReg(Base)); 1661 Inst.addOperand(MCOperand::createImm(Offset)); 1662 1663 return MCDisassembler::Success; 1664 } 1665 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1666 unsigned Insn, 1667 uint64_t Address, 1668 const void *Decoder) { 1669 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1670 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1671 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1672 1673 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1674 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1675 1676 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1677 Inst.addOperand(MCOperand::createReg(Rt)); 1678 } 1679 1680 Inst.addOperand(MCOperand::createReg(Rt)); 1681 Inst.addOperand(MCOperand::createReg(Base)); 1682 Inst.addOperand(MCOperand::createImm(Offset)); 1683 1684 return MCDisassembler::Success; 1685 } 1686 1687 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1688 unsigned RegNo, 1689 uint64_t Address, 1690 const void *Decoder) { 1691 // Currently only hardware register 29 is supported. 1692 if (RegNo != 29) 1693 return MCDisassembler::Fail; 1694 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1695 return MCDisassembler::Success; 1696 } 1697 1698 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1699 unsigned RegNo, 1700 uint64_t Address, 1701 const void *Decoder) { 1702 if (RegNo > 30 || RegNo %2) 1703 return MCDisassembler::Fail; 1704 1705 ; 1706 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1707 Inst.addOperand(MCOperand::createReg(Reg)); 1708 return MCDisassembler::Success; 1709 } 1710 1711 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1712 unsigned RegNo, 1713 uint64_t Address, 1714 const void *Decoder) { 1715 if (RegNo >= 4) 1716 return MCDisassembler::Fail; 1717 1718 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1719 Inst.addOperand(MCOperand::createReg(Reg)); 1720 return MCDisassembler::Success; 1721 } 1722 1723 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1724 unsigned RegNo, 1725 uint64_t Address, 1726 const void *Decoder) { 1727 if (RegNo >= 4) 1728 return MCDisassembler::Fail; 1729 1730 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1731 Inst.addOperand(MCOperand::createReg(Reg)); 1732 return MCDisassembler::Success; 1733 } 1734 1735 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1736 unsigned RegNo, 1737 uint64_t Address, 1738 const void *Decoder) { 1739 if (RegNo >= 4) 1740 return MCDisassembler::Fail; 1741 1742 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1743 Inst.addOperand(MCOperand::createReg(Reg)); 1744 return MCDisassembler::Success; 1745 } 1746 1747 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1748 unsigned RegNo, 1749 uint64_t Address, 1750 const void *Decoder) { 1751 if (RegNo > 31) 1752 return MCDisassembler::Fail; 1753 1754 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1755 Inst.addOperand(MCOperand::createReg(Reg)); 1756 return MCDisassembler::Success; 1757 } 1758 1759 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1760 unsigned RegNo, 1761 uint64_t Address, 1762 const void *Decoder) { 1763 if (RegNo > 31) 1764 return MCDisassembler::Fail; 1765 1766 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1767 Inst.addOperand(MCOperand::createReg(Reg)); 1768 return MCDisassembler::Success; 1769 } 1770 1771 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1772 unsigned RegNo, 1773 uint64_t Address, 1774 const void *Decoder) { 1775 if (RegNo > 31) 1776 return MCDisassembler::Fail; 1777 1778 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1779 Inst.addOperand(MCOperand::createReg(Reg)); 1780 return MCDisassembler::Success; 1781 } 1782 1783 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1784 unsigned RegNo, 1785 uint64_t Address, 1786 const void *Decoder) { 1787 if (RegNo > 31) 1788 return MCDisassembler::Fail; 1789 1790 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1791 Inst.addOperand(MCOperand::createReg(Reg)); 1792 return MCDisassembler::Success; 1793 } 1794 1795 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1796 unsigned RegNo, 1797 uint64_t Address, 1798 const void *Decoder) { 1799 if (RegNo > 7) 1800 return MCDisassembler::Fail; 1801 1802 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1803 Inst.addOperand(MCOperand::createReg(Reg)); 1804 return MCDisassembler::Success; 1805 } 1806 1807 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1808 unsigned RegNo, 1809 uint64_t Address, 1810 const void *Decoder) { 1811 if (RegNo > 31) 1812 return MCDisassembler::Fail; 1813 1814 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1815 Inst.addOperand(MCOperand::createReg(Reg)); 1816 return MCDisassembler::Success; 1817 } 1818 1819 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1820 unsigned RegNo, 1821 uint64_t Address, 1822 const void *Decoder) { 1823 if (RegNo > 31) 1824 return MCDisassembler::Fail; 1825 1826 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1827 Inst.addOperand(MCOperand::createReg(Reg)); 1828 return MCDisassembler::Success; 1829 } 1830 1831 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1832 unsigned Offset, 1833 uint64_t Address, 1834 const void *Decoder) { 1835 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1836 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1837 return MCDisassembler::Success; 1838 } 1839 1840 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 1841 unsigned Offset, 1842 uint64_t Address, 1843 const void *Decoder) { 1844 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 1845 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1846 return MCDisassembler::Success; 1847 } 1848 1849 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1850 unsigned Insn, 1851 uint64_t Address, 1852 const void *Decoder) { 1853 1854 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1855 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1856 return MCDisassembler::Success; 1857 } 1858 1859 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1860 unsigned Offset, 1861 uint64_t Address, 1862 const void *Decoder) { 1863 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 1864 1865 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1866 return MCDisassembler::Success; 1867 } 1868 1869 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 1870 unsigned Offset, 1871 uint64_t Address, 1872 const void *Decoder) { 1873 int32_t BranchOffset = SignExtend32<21>(Offset) << 1; 1874 1875 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1876 return MCDisassembler::Success; 1877 } 1878 1879 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1880 unsigned Offset, 1881 uint64_t Address, 1882 const void *Decoder) { 1883 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 1884 1885 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1886 return MCDisassembler::Success; 1887 } 1888 1889 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1890 unsigned Offset, 1891 uint64_t Address, 1892 const void *Decoder) { 1893 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1894 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1895 return MCDisassembler::Success; 1896 } 1897 1898 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1899 unsigned Offset, 1900 uint64_t Address, 1901 const void *Decoder) { 1902 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1903 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1904 return MCDisassembler::Success; 1905 } 1906 1907 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1908 unsigned Offset, 1909 uint64_t Address, 1910 const void *Decoder) { 1911 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1912 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1913 return MCDisassembler::Success; 1914 } 1915 1916 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 1917 unsigned Offset, 1918 uint64_t Address, 1919 const void *Decoder) { 1920 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 1921 1922 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1923 return MCDisassembler::Success; 1924 } 1925 1926 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1927 unsigned Insn, 1928 uint64_t Address, 1929 const void *Decoder) { 1930 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1931 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1932 return MCDisassembler::Success; 1933 } 1934 1935 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1936 unsigned Value, 1937 uint64_t Address, 1938 const void *Decoder) { 1939 if (Value == 0) 1940 Inst.addOperand(MCOperand::createImm(1)); 1941 else if (Value == 0x7) 1942 Inst.addOperand(MCOperand::createImm(-1)); 1943 else 1944 Inst.addOperand(MCOperand::createImm(Value << 2)); 1945 return MCDisassembler::Success; 1946 } 1947 1948 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 1949 unsigned Value, 1950 uint64_t Address, 1951 const void *Decoder) { 1952 if (Value == 0x7F) 1953 Inst.addOperand(MCOperand::createImm(-1)); 1954 else 1955 Inst.addOperand(MCOperand::createImm(Value)); 1956 return MCDisassembler::Success; 1957 } 1958 1959 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1960 unsigned Value, 1961 uint64_t Address, 1962 const void *Decoder) { 1963 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1964 return MCDisassembler::Success; 1965 } 1966 1967 template <unsigned Bits, int Offset, int Scale> 1968 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1969 uint64_t Address, 1970 const void *Decoder) { 1971 Value &= ((1 << Bits) - 1); 1972 Value *= Scale; 1973 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1974 return MCDisassembler::Success; 1975 } 1976 1977 template <unsigned Bits, int Offset, int ScaleBy> 1978 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1979 uint64_t Address, 1980 const void *Decoder) { 1981 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 1982 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 1983 return MCDisassembler::Success; 1984 } 1985 1986 static DecodeStatus DecodeInsSize(MCInst &Inst, 1987 unsigned Insn, 1988 uint64_t Address, 1989 const void *Decoder) { 1990 // First we need to grab the pos(lsb) from MCInst. 1991 int Pos = Inst.getOperand(2).getImm(); 1992 int Size = (int) Insn - Pos + 1; 1993 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1994 return MCDisassembler::Success; 1995 } 1996 1997 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1998 uint64_t Address, const void *Decoder) { 1999 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2000 return MCDisassembler::Success; 2001 } 2002 2003 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2004 uint64_t Address, const void *Decoder) { 2005 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2006 return MCDisassembler::Success; 2007 } 2008 2009 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2010 uint64_t Address, const void *Decoder) { 2011 int32_t DecodedValue; 2012 switch (Insn) { 2013 case 0: DecodedValue = 256; break; 2014 case 1: DecodedValue = 257; break; 2015 case 510: DecodedValue = -258; break; 2016 case 511: DecodedValue = -257; break; 2017 default: DecodedValue = SignExtend32<9>(Insn); break; 2018 } 2019 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2020 return MCDisassembler::Success; 2021 } 2022 2023 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2024 uint64_t Address, const void *Decoder) { 2025 // Insn must be >= 0, since it is unsigned that condition is always true. 2026 assert(Insn < 16); 2027 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2028 255, 32768, 65535}; 2029 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2030 return MCDisassembler::Success; 2031 } 2032 2033 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2034 unsigned Insn, 2035 uint64_t Address, 2036 const void *Decoder) { 2037 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2038 Mips::S6, Mips::S7, Mips::FP}; 2039 unsigned RegNum; 2040 2041 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2042 2043 // Empty register lists are not allowed. 2044 if (RegLst == 0) 2045 return MCDisassembler::Fail; 2046 2047 RegNum = RegLst & 0xf; 2048 2049 // RegLst values 10-15, and 26-31 are reserved. 2050 if (RegNum > 9) 2051 return MCDisassembler::Fail; 2052 2053 for (unsigned i = 0; i < RegNum; i++) 2054 Inst.addOperand(MCOperand::createReg(Regs[i])); 2055 2056 if (RegLst & 0x10) 2057 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2058 2059 return MCDisassembler::Success; 2060 } 2061 2062 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2063 uint64_t Address, 2064 const void *Decoder) { 2065 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2066 unsigned RegLst; 2067 switch(Inst.getOpcode()) { 2068 default: 2069 RegLst = fieldFromInstruction(Insn, 4, 2); 2070 break; 2071 case Mips::LWM16_MMR6: 2072 case Mips::SWM16_MMR6: 2073 RegLst = fieldFromInstruction(Insn, 8, 2); 2074 break; 2075 } 2076 unsigned RegNum = RegLst & 0x3; 2077 2078 for (unsigned i = 0; i <= RegNum; i++) 2079 Inst.addOperand(MCOperand::createReg(Regs[i])); 2080 2081 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2082 2083 return MCDisassembler::Success; 2084 } 2085 2086 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2087 uint64_t Address, const void *Decoder) { 2088 2089 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2090 2091 switch (RegPair) { 2092 default: 2093 return MCDisassembler::Fail; 2094 case 0: 2095 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2096 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2097 break; 2098 case 1: 2099 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2100 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2101 break; 2102 case 2: 2103 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2104 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2105 break; 2106 case 3: 2107 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2108 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2109 break; 2110 case 4: 2111 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2112 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2113 break; 2114 case 5: 2115 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2116 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2117 break; 2118 case 6: 2119 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2120 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2121 break; 2122 case 7: 2123 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2124 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2125 break; 2126 } 2127 2128 return MCDisassembler::Success; 2129 } 2130 2131 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2132 uint64_t Address, const void *Decoder) { 2133 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2134 return MCDisassembler::Success; 2135 } 2136 2137 template <typename InsnType> 2138 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2139 uint64_t Address, 2140 const void *Decoder) { 2141 // We have: 2142 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2143 // Invalid if rt == 0 2144 // BGTZALC_MMR6 if rs == 0 && rt != 0 2145 // BLTZALC_MMR6 if rs != 0 && rs == rt 2146 // BLTUC_MMR6 if rs != 0 && rs != rt 2147 2148 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2149 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2150 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2151 bool HasRs = false; 2152 bool HasRt = false; 2153 2154 if (Rt == 0) 2155 return MCDisassembler::Fail; 2156 else if (Rs == 0) { 2157 MI.setOpcode(Mips::BGTZALC_MMR6); 2158 HasRt = true; 2159 } 2160 else if (Rs == Rt) { 2161 MI.setOpcode(Mips::BLTZALC_MMR6); 2162 HasRs = true; 2163 } 2164 else { 2165 MI.setOpcode(Mips::BLTUC_MMR6); 2166 HasRs = true; 2167 HasRt = true; 2168 } 2169 2170 if (HasRs) 2171 MI.addOperand( 2172 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2173 2174 if (HasRt) 2175 MI.addOperand( 2176 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2177 2178 MI.addOperand(MCOperand::createImm(Imm)); 2179 2180 return MCDisassembler::Success; 2181 } 2182 2183 template <typename InsnType> 2184 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2185 uint64_t Address, 2186 const void *Decoder) { 2187 // We have: 2188 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2189 // Invalid if rs == 0 2190 // BLEZALC_MMR6 if rs == 0 && rt != 0 2191 // BGEZALC_MMR6 if rs == rt && rt != 0 2192 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2193 2194 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2195 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2196 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2197 bool HasRs = false; 2198 2199 if (Rt == 0) 2200 return MCDisassembler::Fail; 2201 else if (Rs == 0) 2202 MI.setOpcode(Mips::BLEZALC_MMR6); 2203 else if (Rs == Rt) 2204 MI.setOpcode(Mips::BGEZALC_MMR6); 2205 else { 2206 HasRs = true; 2207 MI.setOpcode(Mips::BGEUC_MMR6); 2208 } 2209 2210 if (HasRs) 2211 MI.addOperand( 2212 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2213 MI.addOperand( 2214 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2215 2216 MI.addOperand(MCOperand::createImm(Imm)); 2217 2218 return MCDisassembler::Success; 2219 } 2220