1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Mips Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "Mips.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, 271 // which is shifted left by 2 bit. 272 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeMem(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeMemEVA(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 296 unsigned Insn, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 301 unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSyncI(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeSynciR6(MCInst &Inst, 321 unsigned Insn, 322 uint64_t Address, 323 const void *Decoder); 324 325 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 326 uint64_t Address, const void *Decoder); 327 328 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 334 unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 354 unsigned Insn, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 359 unsigned Insn, 360 uint64_t Address, 361 const void *Decoder); 362 363 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 364 uint64_t Address, 365 const void *Decoder); 366 367 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 368 uint64_t Address, 369 const void *Decoder); 370 371 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 372 const void *Decoder); 373 374 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 380 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 381 uint64_t Address, 382 const void *Decoder); 383 384 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 385 unsigned Insn, 386 uint64_t Address, 387 const void *Decoder); 388 389 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 390 unsigned Value, 391 uint64_t Address, 392 const void *Decoder); 393 394 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 395 unsigned Value, 396 uint64_t Address, 397 const void *Decoder); 398 399 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 400 unsigned Value, 401 uint64_t Address, 402 const void *Decoder); 403 404 template <unsigned Bits, int Offset, int Scale> 405 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 406 uint64_t Address, 407 const void *Decoder); 408 409 template <unsigned Bits, int Offset> 410 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 411 uint64_t Address, 412 const void *Decoder) { 413 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 414 Decoder); 415 } 416 417 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 418 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 419 uint64_t Address, 420 const void *Decoder); 421 422 static DecodeStatus DecodeInsSize(MCInst &Inst, 423 unsigned Insn, 424 uint64_t Address, 425 const void *Decoder); 426 427 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 428 uint64_t Address, const void *Decoder); 429 430 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 431 uint64_t Address, const void *Decoder); 432 433 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 434 uint64_t Address, const void *Decoder); 435 436 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 437 uint64_t Address, const void *Decoder); 438 439 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 440 uint64_t Address, const void *Decoder); 441 442 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 443 /// handle. 444 template <typename InsnType> 445 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 446 const void *Decoder); 447 448 template <typename InsnType> 449 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 450 const void *Decoder); 451 452 template <typename InsnType> 453 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 454 const void *Decoder); 455 456 template <typename InsnType> 457 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 458 const void *Decoder); 459 460 template <typename InsnType> 461 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 462 const void *Decoder); 463 464 template <typename InsnType> 465 static DecodeStatus 466 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 467 const void *Decoder); 468 469 template <typename InsnType> 470 static DecodeStatus 471 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 472 const void *Decoder); 473 474 template <typename InsnType> 475 static DecodeStatus 476 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 477 const void *Decoder); 478 479 template <typename InsnType> 480 static DecodeStatus 481 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 482 const void *Decoder); 483 484 template <typename InsnType> 485 static DecodeStatus 486 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 487 const void *Decoder); 488 489 template <typename InsnType> 490 static DecodeStatus 491 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 492 const void *Decoder); 493 494 template <typename InsnType> 495 static DecodeStatus 496 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 497 const void *Decoder); 498 499 template <typename InsnType> 500 static DecodeStatus 501 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 502 const void *Decoder); 503 504 template <typename InsnType> 505 static DecodeStatus 506 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 507 const void *Decoder); 508 509 template <typename InsnType> 510 static DecodeStatus 511 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 512 const void *Decoder); 513 514 template <typename InsnType> 515 static DecodeStatus 516 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 517 const void *Decoder); 518 519 template <typename InsnType> 520 static DecodeStatus 521 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 522 const void *Decoder); 523 524 template <typename InsnType> 525 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 526 const void *Decoder); 527 528 template <typename InsnType> 529 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 530 const void *Decoder); 531 532 template <typename InsnType> 533 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 534 const void *Decoder); 535 536 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 537 uint64_t Address, 538 const void *Decoder); 539 540 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 541 uint64_t Address, 542 const void *Decoder); 543 544 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 545 uint64_t Address, 546 const void *Decoder); 547 548 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 549 uint64_t Address, const void *Decoder); 550 551 static MCDisassembler *createMipsDisassembler( 552 const Target &T, 553 const MCSubtargetInfo &STI, 554 MCContext &Ctx) { 555 return new MipsDisassembler(STI, Ctx, true); 556 } 557 558 static MCDisassembler *createMipselDisassembler( 559 const Target &T, 560 const MCSubtargetInfo &STI, 561 MCContext &Ctx) { 562 return new MipsDisassembler(STI, Ctx, false); 563 } 564 565 extern "C" void LLVMInitializeMipsDisassembler() { 566 // Register the disassembler. 567 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 568 createMipsDisassembler); 569 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 570 createMipselDisassembler); 571 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 572 createMipsDisassembler); 573 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 574 createMipselDisassembler); 575 } 576 577 #include "MipsGenDisassemblerTables.inc" 578 579 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 580 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 581 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 582 return *(RegInfo->getRegClass(RC).begin() + RegNo); 583 } 584 585 template <typename InsnType> 586 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 587 const void *Decoder) { 588 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 589 590 // The size of the n field depends on the element size 591 // The register class also depends on this. 592 InsnType tmp = fieldFromInstruction(insn, 17, 5); 593 unsigned NSize = 0; 594 DecodeFN RegDecoder = nullptr; 595 if ((tmp & 0x18) == 0x00) { // INSVE_B 596 NSize = 4; 597 RegDecoder = DecodeMSA128BRegisterClass; 598 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 599 NSize = 3; 600 RegDecoder = DecodeMSA128HRegisterClass; 601 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 602 NSize = 2; 603 RegDecoder = DecodeMSA128WRegisterClass; 604 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 605 NSize = 1; 606 RegDecoder = DecodeMSA128DRegisterClass; 607 } else 608 llvm_unreachable("Invalid encoding"); 609 610 assert(NSize != 0 && RegDecoder != nullptr); 611 612 // $wd 613 tmp = fieldFromInstruction(insn, 6, 5); 614 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 615 return MCDisassembler::Fail; 616 // $wd_in 617 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 618 return MCDisassembler::Fail; 619 // $n 620 tmp = fieldFromInstruction(insn, 16, NSize); 621 MI.addOperand(MCOperand::createImm(tmp)); 622 // $ws 623 tmp = fieldFromInstruction(insn, 11, 5); 624 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 625 return MCDisassembler::Fail; 626 // $n2 627 MI.addOperand(MCOperand::createImm(0)); 628 629 return MCDisassembler::Success; 630 } 631 632 template <typename InsnType> 633 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 634 const void *Decoder) { 635 InsnType Rs = fieldFromInstruction(insn, 16, 5); 636 InsnType Imm = fieldFromInstruction(insn, 0, 16); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 638 Rs))); 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 640 Rs))); 641 MI.addOperand(MCOperand::createImm(Imm)); 642 643 return MCDisassembler::Success; 644 } 645 646 template <typename InsnType> 647 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 648 const void *Decoder) { 649 InsnType Rs = fieldFromInstruction(insn, 21, 5); 650 InsnType Imm = fieldFromInstruction(insn, 0, 16); 651 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 652 Rs))); 653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 654 Rs))); 655 MI.addOperand(MCOperand::createImm(Imm)); 656 657 return MCDisassembler::Success; 658 } 659 660 template <typename InsnType> 661 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 662 uint64_t Address, 663 const void *Decoder) { 664 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 665 // (otherwise we would have matched the ADDI instruction from the earlier 666 // ISA's instead). 667 // 668 // We have: 669 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 670 // BOVC if rs >= rt 671 // BEQZALC if rs == 0 && rt != 0 672 // BEQC if rs < rt && rs != 0 673 674 InsnType Rs = fieldFromInstruction(insn, 21, 5); 675 InsnType Rt = fieldFromInstruction(insn, 16, 5); 676 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 677 bool HasRs = false; 678 679 if (Rs >= Rt) { 680 MI.setOpcode(Mips::BOVC); 681 HasRs = true; 682 } else if (Rs != 0 && Rs < Rt) { 683 MI.setOpcode(Mips::BEQC); 684 HasRs = true; 685 } else 686 MI.setOpcode(Mips::BEQZALC); 687 688 if (HasRs) 689 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 690 Rs))); 691 692 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 693 Rt))); 694 MI.addOperand(MCOperand::createImm(Imm)); 695 696 return MCDisassembler::Success; 697 } 698 699 template <typename InsnType> 700 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 701 uint64_t Address, 702 const void *Decoder) { 703 InsnType Rt = fieldFromInstruction(insn, 21, 5); 704 InsnType Rs = fieldFromInstruction(insn, 16, 5); 705 int64_t Imm = 0; 706 707 if (Rs >= Rt) { 708 MI.setOpcode(Mips::BOVC_MMR6); 709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 710 Rt))); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rs))); 713 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 714 } else if (Rs != 0 && Rs < Rt) { 715 MI.setOpcode(Mips::BEQC_MMR6); 716 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 717 Rs))); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rt))); 720 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 721 } else { 722 MI.setOpcode(Mips::BEQZALC_MMR6); 723 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 724 Rt))); 725 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 726 } 727 728 MI.addOperand(MCOperand::createImm(Imm)); 729 730 return MCDisassembler::Success; 731 } 732 733 template <typename InsnType> 734 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 735 uint64_t Address, 736 const void *Decoder) { 737 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 738 // (otherwise we would have matched the ADDI instruction from the earlier 739 // ISA's instead). 740 // 741 // We have: 742 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 743 // BNVC if rs >= rt 744 // BNEZALC if rs == 0 && rt != 0 745 // BNEC if rs < rt && rs != 0 746 747 InsnType Rs = fieldFromInstruction(insn, 21, 5); 748 InsnType Rt = fieldFromInstruction(insn, 16, 5); 749 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 750 bool HasRs = false; 751 752 if (Rs >= Rt) { 753 MI.setOpcode(Mips::BNVC); 754 HasRs = true; 755 } else if (Rs != 0 && Rs < Rt) { 756 MI.setOpcode(Mips::BNEC); 757 HasRs = true; 758 } else 759 MI.setOpcode(Mips::BNEZALC); 760 761 if (HasRs) 762 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 763 Rs))); 764 765 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 766 Rt))); 767 MI.addOperand(MCOperand::createImm(Imm)); 768 769 return MCDisassembler::Success; 770 } 771 772 template <typename InsnType> 773 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 774 uint64_t Address, 775 const void *Decoder) { 776 InsnType Rt = fieldFromInstruction(insn, 21, 5); 777 InsnType Rs = fieldFromInstruction(insn, 16, 5); 778 int64_t Imm = 0; 779 780 if (Rs >= Rt) { 781 MI.setOpcode(Mips::BNVC_MMR6); 782 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 783 Rt))); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rs))); 786 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 787 } else if (Rs != 0 && Rs < Rt) { 788 MI.setOpcode(Mips::BNEC_MMR6); 789 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 790 Rs))); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rt))); 793 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 794 } else { 795 MI.setOpcode(Mips::BNEZALC_MMR6); 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rt))); 798 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 799 } 800 801 MI.addOperand(MCOperand::createImm(Imm)); 802 803 return MCDisassembler::Success; 804 } 805 806 template <typename InsnType> 807 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 808 uint64_t Address, 809 const void *Decoder) { 810 // We have: 811 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 812 // Invalid if rt == 0 813 // BGTZC_MMR6 if rs == 0 && rt != 0 814 // BLTZC_MMR6 if rs == rt && rt != 0 815 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 816 817 InsnType Rt = fieldFromInstruction(insn, 21, 5); 818 InsnType Rs = fieldFromInstruction(insn, 16, 5); 819 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 820 bool HasRs = false; 821 822 if (Rt == 0) 823 return MCDisassembler::Fail; 824 else if (Rs == 0) 825 MI.setOpcode(Mips::BGTZC_MMR6); 826 else if (Rs == Rt) 827 MI.setOpcode(Mips::BLTZC_MMR6); 828 else { 829 MI.setOpcode(Mips::BLTC_MMR6); 830 HasRs = true; 831 } 832 833 if (HasRs) 834 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 835 Rs))); 836 837 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 838 Rt))); 839 840 MI.addOperand(MCOperand::createImm(Imm)); 841 842 return MCDisassembler::Success; 843 } 844 845 template <typename InsnType> 846 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 847 uint64_t Address, 848 const void *Decoder) { 849 // We have: 850 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 851 // Invalid if rt == 0 852 // BLEZC_MMR6 if rs == 0 && rt != 0 853 // BGEZC_MMR6 if rs == rt && rt != 0 854 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 855 856 InsnType Rt = fieldFromInstruction(insn, 21, 5); 857 InsnType Rs = fieldFromInstruction(insn, 16, 5); 858 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 859 bool HasRs = false; 860 861 if (Rt == 0) 862 return MCDisassembler::Fail; 863 else if (Rs == 0) 864 MI.setOpcode(Mips::BLEZC_MMR6); 865 else if (Rs == Rt) 866 MI.setOpcode(Mips::BGEZC_MMR6); 867 else { 868 HasRs = true; 869 MI.setOpcode(Mips::BGEC_MMR6); 870 } 871 872 if (HasRs) 873 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 874 Rs))); 875 876 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 877 Rt))); 878 879 MI.addOperand(MCOperand::createImm(Imm)); 880 881 return MCDisassembler::Success; 882 } 883 884 template <typename InsnType> 885 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 886 uint64_t Address, 887 const void *Decoder) { 888 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 889 // (otherwise we would have matched the BLEZL instruction from the earlier 890 // ISA's instead). 891 // 892 // We have: 893 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 894 // Invalid if rs == 0 895 // BLEZC if rs == 0 && rt != 0 896 // BGEZC if rs == rt && rt != 0 897 // BGEC if rs != rt && rs != 0 && rt != 0 898 899 InsnType Rs = fieldFromInstruction(insn, 21, 5); 900 InsnType Rt = fieldFromInstruction(insn, 16, 5); 901 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 902 bool HasRs = false; 903 904 if (Rt == 0) 905 return MCDisassembler::Fail; 906 else if (Rs == 0) 907 MI.setOpcode(Mips::BLEZC); 908 else if (Rs == Rt) 909 MI.setOpcode(Mips::BGEZC); 910 else { 911 HasRs = true; 912 MI.setOpcode(Mips::BGEC); 913 } 914 915 if (HasRs) 916 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 917 Rs))); 918 919 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 920 Rt))); 921 922 MI.addOperand(MCOperand::createImm(Imm)); 923 924 return MCDisassembler::Success; 925 } 926 927 template <typename InsnType> 928 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 929 uint64_t Address, 930 const void *Decoder) { 931 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 932 // (otherwise we would have matched the BGTZL instruction from the earlier 933 // ISA's instead). 934 // 935 // We have: 936 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 937 // Invalid if rs == 0 938 // BGTZC if rs == 0 && rt != 0 939 // BLTZC if rs == rt && rt != 0 940 // BLTC if rs != rt && rs != 0 && rt != 0 941 942 bool HasRs = false; 943 944 InsnType Rs = fieldFromInstruction(insn, 21, 5); 945 InsnType Rt = fieldFromInstruction(insn, 16, 5); 946 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 947 948 if (Rt == 0) 949 return MCDisassembler::Fail; 950 else if (Rs == 0) 951 MI.setOpcode(Mips::BGTZC); 952 else if (Rs == Rt) 953 MI.setOpcode(Mips::BLTZC); 954 else { 955 MI.setOpcode(Mips::BLTC); 956 HasRs = true; 957 } 958 959 if (HasRs) 960 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 961 Rs))); 962 963 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 964 Rt))); 965 966 MI.addOperand(MCOperand::createImm(Imm)); 967 968 return MCDisassembler::Success; 969 } 970 971 template <typename InsnType> 972 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 973 uint64_t Address, 974 const void *Decoder) { 975 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 976 // (otherwise we would have matched the BGTZ instruction from the earlier 977 // ISA's instead). 978 // 979 // We have: 980 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 981 // BGTZ if rt == 0 982 // BGTZALC if rs == 0 && rt != 0 983 // BLTZALC if rs != 0 && rs == rt 984 // BLTUC if rs != 0 && rs != rt 985 986 InsnType Rs = fieldFromInstruction(insn, 21, 5); 987 InsnType Rt = fieldFromInstruction(insn, 16, 5); 988 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 989 bool HasRs = false; 990 bool HasRt = false; 991 992 if (Rt == 0) { 993 MI.setOpcode(Mips::BGTZ); 994 HasRs = true; 995 } else if (Rs == 0) { 996 MI.setOpcode(Mips::BGTZALC); 997 HasRt = true; 998 } else if (Rs == Rt) { 999 MI.setOpcode(Mips::BLTZALC); 1000 HasRs = true; 1001 } else { 1002 MI.setOpcode(Mips::BLTUC); 1003 HasRs = true; 1004 HasRt = true; 1005 } 1006 1007 if (HasRs) 1008 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1009 Rs))); 1010 1011 if (HasRt) 1012 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1013 Rt))); 1014 1015 MI.addOperand(MCOperand::createImm(Imm)); 1016 1017 return MCDisassembler::Success; 1018 } 1019 1020 template <typename InsnType> 1021 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1022 uint64_t Address, 1023 const void *Decoder) { 1024 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1025 // (otherwise we would have matched the BLEZL instruction from the earlier 1026 // ISA's instead). 1027 // 1028 // We have: 1029 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1030 // Invalid if rs == 0 1031 // BLEZALC if rs == 0 && rt != 0 1032 // BGEZALC if rs == rt && rt != 0 1033 // BGEUC if rs != rt && rs != 0 && rt != 0 1034 1035 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1036 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1037 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1038 bool HasRs = false; 1039 1040 if (Rt == 0) 1041 return MCDisassembler::Fail; 1042 else if (Rs == 0) 1043 MI.setOpcode(Mips::BLEZALC); 1044 else if (Rs == Rt) 1045 MI.setOpcode(Mips::BGEZALC); 1046 else { 1047 HasRs = true; 1048 MI.setOpcode(Mips::BGEUC); 1049 } 1050 1051 if (HasRs) 1052 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1053 Rs))); 1054 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1055 Rt))); 1056 1057 MI.addOperand(MCOperand::createImm(Imm)); 1058 1059 return MCDisassembler::Success; 1060 } 1061 1062 // Override the generated disassembler to produce DEXT all the time. This is 1063 // for feature / behaviour parity with binutils. 1064 template <typename InsnType> 1065 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1066 const void *Decoder) { 1067 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1068 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1069 unsigned Size = 0; 1070 unsigned Pos = 0; 1071 1072 switch (MI.getOpcode()) { 1073 case Mips::DEXT: 1074 Pos = Lsb; 1075 Size = Msbd + 1; 1076 break; 1077 case Mips::DEXTM: 1078 Pos = Lsb; 1079 Size = Msbd + 1 + 32; 1080 break; 1081 case Mips::DEXTU: 1082 Pos = Lsb + 32; 1083 Size = Msbd + 1; 1084 break; 1085 default: 1086 llvm_unreachable("Unknown DEXT instruction!"); 1087 } 1088 1089 MI.setOpcode(Mips::DEXT); 1090 1091 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1092 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1093 1094 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1095 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1096 MI.addOperand(MCOperand::createImm(Pos)); 1097 MI.addOperand(MCOperand::createImm(Size)); 1098 1099 return MCDisassembler::Success; 1100 } 1101 1102 // Override the generated disassembler to produce DINS all the time. This is 1103 // for feature / behaviour parity with binutils. 1104 template <typename InsnType> 1105 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1106 const void *Decoder) { 1107 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1108 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1109 unsigned Size = 0; 1110 unsigned Pos = 0; 1111 1112 switch (MI.getOpcode()) { 1113 case Mips::DINS: 1114 Pos = Lsb; 1115 Size = Msbd + 1 - Pos; 1116 break; 1117 case Mips::DINSM: 1118 Pos = Lsb; 1119 Size = Msbd + 33 - Pos; 1120 break; 1121 case Mips::DINSU: 1122 Pos = Lsb + 32; 1123 // mbsd = pos + size - 33 1124 // mbsd - pos + 33 = size 1125 Size = Msbd + 33 - Pos; 1126 break; 1127 default: 1128 llvm_unreachable("Unknown DINS instruction!"); 1129 } 1130 1131 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1132 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1133 1134 MI.setOpcode(Mips::DINS); 1135 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1136 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1137 MI.addOperand(MCOperand::createImm(Pos)); 1138 MI.addOperand(MCOperand::createImm(Size)); 1139 1140 return MCDisassembler::Success; 1141 } 1142 1143 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1144 template <typename InsnType> 1145 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1146 const void *Decoder) { 1147 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1148 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1149 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1150 Rt))); 1151 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1152 Rs))); 1153 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1154 Rt))); 1155 return MCDisassembler::Success; 1156 } 1157 1158 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1159 /// according to the given endianness. 1160 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1161 uint64_t &Size, uint32_t &Insn, 1162 bool IsBigEndian) { 1163 // We want to read exactly 2 Bytes of data. 1164 if (Bytes.size() < 2) { 1165 Size = 0; 1166 return MCDisassembler::Fail; 1167 } 1168 1169 if (IsBigEndian) { 1170 Insn = (Bytes[0] << 8) | Bytes[1]; 1171 } else { 1172 Insn = (Bytes[1] << 8) | Bytes[0]; 1173 } 1174 1175 return MCDisassembler::Success; 1176 } 1177 1178 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1179 /// according to the given endianness. 1180 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1181 uint64_t &Size, uint32_t &Insn, 1182 bool IsBigEndian, bool IsMicroMips) { 1183 // We want to read exactly 4 Bytes of data. 1184 if (Bytes.size() < 4) { 1185 Size = 0; 1186 return MCDisassembler::Fail; 1187 } 1188 1189 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1190 // always precede the low 16 bits in the instruction stream (that is, they 1191 // are placed at lower addresses in the instruction stream). 1192 // 1193 // microMIPS byte ordering: 1194 // Big-endian: 0 | 1 | 2 | 3 1195 // Little-endian: 1 | 0 | 3 | 2 1196 1197 if (IsBigEndian) { 1198 // Encoded as a big-endian 32-bit word in the stream. 1199 Insn = 1200 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1201 } else { 1202 if (IsMicroMips) { 1203 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1204 (Bytes[1] << 24); 1205 } else { 1206 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1207 (Bytes[3] << 24); 1208 } 1209 } 1210 1211 return MCDisassembler::Success; 1212 } 1213 1214 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1215 ArrayRef<uint8_t> Bytes, 1216 uint64_t Address, 1217 raw_ostream &VStream, 1218 raw_ostream &CStream) const { 1219 uint32_t Insn; 1220 DecodeStatus Result; 1221 Size = 0; 1222 1223 if (IsMicroMips) { 1224 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1225 if (Result == MCDisassembler::Fail) 1226 return MCDisassembler::Fail; 1227 1228 if (hasMips32r6()) { 1229 LLVM_DEBUG( 1230 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1231 // Calling the auto-generated decoder function for microMIPS32R6 1232 // 16-bit instructions. 1233 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1234 Address, this, STI); 1235 if (Result != MCDisassembler::Fail) { 1236 Size = 2; 1237 return Result; 1238 } 1239 } 1240 1241 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1242 // Calling the auto-generated decoder function for microMIPS 16-bit 1243 // instructions. 1244 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1245 this, STI); 1246 if (Result != MCDisassembler::Fail) { 1247 Size = 2; 1248 return Result; 1249 } 1250 1251 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1252 if (Result == MCDisassembler::Fail) 1253 return MCDisassembler::Fail; 1254 1255 if (hasMips32r6()) { 1256 LLVM_DEBUG( 1257 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1258 // Calling the auto-generated decoder function. 1259 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1260 this, STI); 1261 if (Result != MCDisassembler::Fail) { 1262 Size = 4; 1263 return Result; 1264 } 1265 } 1266 1267 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1268 // Calling the auto-generated decoder function. 1269 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1270 this, STI); 1271 if (Result != MCDisassembler::Fail) { 1272 Size = 4; 1273 return Result; 1274 } 1275 1276 if (isFP64()) { 1277 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1278 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1279 Address, this, STI); 1280 if (Result != MCDisassembler::Fail) { 1281 Size = 4; 1282 return Result; 1283 } 1284 } 1285 1286 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1287 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1288 // could form a valid instruction. The two bytes we rejected as an 1289 // instruction could have actually beeen an inline constant pool that is 1290 // unconditionally branched over. 1291 Size = 2; 1292 return MCDisassembler::Fail; 1293 } 1294 1295 // Attempt to read the instruction so that we can attempt to decode it. If 1296 // the buffer is not 4 bytes long, let the higher level logic figure out 1297 // what to do with a size of zero and MCDisassembler::Fail. 1298 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1299 if (Result == MCDisassembler::Fail) 1300 return MCDisassembler::Fail; 1301 1302 // The only instruction size for standard encoded MIPS. 1303 Size = 4; 1304 1305 if (hasCOP3()) { 1306 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1307 Result = 1308 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1309 if (Result != MCDisassembler::Fail) 1310 return Result; 1311 } 1312 1313 if (hasMips32r6() && isGP64()) { 1314 LLVM_DEBUG( 1315 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1316 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1317 Address, this, STI); 1318 if (Result != MCDisassembler::Fail) 1319 return Result; 1320 } 1321 1322 if (hasMips32r6() && isPTR64()) { 1323 LLVM_DEBUG( 1324 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1325 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1326 Address, this, STI); 1327 if (Result != MCDisassembler::Fail) 1328 return Result; 1329 } 1330 1331 if (hasMips32r6()) { 1332 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1333 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1334 Address, this, STI); 1335 if (Result != MCDisassembler::Fail) 1336 return Result; 1337 } 1338 1339 if (hasMips2() && isPTR64()) { 1340 LLVM_DEBUG( 1341 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1342 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1343 Address, this, STI); 1344 if (Result != MCDisassembler::Fail) 1345 return Result; 1346 } 1347 1348 if (hasCnMips()) { 1349 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1350 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1351 Address, this, STI); 1352 if (Result != MCDisassembler::Fail) 1353 return Result; 1354 } 1355 1356 if (isGP64()) { 1357 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1358 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1359 Address, this, STI); 1360 if (Result != MCDisassembler::Fail) 1361 return Result; 1362 } 1363 1364 if (isFP64()) { 1365 LLVM_DEBUG( 1366 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1367 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1368 Address, this, STI); 1369 if (Result != MCDisassembler::Fail) 1370 return Result; 1371 } 1372 1373 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1374 // Calling the auto-generated decoder function. 1375 Result = 1376 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1377 if (Result != MCDisassembler::Fail) 1378 return Result; 1379 1380 return MCDisassembler::Fail; 1381 } 1382 1383 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1384 unsigned RegNo, 1385 uint64_t Address, 1386 const void *Decoder) { 1387 return MCDisassembler::Fail; 1388 } 1389 1390 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1391 unsigned RegNo, 1392 uint64_t Address, 1393 const void *Decoder) { 1394 if (RegNo > 31) 1395 return MCDisassembler::Fail; 1396 1397 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1398 Inst.addOperand(MCOperand::createReg(Reg)); 1399 return MCDisassembler::Success; 1400 } 1401 1402 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1403 unsigned RegNo, 1404 uint64_t Address, 1405 const void *Decoder) { 1406 if (RegNo > 7) 1407 return MCDisassembler::Fail; 1408 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1409 Inst.addOperand(MCOperand::createReg(Reg)); 1410 return MCDisassembler::Success; 1411 } 1412 1413 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1414 unsigned RegNo, 1415 uint64_t Address, 1416 const void *Decoder) { 1417 if (RegNo > 7) 1418 return MCDisassembler::Fail; 1419 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1420 Inst.addOperand(MCOperand::createReg(Reg)); 1421 return MCDisassembler::Success; 1422 } 1423 1424 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1425 unsigned RegNo, 1426 uint64_t Address, 1427 const void *Decoder) { 1428 if (RegNo > 7) 1429 return MCDisassembler::Fail; 1430 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1431 Inst.addOperand(MCOperand::createReg(Reg)); 1432 return MCDisassembler::Success; 1433 } 1434 1435 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1436 unsigned RegNo, 1437 uint64_t Address, 1438 const void *Decoder) { 1439 if (RegNo > 31) 1440 return MCDisassembler::Fail; 1441 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1442 Inst.addOperand(MCOperand::createReg(Reg)); 1443 return MCDisassembler::Success; 1444 } 1445 1446 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1447 unsigned RegNo, 1448 uint64_t Address, 1449 const void *Decoder) { 1450 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1451 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1452 1453 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1454 } 1455 1456 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1457 unsigned RegNo, 1458 uint64_t Address, 1459 const void *Decoder) { 1460 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1461 } 1462 1463 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1464 unsigned RegNo, 1465 uint64_t Address, 1466 const void *Decoder) { 1467 if (RegNo > 31) 1468 return MCDisassembler::Fail; 1469 1470 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1471 Inst.addOperand(MCOperand::createReg(Reg)); 1472 return MCDisassembler::Success; 1473 } 1474 1475 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1476 unsigned RegNo, 1477 uint64_t Address, 1478 const void *Decoder) { 1479 if (RegNo > 31) 1480 return MCDisassembler::Fail; 1481 1482 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1483 Inst.addOperand(MCOperand::createReg(Reg)); 1484 return MCDisassembler::Success; 1485 } 1486 1487 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1488 unsigned RegNo, 1489 uint64_t Address, 1490 const void *Decoder) { 1491 if (RegNo > 31) 1492 return MCDisassembler::Fail; 1493 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1494 Inst.addOperand(MCOperand::createReg(Reg)); 1495 return MCDisassembler::Success; 1496 } 1497 1498 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1499 unsigned RegNo, 1500 uint64_t Address, 1501 const void *Decoder) { 1502 if (RegNo > 7) 1503 return MCDisassembler::Fail; 1504 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1505 Inst.addOperand(MCOperand::createReg(Reg)); 1506 return MCDisassembler::Success; 1507 } 1508 1509 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1510 uint64_t Address, 1511 const void *Decoder) { 1512 if (RegNo > 31) 1513 return MCDisassembler::Fail; 1514 1515 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1516 Inst.addOperand(MCOperand::createReg(Reg)); 1517 return MCDisassembler::Success; 1518 } 1519 1520 static DecodeStatus DecodeMem(MCInst &Inst, 1521 unsigned Insn, 1522 uint64_t Address, 1523 const void *Decoder) { 1524 int Offset = SignExtend32<16>(Insn & 0xffff); 1525 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1526 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1527 1528 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1529 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1530 1531 if (Inst.getOpcode() == Mips::SC || 1532 Inst.getOpcode() == Mips::SCD) 1533 Inst.addOperand(MCOperand::createReg(Reg)); 1534 1535 Inst.addOperand(MCOperand::createReg(Reg)); 1536 Inst.addOperand(MCOperand::createReg(Base)); 1537 Inst.addOperand(MCOperand::createImm(Offset)); 1538 1539 return MCDisassembler::Success; 1540 } 1541 1542 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1543 unsigned Insn, 1544 uint64_t Address, 1545 const void *Decoder) { 1546 int Offset = SignExtend32<9>(Insn >> 7); 1547 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1548 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1549 1550 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1551 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1552 1553 if (Inst.getOpcode() == Mips::SCE) 1554 Inst.addOperand(MCOperand::createReg(Reg)); 1555 1556 Inst.addOperand(MCOperand::createReg(Reg)); 1557 Inst.addOperand(MCOperand::createReg(Base)); 1558 Inst.addOperand(MCOperand::createImm(Offset)); 1559 1560 return MCDisassembler::Success; 1561 } 1562 1563 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1564 unsigned Insn, 1565 uint64_t Address, 1566 const void *Decoder) { 1567 int Offset = SignExtend32<16>(Insn & 0xffff); 1568 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1569 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1570 1571 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1572 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1573 1574 Inst.addOperand(MCOperand::createReg(Reg)); 1575 Inst.addOperand(MCOperand::createReg(Base)); 1576 Inst.addOperand(MCOperand::createImm(Offset)); 1577 1578 return MCDisassembler::Success; 1579 } 1580 1581 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1582 unsigned Insn, 1583 uint64_t Address, 1584 const void *Decoder) { 1585 int Offset = SignExtend32<16>(Insn & 0xffff); 1586 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1587 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1588 1589 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1590 1591 Inst.addOperand(MCOperand::createReg(Base)); 1592 Inst.addOperand(MCOperand::createImm(Offset)); 1593 Inst.addOperand(MCOperand::createImm(Hint)); 1594 1595 return MCDisassembler::Success; 1596 } 1597 1598 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1599 unsigned Insn, 1600 uint64_t Address, 1601 const void *Decoder) { 1602 int Offset = SignExtend32<12>(Insn & 0xfff); 1603 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1604 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1605 1606 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1607 1608 Inst.addOperand(MCOperand::createReg(Base)); 1609 Inst.addOperand(MCOperand::createImm(Offset)); 1610 Inst.addOperand(MCOperand::createImm(Hint)); 1611 1612 return MCDisassembler::Success; 1613 } 1614 1615 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1616 unsigned Insn, 1617 uint64_t Address, 1618 const void *Decoder) { 1619 int Offset = SignExtend32<9>(Insn & 0x1ff); 1620 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1621 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1622 1623 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1624 1625 Inst.addOperand(MCOperand::createReg(Base)); 1626 Inst.addOperand(MCOperand::createImm(Offset)); 1627 Inst.addOperand(MCOperand::createImm(Hint)); 1628 1629 return MCDisassembler::Success; 1630 } 1631 1632 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1633 unsigned Insn, 1634 uint64_t Address, 1635 const void *Decoder) { 1636 int Offset = SignExtend32<9>(Insn >> 7); 1637 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1638 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1639 1640 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1641 1642 Inst.addOperand(MCOperand::createReg(Base)); 1643 Inst.addOperand(MCOperand::createImm(Offset)); 1644 Inst.addOperand(MCOperand::createImm(Hint)); 1645 1646 return MCDisassembler::Success; 1647 } 1648 1649 static DecodeStatus DecodeSyncI(MCInst &Inst, 1650 unsigned Insn, 1651 uint64_t Address, 1652 const void *Decoder) { 1653 int Offset = SignExtend32<16>(Insn & 0xffff); 1654 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1655 1656 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1657 1658 Inst.addOperand(MCOperand::createReg(Base)); 1659 Inst.addOperand(MCOperand::createImm(Offset)); 1660 1661 return MCDisassembler::Success; 1662 } 1663 1664 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1665 uint64_t Address, const void *Decoder) { 1666 int Offset = SignExtend32<16>(Insn & 0xffff); 1667 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1668 1669 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1670 1671 Inst.addOperand(MCOperand::createReg(Base)); 1672 Inst.addOperand(MCOperand::createImm(Offset)); 1673 1674 return MCDisassembler::Success; 1675 } 1676 1677 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1678 unsigned Insn, 1679 uint64_t Address, 1680 const void *Decoder) { 1681 int Immediate = SignExtend32<16>(Insn & 0xffff); 1682 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1683 1684 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1685 1686 Inst.addOperand(MCOperand::createReg(Base)); 1687 Inst.addOperand(MCOperand::createImm(Immediate)); 1688 1689 return MCDisassembler::Success; 1690 } 1691 1692 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1693 uint64_t Address, const void *Decoder) { 1694 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1695 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1696 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1697 1698 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1699 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1700 1701 Inst.addOperand(MCOperand::createReg(Reg)); 1702 Inst.addOperand(MCOperand::createReg(Base)); 1703 1704 // The immediate field of an LD/ST instruction is scaled which means it must 1705 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1706 // data format. 1707 // .b - 1 byte 1708 // .h - 2 bytes 1709 // .w - 4 bytes 1710 // .d - 8 bytes 1711 switch(Inst.getOpcode()) 1712 { 1713 default: 1714 assert(false && "Unexpected instruction"); 1715 return MCDisassembler::Fail; 1716 break; 1717 case Mips::LD_B: 1718 case Mips::ST_B: 1719 Inst.addOperand(MCOperand::createImm(Offset)); 1720 break; 1721 case Mips::LD_H: 1722 case Mips::ST_H: 1723 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1724 break; 1725 case Mips::LD_W: 1726 case Mips::ST_W: 1727 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1728 break; 1729 case Mips::LD_D: 1730 case Mips::ST_D: 1731 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1732 break; 1733 } 1734 1735 return MCDisassembler::Success; 1736 } 1737 1738 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1739 unsigned Insn, 1740 uint64_t Address, 1741 const void *Decoder) { 1742 unsigned Offset = Insn & 0xf; 1743 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1744 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1745 1746 switch (Inst.getOpcode()) { 1747 case Mips::LBU16_MM: 1748 case Mips::LHU16_MM: 1749 case Mips::LW16_MM: 1750 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1751 == MCDisassembler::Fail) 1752 return MCDisassembler::Fail; 1753 break; 1754 case Mips::SB16_MM: 1755 case Mips::SB16_MMR6: 1756 case Mips::SH16_MM: 1757 case Mips::SH16_MMR6: 1758 case Mips::SW16_MM: 1759 case Mips::SW16_MMR6: 1760 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1761 == MCDisassembler::Fail) 1762 return MCDisassembler::Fail; 1763 break; 1764 } 1765 1766 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1767 == MCDisassembler::Fail) 1768 return MCDisassembler::Fail; 1769 1770 switch (Inst.getOpcode()) { 1771 case Mips::LBU16_MM: 1772 if (Offset == 0xf) 1773 Inst.addOperand(MCOperand::createImm(-1)); 1774 else 1775 Inst.addOperand(MCOperand::createImm(Offset)); 1776 break; 1777 case Mips::SB16_MM: 1778 case Mips::SB16_MMR6: 1779 Inst.addOperand(MCOperand::createImm(Offset)); 1780 break; 1781 case Mips::LHU16_MM: 1782 case Mips::SH16_MM: 1783 case Mips::SH16_MMR6: 1784 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1785 break; 1786 case Mips::LW16_MM: 1787 case Mips::SW16_MM: 1788 case Mips::SW16_MMR6: 1789 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1790 break; 1791 } 1792 1793 return MCDisassembler::Success; 1794 } 1795 1796 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1797 unsigned Insn, 1798 uint64_t Address, 1799 const void *Decoder) { 1800 unsigned Offset = Insn & 0x1F; 1801 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1802 1803 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1804 1805 Inst.addOperand(MCOperand::createReg(Reg)); 1806 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1807 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1808 1809 return MCDisassembler::Success; 1810 } 1811 1812 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1813 unsigned Insn, 1814 uint64_t Address, 1815 const void *Decoder) { 1816 unsigned Offset = Insn & 0x7F; 1817 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1818 1819 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1820 1821 Inst.addOperand(MCOperand::createReg(Reg)); 1822 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1823 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1824 1825 return MCDisassembler::Success; 1826 } 1827 1828 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1829 unsigned Insn, 1830 uint64_t Address, 1831 const void *Decoder) { 1832 int Offset; 1833 switch (Inst.getOpcode()) { 1834 case Mips::LWM16_MMR6: 1835 case Mips::SWM16_MMR6: 1836 Offset = fieldFromInstruction(Insn, 4, 4); 1837 break; 1838 default: 1839 Offset = SignExtend32<4>(Insn & 0xf); 1840 break; 1841 } 1842 1843 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1844 == MCDisassembler::Fail) 1845 return MCDisassembler::Fail; 1846 1847 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1848 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1849 1850 return MCDisassembler::Success; 1851 } 1852 1853 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1854 unsigned Insn, 1855 uint64_t Address, 1856 const void *Decoder) { 1857 int Offset = SignExtend32<9>(Insn & 0x1ff); 1858 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1859 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1860 1861 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1862 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1863 1864 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) 1865 Inst.addOperand(MCOperand::createReg(Reg)); 1866 1867 Inst.addOperand(MCOperand::createReg(Reg)); 1868 Inst.addOperand(MCOperand::createReg(Base)); 1869 Inst.addOperand(MCOperand::createImm(Offset)); 1870 1871 return MCDisassembler::Success; 1872 } 1873 1874 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1875 unsigned Insn, 1876 uint64_t Address, 1877 const void *Decoder) { 1878 int Offset = SignExtend32<12>(Insn & 0x0fff); 1879 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1880 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1881 1882 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1883 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1884 1885 switch (Inst.getOpcode()) { 1886 case Mips::SWM32_MM: 1887 case Mips::LWM32_MM: 1888 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1889 == MCDisassembler::Fail) 1890 return MCDisassembler::Fail; 1891 Inst.addOperand(MCOperand::createReg(Base)); 1892 Inst.addOperand(MCOperand::createImm(Offset)); 1893 break; 1894 case Mips::SC_MM: 1895 Inst.addOperand(MCOperand::createReg(Reg)); 1896 LLVM_FALLTHROUGH; 1897 default: 1898 Inst.addOperand(MCOperand::createReg(Reg)); 1899 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1900 Inst.addOperand(MCOperand::createReg(Reg+1)); 1901 1902 Inst.addOperand(MCOperand::createReg(Base)); 1903 Inst.addOperand(MCOperand::createImm(Offset)); 1904 } 1905 1906 return MCDisassembler::Success; 1907 } 1908 1909 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1910 unsigned Insn, 1911 uint64_t Address, 1912 const void *Decoder) { 1913 int Offset = SignExtend32<16>(Insn & 0xffff); 1914 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1915 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1916 1917 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1918 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1919 1920 Inst.addOperand(MCOperand::createReg(Reg)); 1921 Inst.addOperand(MCOperand::createReg(Base)); 1922 Inst.addOperand(MCOperand::createImm(Offset)); 1923 1924 return MCDisassembler::Success; 1925 } 1926 1927 static DecodeStatus DecodeFMem(MCInst &Inst, 1928 unsigned Insn, 1929 uint64_t Address, 1930 const void *Decoder) { 1931 int Offset = SignExtend32<16>(Insn & 0xffff); 1932 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1933 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1934 1935 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1936 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1937 1938 Inst.addOperand(MCOperand::createReg(Reg)); 1939 Inst.addOperand(MCOperand::createReg(Base)); 1940 Inst.addOperand(MCOperand::createImm(Offset)); 1941 1942 return MCDisassembler::Success; 1943 } 1944 1945 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1946 uint64_t Address, const void *Decoder) { 1947 // This function is the same as DecodeFMem but with the Reg and Base fields 1948 // swapped according to microMIPS spec. 1949 int Offset = SignExtend32<16>(Insn & 0xffff); 1950 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1951 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1952 1953 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1954 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1955 1956 Inst.addOperand(MCOperand::createReg(Reg)); 1957 Inst.addOperand(MCOperand::createReg(Base)); 1958 Inst.addOperand(MCOperand::createImm(Offset)); 1959 1960 return MCDisassembler::Success; 1961 } 1962 1963 static DecodeStatus DecodeFMem2(MCInst &Inst, 1964 unsigned Insn, 1965 uint64_t Address, 1966 const void *Decoder) { 1967 int Offset = SignExtend32<16>(Insn & 0xffff); 1968 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1969 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1970 1971 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1972 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1973 1974 Inst.addOperand(MCOperand::createReg(Reg)); 1975 Inst.addOperand(MCOperand::createReg(Base)); 1976 Inst.addOperand(MCOperand::createImm(Offset)); 1977 1978 return MCDisassembler::Success; 1979 } 1980 1981 static DecodeStatus DecodeFMem3(MCInst &Inst, 1982 unsigned Insn, 1983 uint64_t Address, 1984 const void *Decoder) { 1985 int Offset = SignExtend32<16>(Insn & 0xffff); 1986 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1987 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1988 1989 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1990 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1991 1992 Inst.addOperand(MCOperand::createReg(Reg)); 1993 Inst.addOperand(MCOperand::createReg(Base)); 1994 Inst.addOperand(MCOperand::createImm(Offset)); 1995 1996 return MCDisassembler::Success; 1997 } 1998 1999 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2000 unsigned Insn, 2001 uint64_t Address, 2002 const void *Decoder) { 2003 int Offset = SignExtend32<11>(Insn & 0x07ff); 2004 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2005 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2006 2007 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2008 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2009 2010 Inst.addOperand(MCOperand::createReg(Reg)); 2011 Inst.addOperand(MCOperand::createReg(Base)); 2012 Inst.addOperand(MCOperand::createImm(Offset)); 2013 2014 return MCDisassembler::Success; 2015 } 2016 2017 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2018 uint64_t Address, const void *Decoder) { 2019 int Offset = SignExtend32<11>(Insn & 0x07ff); 2020 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2021 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2022 2023 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2024 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2025 2026 Inst.addOperand(MCOperand::createReg(Reg)); 2027 Inst.addOperand(MCOperand::createReg(Base)); 2028 Inst.addOperand(MCOperand::createImm(Offset)); 2029 2030 return MCDisassembler::Success; 2031 } 2032 2033 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2034 unsigned Insn, 2035 uint64_t Address, 2036 const void *Decoder) { 2037 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2038 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2039 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2040 2041 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2042 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2043 2044 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2045 Inst.addOperand(MCOperand::createReg(Rt)); 2046 } 2047 2048 Inst.addOperand(MCOperand::createReg(Rt)); 2049 Inst.addOperand(MCOperand::createReg(Base)); 2050 Inst.addOperand(MCOperand::createImm(Offset)); 2051 2052 return MCDisassembler::Success; 2053 } 2054 2055 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2056 unsigned RegNo, 2057 uint64_t Address, 2058 const void *Decoder) { 2059 // Currently only hardware register 29 is supported. 2060 if (RegNo != 29) 2061 return MCDisassembler::Fail; 2062 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2063 return MCDisassembler::Success; 2064 } 2065 2066 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2067 unsigned RegNo, 2068 uint64_t Address, 2069 const void *Decoder) { 2070 if (RegNo > 30 || RegNo %2) 2071 return MCDisassembler::Fail; 2072 2073 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2074 Inst.addOperand(MCOperand::createReg(Reg)); 2075 return MCDisassembler::Success; 2076 } 2077 2078 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2079 unsigned RegNo, 2080 uint64_t Address, 2081 const void *Decoder) { 2082 if (RegNo >= 4) 2083 return MCDisassembler::Fail; 2084 2085 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2086 Inst.addOperand(MCOperand::createReg(Reg)); 2087 return MCDisassembler::Success; 2088 } 2089 2090 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2091 unsigned RegNo, 2092 uint64_t Address, 2093 const void *Decoder) { 2094 if (RegNo >= 4) 2095 return MCDisassembler::Fail; 2096 2097 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2098 Inst.addOperand(MCOperand::createReg(Reg)); 2099 return MCDisassembler::Success; 2100 } 2101 2102 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2103 unsigned RegNo, 2104 uint64_t Address, 2105 const void *Decoder) { 2106 if (RegNo >= 4) 2107 return MCDisassembler::Fail; 2108 2109 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2110 Inst.addOperand(MCOperand::createReg(Reg)); 2111 return MCDisassembler::Success; 2112 } 2113 2114 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2115 unsigned RegNo, 2116 uint64_t Address, 2117 const void *Decoder) { 2118 if (RegNo > 31) 2119 return MCDisassembler::Fail; 2120 2121 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2122 Inst.addOperand(MCOperand::createReg(Reg)); 2123 return MCDisassembler::Success; 2124 } 2125 2126 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2127 unsigned RegNo, 2128 uint64_t Address, 2129 const void *Decoder) { 2130 if (RegNo > 31) 2131 return MCDisassembler::Fail; 2132 2133 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2134 Inst.addOperand(MCOperand::createReg(Reg)); 2135 return MCDisassembler::Success; 2136 } 2137 2138 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2139 unsigned RegNo, 2140 uint64_t Address, 2141 const void *Decoder) { 2142 if (RegNo > 31) 2143 return MCDisassembler::Fail; 2144 2145 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2146 Inst.addOperand(MCOperand::createReg(Reg)); 2147 return MCDisassembler::Success; 2148 } 2149 2150 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2151 unsigned RegNo, 2152 uint64_t Address, 2153 const void *Decoder) { 2154 if (RegNo > 31) 2155 return MCDisassembler::Fail; 2156 2157 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2158 Inst.addOperand(MCOperand::createReg(Reg)); 2159 return MCDisassembler::Success; 2160 } 2161 2162 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2163 unsigned RegNo, 2164 uint64_t Address, 2165 const void *Decoder) { 2166 if (RegNo > 7) 2167 return MCDisassembler::Fail; 2168 2169 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2170 Inst.addOperand(MCOperand::createReg(Reg)); 2171 return MCDisassembler::Success; 2172 } 2173 2174 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2175 unsigned RegNo, 2176 uint64_t Address, 2177 const void *Decoder) { 2178 if (RegNo > 31) 2179 return MCDisassembler::Fail; 2180 2181 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2182 Inst.addOperand(MCOperand::createReg(Reg)); 2183 return MCDisassembler::Success; 2184 } 2185 2186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2187 unsigned RegNo, 2188 uint64_t Address, 2189 const void *Decoder) { 2190 if (RegNo > 31) 2191 return MCDisassembler::Fail; 2192 2193 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2194 Inst.addOperand(MCOperand::createReg(Reg)); 2195 return MCDisassembler::Success; 2196 } 2197 2198 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2199 unsigned Offset, 2200 uint64_t Address, 2201 const void *Decoder) { 2202 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2203 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2204 return MCDisassembler::Success; 2205 } 2206 2207 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2208 unsigned Offset, 2209 uint64_t Address, 2210 const void *Decoder) { 2211 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2212 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2213 return MCDisassembler::Success; 2214 } 2215 2216 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2217 unsigned Insn, 2218 uint64_t Address, 2219 const void *Decoder) { 2220 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2221 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2222 return MCDisassembler::Success; 2223 } 2224 2225 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2226 unsigned Offset, 2227 uint64_t Address, 2228 const void *Decoder) { 2229 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2230 2231 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2232 return MCDisassembler::Success; 2233 } 2234 2235 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2236 unsigned Offset, 2237 uint64_t Address, 2238 const void *Decoder) { 2239 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2240 2241 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2242 return MCDisassembler::Success; 2243 } 2244 2245 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2246 unsigned Offset, 2247 uint64_t Address, 2248 const void *Decoder) { 2249 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2250 2251 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2252 return MCDisassembler::Success; 2253 } 2254 2255 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2256 unsigned Offset, 2257 uint64_t Address, 2258 const void *Decoder) { 2259 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2260 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2261 return MCDisassembler::Success; 2262 } 2263 2264 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2265 unsigned Offset, 2266 uint64_t Address, 2267 const void *Decoder) { 2268 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2269 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2270 return MCDisassembler::Success; 2271 } 2272 2273 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2274 unsigned Offset, 2275 uint64_t Address, 2276 const void *Decoder) { 2277 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2278 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2279 return MCDisassembler::Success; 2280 } 2281 2282 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2283 unsigned Offset, 2284 uint64_t Address, 2285 const void *Decoder) { 2286 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2287 2288 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2289 return MCDisassembler::Success; 2290 } 2291 2292 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2293 unsigned Insn, 2294 uint64_t Address, 2295 const void *Decoder) { 2296 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2297 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2298 return MCDisassembler::Success; 2299 } 2300 2301 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 2302 unsigned Insn, 2303 uint64_t Address, 2304 const void *Decoder) { 2305 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2306 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2307 return MCDisassembler::Success; 2308 } 2309 2310 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2311 unsigned Value, 2312 uint64_t Address, 2313 const void *Decoder) { 2314 if (Value == 0) 2315 Inst.addOperand(MCOperand::createImm(1)); 2316 else if (Value == 0x7) 2317 Inst.addOperand(MCOperand::createImm(-1)); 2318 else 2319 Inst.addOperand(MCOperand::createImm(Value << 2)); 2320 return MCDisassembler::Success; 2321 } 2322 2323 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2324 unsigned Value, 2325 uint64_t Address, 2326 const void *Decoder) { 2327 if (Value == 0x7F) 2328 Inst.addOperand(MCOperand::createImm(-1)); 2329 else 2330 Inst.addOperand(MCOperand::createImm(Value)); 2331 return MCDisassembler::Success; 2332 } 2333 2334 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2335 unsigned Value, 2336 uint64_t Address, 2337 const void *Decoder) { 2338 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2339 return MCDisassembler::Success; 2340 } 2341 2342 template <unsigned Bits, int Offset, int Scale> 2343 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2344 uint64_t Address, 2345 const void *Decoder) { 2346 Value &= ((1 << Bits) - 1); 2347 Value *= Scale; 2348 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2349 return MCDisassembler::Success; 2350 } 2351 2352 template <unsigned Bits, int Offset, int ScaleBy> 2353 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2354 uint64_t Address, 2355 const void *Decoder) { 2356 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2357 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2358 return MCDisassembler::Success; 2359 } 2360 2361 static DecodeStatus DecodeInsSize(MCInst &Inst, 2362 unsigned Insn, 2363 uint64_t Address, 2364 const void *Decoder) { 2365 // First we need to grab the pos(lsb) from MCInst. 2366 // This function only handles the 32 bit variants of ins, as dins 2367 // variants are handled differently. 2368 int Pos = Inst.getOperand(2).getImm(); 2369 int Size = (int) Insn - Pos + 1; 2370 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2371 return MCDisassembler::Success; 2372 } 2373 2374 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2375 uint64_t Address, const void *Decoder) { 2376 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2377 return MCDisassembler::Success; 2378 } 2379 2380 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2381 uint64_t Address, const void *Decoder) { 2382 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2383 return MCDisassembler::Success; 2384 } 2385 2386 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2387 uint64_t Address, const void *Decoder) { 2388 int32_t DecodedValue; 2389 switch (Insn) { 2390 case 0: DecodedValue = 256; break; 2391 case 1: DecodedValue = 257; break; 2392 case 510: DecodedValue = -258; break; 2393 case 511: DecodedValue = -257; break; 2394 default: DecodedValue = SignExtend32<9>(Insn); break; 2395 } 2396 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2397 return MCDisassembler::Success; 2398 } 2399 2400 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2401 uint64_t Address, const void *Decoder) { 2402 // Insn must be >= 0, since it is unsigned that condition is always true. 2403 assert(Insn < 16); 2404 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2405 255, 32768, 65535}; 2406 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2407 return MCDisassembler::Success; 2408 } 2409 2410 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2411 unsigned Insn, 2412 uint64_t Address, 2413 const void *Decoder) { 2414 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2415 Mips::S6, Mips::S7, Mips::FP}; 2416 unsigned RegNum; 2417 2418 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2419 2420 // Empty register lists are not allowed. 2421 if (RegLst == 0) 2422 return MCDisassembler::Fail; 2423 2424 RegNum = RegLst & 0xf; 2425 2426 // RegLst values 10-15, and 26-31 are reserved. 2427 if (RegNum > 9) 2428 return MCDisassembler::Fail; 2429 2430 for (unsigned i = 0; i < RegNum; i++) 2431 Inst.addOperand(MCOperand::createReg(Regs[i])); 2432 2433 if (RegLst & 0x10) 2434 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2435 2436 return MCDisassembler::Success; 2437 } 2438 2439 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2440 uint64_t Address, 2441 const void *Decoder) { 2442 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2443 unsigned RegLst; 2444 switch(Inst.getOpcode()) { 2445 default: 2446 RegLst = fieldFromInstruction(Insn, 4, 2); 2447 break; 2448 case Mips::LWM16_MMR6: 2449 case Mips::SWM16_MMR6: 2450 RegLst = fieldFromInstruction(Insn, 8, 2); 2451 break; 2452 } 2453 unsigned RegNum = RegLst & 0x3; 2454 2455 for (unsigned i = 0; i <= RegNum; i++) 2456 Inst.addOperand(MCOperand::createReg(Regs[i])); 2457 2458 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2459 2460 return MCDisassembler::Success; 2461 } 2462 2463 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 2464 uint64_t Address, 2465 const void *Decoder) { 2466 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2467 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == 2468 MCDisassembler::Fail) 2469 return MCDisassembler::Fail; 2470 2471 unsigned RegRs; 2472 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) 2473 RegRs = fieldFromInstruction(Insn, 0, 2) | 2474 (fieldFromInstruction(Insn, 3, 1) << 2); 2475 else 2476 RegRs = fieldFromInstruction(Insn, 1, 3); 2477 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == 2478 MCDisassembler::Fail) 2479 return MCDisassembler::Fail; 2480 2481 unsigned RegRt = fieldFromInstruction(Insn, 4, 3); 2482 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == 2483 MCDisassembler::Fail) 2484 return MCDisassembler::Fail; 2485 2486 return MCDisassembler::Success; 2487 } 2488 2489 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2490 uint64_t Address, const void *Decoder) { 2491 switch (RegPair) { 2492 default: 2493 return MCDisassembler::Fail; 2494 case 0: 2495 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2496 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2497 break; 2498 case 1: 2499 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2500 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2501 break; 2502 case 2: 2503 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2504 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2505 break; 2506 case 3: 2507 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2508 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2509 break; 2510 case 4: 2511 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2512 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2513 break; 2514 case 5: 2515 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2516 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2517 break; 2518 case 6: 2519 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2520 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2521 break; 2522 case 7: 2523 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2524 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2525 break; 2526 } 2527 2528 return MCDisassembler::Success; 2529 } 2530 2531 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2532 uint64_t Address, const void *Decoder) { 2533 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2534 return MCDisassembler::Success; 2535 } 2536 2537 template <typename InsnType> 2538 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2539 uint64_t Address, 2540 const void *Decoder) { 2541 // We have: 2542 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2543 // Invalid if rt == 0 2544 // BGTZALC_MMR6 if rs == 0 && rt != 0 2545 // BLTZALC_MMR6 if rs != 0 && rs == rt 2546 // BLTUC_MMR6 if rs != 0 && rs != rt 2547 2548 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2549 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2550 InsnType Imm = 0; 2551 bool HasRs = false; 2552 bool HasRt = false; 2553 2554 if (Rt == 0) 2555 return MCDisassembler::Fail; 2556 else if (Rs == 0) { 2557 MI.setOpcode(Mips::BGTZALC_MMR6); 2558 HasRt = true; 2559 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2560 } 2561 else if (Rs == Rt) { 2562 MI.setOpcode(Mips::BLTZALC_MMR6); 2563 HasRs = true; 2564 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2565 } 2566 else { 2567 MI.setOpcode(Mips::BLTUC_MMR6); 2568 HasRs = true; 2569 HasRt = true; 2570 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2571 } 2572 2573 if (HasRs) 2574 MI.addOperand( 2575 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2576 2577 if (HasRt) 2578 MI.addOperand( 2579 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2580 2581 MI.addOperand(MCOperand::createImm(Imm)); 2582 2583 return MCDisassembler::Success; 2584 } 2585 2586 template <typename InsnType> 2587 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2588 uint64_t Address, 2589 const void *Decoder) { 2590 // We have: 2591 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2592 // Invalid if rt == 0 2593 // BLEZALC_MMR6 if rs == 0 && rt != 0 2594 // BGEZALC_MMR6 if rs == rt && rt != 0 2595 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2596 2597 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2598 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2599 InsnType Imm = 0; 2600 bool HasRs = false; 2601 2602 if (Rt == 0) 2603 return MCDisassembler::Fail; 2604 else if (Rs == 0) { 2605 MI.setOpcode(Mips::BLEZALC_MMR6); 2606 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2607 } 2608 else if (Rs == Rt) { 2609 MI.setOpcode(Mips::BGEZALC_MMR6); 2610 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2611 } 2612 else { 2613 HasRs = true; 2614 MI.setOpcode(Mips::BGEUC_MMR6); 2615 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2616 } 2617 2618 if (HasRs) 2619 MI.addOperand( 2620 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2621 MI.addOperand( 2622 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2623 2624 MI.addOperand(MCOperand::createImm(Imm)); 2625 2626 return MCDisassembler::Success; 2627 } 2628