1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "llvm/ADT/ArrayRef.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <cassert> 29 #include <cstdint> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "mips-disassembler" 34 35 typedef MCDisassembler::DecodeStatus DecodeStatus; 36 37 namespace { 38 39 class MipsDisassembler : public MCDisassembler { 40 bool IsMicroMips; 41 bool IsBigEndian; 42 43 public: 44 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 45 : MCDisassembler(STI, Ctx), 46 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 47 IsBigEndian(IsBigEndian) {} 48 49 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 50 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 51 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 52 53 bool hasMips32r6() const { 54 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 55 } 56 57 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 58 59 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 60 61 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 62 63 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 64 65 bool hasCOP3() const { 66 // Only present in MIPS-I and MIPS-II 67 return !hasMips32() && !hasMips3(); 68 } 69 70 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 71 ArrayRef<uint8_t> Bytes, uint64_t Address, 72 raw_ostream &VStream, 73 raw_ostream &CStream) const override; 74 }; 75 76 } // end anonymous namespace 77 78 // Forward declare these because the autogenerated code will reference them. 79 // Definitions are further down. 80 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 81 unsigned RegNo, 82 uint64_t Address, 83 const void *Decoder); 84 85 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 86 unsigned RegNo, 87 uint64_t Address, 88 const void *Decoder); 89 90 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 91 unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 95 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 96 unsigned RegNo, 97 uint64_t Address, 98 const void *Decoder); 99 100 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 101 unsigned RegNo, 102 uint64_t Address, 103 const void *Decoder); 104 105 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 106 unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 110 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 111 unsigned Insn, 112 uint64_t Address, 113 const void *Decoder); 114 115 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 116 unsigned RegNo, 117 uint64_t Address, 118 const void *Decoder); 119 120 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 125 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 126 unsigned RegNo, 127 uint64_t Address, 128 const void *Decoder); 129 130 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 131 unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 136 unsigned RegNo, 137 uint64_t Address, 138 const void *Decoder); 139 140 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 141 uint64_t Address, 142 const void *Decoder); 143 144 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 145 unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148 149 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 150 unsigned RegNo, 151 uint64_t Address, 152 const void *Decoder); 153 154 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 155 unsigned RegNo, 156 uint64_t Address, 157 const void *Decoder); 158 159 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 160 unsigned RegNo, 161 uint64_t Address, 162 const void *Decoder); 163 164 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 165 unsigned RegNo, 166 uint64_t Address, 167 const void *Decoder); 168 169 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 170 unsigned RegNo, 171 uint64_t Address, 172 const void *Decoder); 173 174 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Address, 177 const void *Decoder); 178 179 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 180 unsigned RegNo, 181 uint64_t Address, 182 const void *Decoder); 183 184 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 185 unsigned RegNo, 186 uint64_t Address, 187 const void *Decoder); 188 189 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 190 unsigned RegNo, 191 uint64_t Address, 192 const void *Decoder); 193 194 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 195 unsigned RegNo, 196 uint64_t Address, 197 const void *Decoder); 198 199 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 200 unsigned RegNo, 201 uint64_t Address, 202 const void *Decoder); 203 204 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 205 unsigned Offset, 206 uint64_t Address, 207 const void *Decoder); 208 209 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 210 unsigned Offset, 211 uint64_t Address, 212 const void *Decoder); 213 214 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 215 unsigned Insn, 216 uint64_t Address, 217 const void *Decoder); 218 219 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 220 unsigned Offset, 221 uint64_t Address, 222 const void *Decoder); 223 224 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 225 unsigned Offset, 226 uint64_t Address, 227 const void *Decoder); 228 229 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 230 unsigned Offset, 231 uint64_t Address, 232 const void *Decoder); 233 234 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 235 // shifted left by 1 bit. 236 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 237 unsigned Offset, 238 uint64_t Address, 239 const void *Decoder); 240 241 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 242 // shifted left by 1 bit. 243 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 244 unsigned Offset, 245 uint64_t Address, 246 const void *Decoder); 247 248 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 249 // shifted left by 1 bit. 250 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 251 unsigned Offset, 252 uint64_t Address, 253 const void *Decoder); 254 255 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 256 // shifted left by 1 bit. 257 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 258 unsigned Offset, 259 uint64_t Address, 260 const void *Decoder); 261 262 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 263 // shifted left by 1 bit. 264 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 265 unsigned Insn, 266 uint64_t Address, 267 const void *Decoder); 268 269 static DecodeStatus DecodeMem(MCInst &Inst, 270 unsigned Insn, 271 uint64_t Address, 272 const void *Decoder); 273 274 static DecodeStatus DecodeMemEVA(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 285 unsigned Insn, 286 uint64_t Address, 287 const void *Decoder); 288 289 static DecodeStatus DecodeCacheOp(MCInst &Inst, 290 unsigned Insn, 291 uint64_t Address, 292 const void *Decoder); 293 294 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 295 unsigned Insn, 296 uint64_t Address, 297 const void *Decoder); 298 299 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 300 unsigned Insn, 301 uint64_t Address, 302 const void *Decoder); 303 304 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 305 unsigned Insn, 306 uint64_t Address, 307 const void *Decoder); 308 309 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 310 unsigned Insn, 311 uint64_t Address, 312 const void *Decoder); 313 314 static DecodeStatus DecodeSyncI(MCInst &Inst, 315 unsigned Insn, 316 uint64_t Address, 317 const void *Decoder); 318 319 static DecodeStatus DecodeSynciR6(MCInst &Inst, 320 unsigned Insn, 321 uint64_t Address, 322 const void *Decoder); 323 324 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 327 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 328 unsigned Insn, 329 uint64_t Address, 330 const void *Decoder); 331 332 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 333 unsigned Insn, 334 uint64_t Address, 335 const void *Decoder); 336 337 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 338 unsigned Insn, 339 uint64_t Address, 340 const void *Decoder); 341 342 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 343 unsigned Insn, 344 uint64_t Address, 345 const void *Decoder); 346 347 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 348 unsigned Insn, 349 uint64_t Address, 350 const void *Decoder); 351 352 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 353 unsigned Insn, 354 uint64_t Address, 355 const void *Decoder); 356 357 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 358 unsigned Insn, 359 uint64_t Address, 360 const void *Decoder); 361 362 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 363 uint64_t Address, 364 const void *Decoder); 365 366 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 367 uint64_t Address, 368 const void *Decoder); 369 370 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 371 uint64_t Address, 372 const void *Decoder); 373 374 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 375 uint64_t Address, 376 const void *Decoder); 377 378 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 383 uint64_t Address, 384 const void *Decoder); 385 386 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 387 unsigned Insn, 388 uint64_t Address, 389 const void *Decoder); 390 391 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 392 unsigned Value, 393 uint64_t Address, 394 const void *Decoder); 395 396 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 397 unsigned Value, 398 uint64_t Address, 399 const void *Decoder); 400 401 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 402 unsigned Value, 403 uint64_t Address, 404 const void *Decoder); 405 406 template <unsigned Bits, int Offset, int Scale> 407 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 408 uint64_t Address, 409 const void *Decoder); 410 411 template <unsigned Bits, int Offset> 412 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 413 uint64_t Address, 414 const void *Decoder) { 415 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 416 Decoder); 417 } 418 419 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 420 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 421 uint64_t Address, 422 const void *Decoder); 423 424 static DecodeStatus DecodeInsSize(MCInst &Inst, 425 unsigned Insn, 426 uint64_t Address, 427 const void *Decoder); 428 429 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 436 uint64_t Address, const void *Decoder); 437 438 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 439 uint64_t Address, const void *Decoder); 440 441 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 442 uint64_t Address, const void *Decoder); 443 444 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 445 /// handle. 446 template <typename InsnType> 447 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 452 const void *Decoder); 453 454 template <typename InsnType> 455 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 464 const void *Decoder); 465 466 template <typename InsnType> 467 static DecodeStatus 468 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 469 const void *Decoder); 470 471 template <typename InsnType> 472 static DecodeStatus 473 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 474 const void *Decoder); 475 476 template <typename InsnType> 477 static DecodeStatus 478 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 479 const void *Decoder); 480 481 template <typename InsnType> 482 static DecodeStatus 483 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 484 const void *Decoder); 485 486 template <typename InsnType> 487 static DecodeStatus 488 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 489 const void *Decoder); 490 491 template <typename InsnType> 492 static DecodeStatus 493 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 494 const void *Decoder); 495 496 template <typename InsnType> 497 static DecodeStatus 498 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 499 const void *Decoder); 500 501 template <typename InsnType> 502 static DecodeStatus 503 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 504 const void *Decoder); 505 506 template <typename InsnType> 507 static DecodeStatus 508 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 509 const void *Decoder); 510 511 template <typename InsnType> 512 static DecodeStatus 513 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 514 const void *Decoder); 515 516 template <typename InsnType> 517 static DecodeStatus 518 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 519 const void *Decoder); 520 521 template <typename InsnType> 522 static DecodeStatus 523 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 524 const void *Decoder); 525 526 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 527 uint64_t Address, 528 const void *Decoder); 529 530 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 531 uint64_t Address, 532 const void *Decoder); 533 534 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 535 uint64_t Address, 536 const void *Decoder); 537 538 namespace llvm { 539 540 Target &getTheMipselTarget(); 541 Target &getTheMipsTarget(); 542 Target &getTheMips64Target(); 543 Target &getTheMips64elTarget(); 544 545 } // end namespace llvm 546 547 static MCDisassembler *createMipsDisassembler( 548 const Target &T, 549 const MCSubtargetInfo &STI, 550 MCContext &Ctx) { 551 return new MipsDisassembler(STI, Ctx, true); 552 } 553 554 static MCDisassembler *createMipselDisassembler( 555 const Target &T, 556 const MCSubtargetInfo &STI, 557 MCContext &Ctx) { 558 return new MipsDisassembler(STI, Ctx, false); 559 } 560 561 extern "C" void LLVMInitializeMipsDisassembler() { 562 // Register the disassembler. 563 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 564 createMipsDisassembler); 565 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 566 createMipselDisassembler); 567 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 568 createMipsDisassembler); 569 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 570 createMipselDisassembler); 571 } 572 573 #include "MipsGenDisassemblerTables.inc" 574 575 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 576 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 577 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 578 return *(RegInfo->getRegClass(RC).begin() + RegNo); 579 } 580 581 template <typename InsnType> 582 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 583 const void *Decoder) { 584 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 585 // The size of the n field depends on the element size 586 // The register class also depends on this. 587 InsnType tmp = fieldFromInstruction(insn, 17, 5); 588 unsigned NSize = 0; 589 DecodeFN RegDecoder = nullptr; 590 if ((tmp & 0x18) == 0x00) { // INSVE_B 591 NSize = 4; 592 RegDecoder = DecodeMSA128BRegisterClass; 593 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 594 NSize = 3; 595 RegDecoder = DecodeMSA128HRegisterClass; 596 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 597 NSize = 2; 598 RegDecoder = DecodeMSA128WRegisterClass; 599 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 600 NSize = 1; 601 RegDecoder = DecodeMSA128DRegisterClass; 602 } else 603 llvm_unreachable("Invalid encoding"); 604 605 assert(NSize != 0 && RegDecoder != nullptr); 606 607 // $wd 608 tmp = fieldFromInstruction(insn, 6, 5); 609 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 610 return MCDisassembler::Fail; 611 // $wd_in 612 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 613 return MCDisassembler::Fail; 614 // $n 615 tmp = fieldFromInstruction(insn, 16, NSize); 616 MI.addOperand(MCOperand::createImm(tmp)); 617 // $ws 618 tmp = fieldFromInstruction(insn, 11, 5); 619 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 620 return MCDisassembler::Fail; 621 // $n2 622 MI.addOperand(MCOperand::createImm(0)); 623 624 return MCDisassembler::Success; 625 } 626 627 template <typename InsnType> 628 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 629 const void *Decoder) { 630 InsnType Rs = fieldFromInstruction(insn, 16, 5); 631 InsnType Imm = fieldFromInstruction(insn, 0, 16); 632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 633 Rs))); 634 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 635 Rs))); 636 MI.addOperand(MCOperand::createImm(Imm)); 637 638 return MCDisassembler::Success; 639 } 640 641 template <typename InsnType> 642 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 643 const void *Decoder) { 644 InsnType Rs = fieldFromInstruction(insn, 21, 5); 645 InsnType Imm = fieldFromInstruction(insn, 0, 16); 646 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 647 Rs))); 648 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 649 Rs))); 650 MI.addOperand(MCOperand::createImm(Imm)); 651 652 return MCDisassembler::Success; 653 } 654 655 template <typename InsnType> 656 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 657 uint64_t Address, 658 const void *Decoder) { 659 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 660 // (otherwise we would have matched the ADDI instruction from the earlier 661 // ISA's instead). 662 // 663 // We have: 664 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 665 // BOVC if rs >= rt 666 // BEQZALC if rs == 0 && rt != 0 667 // BEQC if rs < rt && rs != 0 668 669 InsnType Rs = fieldFromInstruction(insn, 21, 5); 670 InsnType Rt = fieldFromInstruction(insn, 16, 5); 671 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 672 bool HasRs = false; 673 674 if (Rs >= Rt) { 675 MI.setOpcode(Mips::BOVC); 676 HasRs = true; 677 } else if (Rs != 0 && Rs < Rt) { 678 MI.setOpcode(Mips::BEQC); 679 HasRs = true; 680 } else 681 MI.setOpcode(Mips::BEQZALC); 682 683 if (HasRs) 684 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 685 Rs))); 686 687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 688 Rt))); 689 MI.addOperand(MCOperand::createImm(Imm)); 690 691 return MCDisassembler::Success; 692 } 693 694 template <typename InsnType> 695 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 696 uint64_t Address, 697 const void *Decoder) { 698 InsnType Rt = fieldFromInstruction(insn, 21, 5); 699 InsnType Rs = fieldFromInstruction(insn, 16, 5); 700 int64_t Imm = 0; 701 702 if (Rs >= Rt) { 703 MI.setOpcode(Mips::BOVC_MMR6); 704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 705 Rt))); 706 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 707 Rs))); 708 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 709 } else if (Rs != 0 && Rs < Rt) { 710 MI.setOpcode(Mips::BEQC_MMR6); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rs))); 713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 714 Rt))); 715 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 716 } else { 717 MI.setOpcode(Mips::BEQZALC_MMR6); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rt))); 720 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 721 } 722 723 MI.addOperand(MCOperand::createImm(Imm)); 724 725 return MCDisassembler::Success; 726 } 727 728 template <typename InsnType> 729 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 730 uint64_t Address, 731 const void *Decoder) { 732 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 733 // (otherwise we would have matched the ADDI instruction from the earlier 734 // ISA's instead). 735 // 736 // We have: 737 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 738 // BNVC if rs >= rt 739 // BNEZALC if rs == 0 && rt != 0 740 // BNEC if rs < rt && rs != 0 741 742 InsnType Rs = fieldFromInstruction(insn, 21, 5); 743 InsnType Rt = fieldFromInstruction(insn, 16, 5); 744 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 745 bool HasRs = false; 746 747 if (Rs >= Rt) { 748 MI.setOpcode(Mips::BNVC); 749 HasRs = true; 750 } else if (Rs != 0 && Rs < Rt) { 751 MI.setOpcode(Mips::BNEC); 752 HasRs = true; 753 } else 754 MI.setOpcode(Mips::BNEZALC); 755 756 if (HasRs) 757 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 758 Rs))); 759 760 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 761 Rt))); 762 MI.addOperand(MCOperand::createImm(Imm)); 763 764 return MCDisassembler::Success; 765 } 766 767 template <typename InsnType> 768 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 769 uint64_t Address, 770 const void *Decoder) { 771 InsnType Rt = fieldFromInstruction(insn, 21, 5); 772 InsnType Rs = fieldFromInstruction(insn, 16, 5); 773 int64_t Imm = 0; 774 775 if (Rs >= Rt) { 776 MI.setOpcode(Mips::BNVC_MMR6); 777 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 778 Rt))); 779 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 780 Rs))); 781 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 782 } else if (Rs != 0 && Rs < Rt) { 783 MI.setOpcode(Mips::BNEC_MMR6); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rs))); 786 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 787 Rt))); 788 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 789 } else { 790 MI.setOpcode(Mips::BNEZALC_MMR6); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rt))); 793 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 794 } 795 796 MI.addOperand(MCOperand::createImm(Imm)); 797 798 return MCDisassembler::Success; 799 } 800 801 template <typename InsnType> 802 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 803 uint64_t Address, 804 const void *Decoder) { 805 // We have: 806 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 807 // Invalid if rt == 0 808 // BGTZC_MMR6 if rs == 0 && rt != 0 809 // BLTZC_MMR6 if rs == rt && rt != 0 810 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 811 812 InsnType Rt = fieldFromInstruction(insn, 21, 5); 813 InsnType Rs = fieldFromInstruction(insn, 16, 5); 814 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 815 bool HasRs = false; 816 817 if (Rt == 0) 818 return MCDisassembler::Fail; 819 else if (Rs == 0) 820 MI.setOpcode(Mips::BGTZC_MMR6); 821 else if (Rs == Rt) 822 MI.setOpcode(Mips::BLTZC_MMR6); 823 else { 824 MI.setOpcode(Mips::BLTC_MMR6); 825 HasRs = true; 826 } 827 828 if (HasRs) 829 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 830 Rs))); 831 832 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 833 Rt))); 834 835 MI.addOperand(MCOperand::createImm(Imm)); 836 837 return MCDisassembler::Success; 838 } 839 840 template <typename InsnType> 841 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 842 uint64_t Address, 843 const void *Decoder) { 844 // We have: 845 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 846 // Invalid if rt == 0 847 // BLEZC_MMR6 if rs == 0 && rt != 0 848 // BGEZC_MMR6 if rs == rt && rt != 0 849 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 850 851 InsnType Rt = fieldFromInstruction(insn, 21, 5); 852 InsnType Rs = fieldFromInstruction(insn, 16, 5); 853 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 854 bool HasRs = false; 855 856 if (Rt == 0) 857 return MCDisassembler::Fail; 858 else if (Rs == 0) 859 MI.setOpcode(Mips::BLEZC_MMR6); 860 else if (Rs == Rt) 861 MI.setOpcode(Mips::BGEZC_MMR6); 862 else { 863 HasRs = true; 864 MI.setOpcode(Mips::BGEC_MMR6); 865 } 866 867 if (HasRs) 868 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 869 Rs))); 870 871 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 872 Rt))); 873 874 MI.addOperand(MCOperand::createImm(Imm)); 875 876 return MCDisassembler::Success; 877 } 878 879 template <typename InsnType> 880 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 881 uint64_t Address, 882 const void *Decoder) { 883 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 884 // (otherwise we would have matched the BLEZL instruction from the earlier 885 // ISA's instead). 886 // 887 // We have: 888 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 889 // Invalid if rs == 0 890 // BLEZC if rs == 0 && rt != 0 891 // BGEZC if rs == rt && rt != 0 892 // BGEC if rs != rt && rs != 0 && rt != 0 893 894 InsnType Rs = fieldFromInstruction(insn, 21, 5); 895 InsnType Rt = fieldFromInstruction(insn, 16, 5); 896 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 897 bool HasRs = false; 898 899 if (Rt == 0) 900 return MCDisassembler::Fail; 901 else if (Rs == 0) 902 MI.setOpcode(Mips::BLEZC); 903 else if (Rs == Rt) 904 MI.setOpcode(Mips::BGEZC); 905 else { 906 HasRs = true; 907 MI.setOpcode(Mips::BGEC); 908 } 909 910 if (HasRs) 911 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 912 Rs))); 913 914 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 915 Rt))); 916 917 MI.addOperand(MCOperand::createImm(Imm)); 918 919 return MCDisassembler::Success; 920 } 921 922 template <typename InsnType> 923 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 924 uint64_t Address, 925 const void *Decoder) { 926 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 927 // (otherwise we would have matched the BGTZL instruction from the earlier 928 // ISA's instead). 929 // 930 // We have: 931 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 932 // Invalid if rs == 0 933 // BGTZC if rs == 0 && rt != 0 934 // BLTZC if rs == rt && rt != 0 935 // BLTC if rs != rt && rs != 0 && rt != 0 936 937 bool HasRs = false; 938 939 InsnType Rs = fieldFromInstruction(insn, 21, 5); 940 InsnType Rt = fieldFromInstruction(insn, 16, 5); 941 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 942 943 if (Rt == 0) 944 return MCDisassembler::Fail; 945 else if (Rs == 0) 946 MI.setOpcode(Mips::BGTZC); 947 else if (Rs == Rt) 948 MI.setOpcode(Mips::BLTZC); 949 else { 950 MI.setOpcode(Mips::BLTC); 951 HasRs = true; 952 } 953 954 if (HasRs) 955 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 956 Rs))); 957 958 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 959 Rt))); 960 961 MI.addOperand(MCOperand::createImm(Imm)); 962 963 return MCDisassembler::Success; 964 } 965 966 template <typename InsnType> 967 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 968 uint64_t Address, 969 const void *Decoder) { 970 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 971 // (otherwise we would have matched the BGTZ instruction from the earlier 972 // ISA's instead). 973 // 974 // We have: 975 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 976 // BGTZ if rt == 0 977 // BGTZALC if rs == 0 && rt != 0 978 // BLTZALC if rs != 0 && rs == rt 979 // BLTUC if rs != 0 && rs != rt 980 981 InsnType Rs = fieldFromInstruction(insn, 21, 5); 982 InsnType Rt = fieldFromInstruction(insn, 16, 5); 983 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 984 bool HasRs = false; 985 bool HasRt = false; 986 987 if (Rt == 0) { 988 MI.setOpcode(Mips::BGTZ); 989 HasRs = true; 990 } else if (Rs == 0) { 991 MI.setOpcode(Mips::BGTZALC); 992 HasRt = true; 993 } else if (Rs == Rt) { 994 MI.setOpcode(Mips::BLTZALC); 995 HasRs = true; 996 } else { 997 MI.setOpcode(Mips::BLTUC); 998 HasRs = true; 999 HasRt = true; 1000 } 1001 1002 if (HasRs) 1003 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1004 Rs))); 1005 1006 if (HasRt) 1007 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1008 Rt))); 1009 1010 MI.addOperand(MCOperand::createImm(Imm)); 1011 1012 return MCDisassembler::Success; 1013 } 1014 1015 template <typename InsnType> 1016 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1017 uint64_t Address, 1018 const void *Decoder) { 1019 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1020 // (otherwise we would have matched the BLEZL instruction from the earlier 1021 // ISA's instead). 1022 // 1023 // We have: 1024 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1025 // Invalid if rs == 0 1026 // BLEZALC if rs == 0 && rt != 0 1027 // BGEZALC if rs == rt && rt != 0 1028 // BGEUC if rs != rt && rs != 0 && rt != 0 1029 1030 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1031 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1032 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1033 bool HasRs = false; 1034 1035 if (Rt == 0) 1036 return MCDisassembler::Fail; 1037 else if (Rs == 0) 1038 MI.setOpcode(Mips::BLEZALC); 1039 else if (Rs == Rt) 1040 MI.setOpcode(Mips::BGEZALC); 1041 else { 1042 HasRs = true; 1043 MI.setOpcode(Mips::BGEUC); 1044 } 1045 1046 if (HasRs) 1047 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1048 Rs))); 1049 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1050 Rt))); 1051 1052 MI.addOperand(MCOperand::createImm(Imm)); 1053 1054 return MCDisassembler::Success; 1055 } 1056 1057 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1058 /// according to the given endianness. 1059 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1060 uint64_t &Size, uint32_t &Insn, 1061 bool IsBigEndian) { 1062 // We want to read exactly 2 Bytes of data. 1063 if (Bytes.size() < 2) { 1064 Size = 0; 1065 return MCDisassembler::Fail; 1066 } 1067 1068 if (IsBigEndian) { 1069 Insn = (Bytes[0] << 8) | Bytes[1]; 1070 } else { 1071 Insn = (Bytes[1] << 8) | Bytes[0]; 1072 } 1073 1074 return MCDisassembler::Success; 1075 } 1076 1077 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1078 /// according to the given endianness. 1079 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1080 uint64_t &Size, uint32_t &Insn, 1081 bool IsBigEndian, bool IsMicroMips) { 1082 // We want to read exactly 4 Bytes of data. 1083 if (Bytes.size() < 4) { 1084 Size = 0; 1085 return MCDisassembler::Fail; 1086 } 1087 1088 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1089 // always precede the low 16 bits in the instruction stream (that is, they 1090 // are placed at lower addresses in the instruction stream). 1091 // 1092 // microMIPS byte ordering: 1093 // Big-endian: 0 | 1 | 2 | 3 1094 // Little-endian: 1 | 0 | 3 | 2 1095 1096 if (IsBigEndian) { 1097 // Encoded as a big-endian 32-bit word in the stream. 1098 Insn = 1099 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1100 } else { 1101 if (IsMicroMips) { 1102 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1103 (Bytes[1] << 24); 1104 } else { 1105 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1106 (Bytes[3] << 24); 1107 } 1108 } 1109 1110 return MCDisassembler::Success; 1111 } 1112 1113 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1114 ArrayRef<uint8_t> Bytes, 1115 uint64_t Address, 1116 raw_ostream &VStream, 1117 raw_ostream &CStream) const { 1118 uint32_t Insn; 1119 DecodeStatus Result; 1120 1121 if (IsMicroMips) { 1122 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1123 if (Result == MCDisassembler::Fail) 1124 return MCDisassembler::Fail; 1125 1126 if (hasMips32r6()) { 1127 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1128 // Calling the auto-generated decoder function for microMIPS32R6 1129 // (and microMIPS64R6) 16-bit instructions. 1130 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1131 Address, this, STI); 1132 if (Result != MCDisassembler::Fail) { 1133 Size = 2; 1134 return Result; 1135 } 1136 } 1137 1138 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1139 // Calling the auto-generated decoder function for microMIPS 16-bit 1140 // instructions. 1141 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1142 this, STI); 1143 if (Result != MCDisassembler::Fail) { 1144 Size = 2; 1145 return Result; 1146 } 1147 1148 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1149 if (Result == MCDisassembler::Fail) 1150 return MCDisassembler::Fail; 1151 1152 if (hasMips32r6()) { 1153 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1154 // Calling the auto-generated decoder function. 1155 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1156 this, STI); 1157 if (Result != MCDisassembler::Fail) { 1158 Size = 4; 1159 return Result; 1160 } 1161 } 1162 1163 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1164 // Calling the auto-generated decoder function. 1165 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1166 this, STI); 1167 if (Result != MCDisassembler::Fail) { 1168 Size = 4; 1169 return Result; 1170 } 1171 1172 if (hasMips32r6() && isFP64()) { 1173 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 1174 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 1175 Address, this, STI); 1176 if (Result != MCDisassembler::Fail) { 1177 Size = 4; 1178 return Result; 1179 } 1180 } 1181 1182 // This is an invalid instruction. Let the disassembler move forward by the 1183 // minimum instruction size. 1184 Size = 2; 1185 return MCDisassembler::Fail; 1186 } 1187 1188 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1189 if (Result == MCDisassembler::Fail) { 1190 Size = 4; 1191 return MCDisassembler::Fail; 1192 } 1193 1194 if (hasCOP3()) { 1195 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1196 Result = 1197 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1198 if (Result != MCDisassembler::Fail) { 1199 Size = 4; 1200 return Result; 1201 } 1202 } 1203 1204 if (hasMips32r6() && isGP64()) { 1205 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1206 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1207 Address, this, STI); 1208 if (Result != MCDisassembler::Fail) { 1209 Size = 4; 1210 return Result; 1211 } 1212 } 1213 1214 if (hasMips32r6() && isPTR64()) { 1215 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1216 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1217 Address, this, STI); 1218 if (Result != MCDisassembler::Fail) { 1219 Size = 4; 1220 return Result; 1221 } 1222 } 1223 1224 if (hasMips32r6()) { 1225 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1226 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1227 Address, this, STI); 1228 if (Result != MCDisassembler::Fail) { 1229 Size = 4; 1230 return Result; 1231 } 1232 } 1233 1234 if (hasMips2() && isPTR64()) { 1235 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1236 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1237 Address, this, STI); 1238 if (Result != MCDisassembler::Fail) { 1239 Size = 4; 1240 return Result; 1241 } 1242 } 1243 1244 if (hasCnMips()) { 1245 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1246 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1247 Address, this, STI); 1248 if (Result != MCDisassembler::Fail) { 1249 Size = 4; 1250 return Result; 1251 } 1252 } 1253 1254 if (isGP64()) { 1255 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1256 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1257 Address, this, STI); 1258 if (Result != MCDisassembler::Fail) { 1259 Size = 4; 1260 return Result; 1261 } 1262 } 1263 1264 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1265 // Calling the auto-generated decoder function. 1266 Result = 1267 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1268 if (Result != MCDisassembler::Fail) { 1269 Size = 4; 1270 return Result; 1271 } 1272 1273 Size = 4; 1274 return MCDisassembler::Fail; 1275 } 1276 1277 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1278 unsigned RegNo, 1279 uint64_t Address, 1280 const void *Decoder) { 1281 return MCDisassembler::Fail; 1282 } 1283 1284 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1285 unsigned RegNo, 1286 uint64_t Address, 1287 const void *Decoder) { 1288 if (RegNo > 31) 1289 return MCDisassembler::Fail; 1290 1291 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1292 Inst.addOperand(MCOperand::createReg(Reg)); 1293 return MCDisassembler::Success; 1294 } 1295 1296 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1297 unsigned RegNo, 1298 uint64_t Address, 1299 const void *Decoder) { 1300 if (RegNo > 7) 1301 return MCDisassembler::Fail; 1302 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1303 Inst.addOperand(MCOperand::createReg(Reg)); 1304 return MCDisassembler::Success; 1305 } 1306 1307 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1308 unsigned RegNo, 1309 uint64_t Address, 1310 const void *Decoder) { 1311 if (RegNo > 7) 1312 return MCDisassembler::Fail; 1313 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1314 Inst.addOperand(MCOperand::createReg(Reg)); 1315 return MCDisassembler::Success; 1316 } 1317 1318 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1319 unsigned RegNo, 1320 uint64_t Address, 1321 const void *Decoder) { 1322 if (RegNo > 7) 1323 return MCDisassembler::Fail; 1324 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1325 Inst.addOperand(MCOperand::createReg(Reg)); 1326 return MCDisassembler::Success; 1327 } 1328 1329 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1330 unsigned RegNo, 1331 uint64_t Address, 1332 const void *Decoder) { 1333 if (RegNo > 31) 1334 return MCDisassembler::Fail; 1335 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1336 Inst.addOperand(MCOperand::createReg(Reg)); 1337 return MCDisassembler::Success; 1338 } 1339 1340 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1341 unsigned RegNo, 1342 uint64_t Address, 1343 const void *Decoder) { 1344 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1345 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1346 1347 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1348 } 1349 1350 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1351 unsigned RegNo, 1352 uint64_t Address, 1353 const void *Decoder) { 1354 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1355 } 1356 1357 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1358 unsigned RegNo, 1359 uint64_t Address, 1360 const void *Decoder) { 1361 if (RegNo > 31) 1362 return MCDisassembler::Fail; 1363 1364 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1365 Inst.addOperand(MCOperand::createReg(Reg)); 1366 return MCDisassembler::Success; 1367 } 1368 1369 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1370 unsigned RegNo, 1371 uint64_t Address, 1372 const void *Decoder) { 1373 if (RegNo > 31) 1374 return MCDisassembler::Fail; 1375 1376 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1377 Inst.addOperand(MCOperand::createReg(Reg)); 1378 return MCDisassembler::Success; 1379 } 1380 1381 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1382 unsigned RegNo, 1383 uint64_t Address, 1384 const void *Decoder) { 1385 if (RegNo > 31) 1386 return MCDisassembler::Fail; 1387 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1388 Inst.addOperand(MCOperand::createReg(Reg)); 1389 return MCDisassembler::Success; 1390 } 1391 1392 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1393 unsigned RegNo, 1394 uint64_t Address, 1395 const void *Decoder) { 1396 if (RegNo > 7) 1397 return MCDisassembler::Fail; 1398 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1399 Inst.addOperand(MCOperand::createReg(Reg)); 1400 return MCDisassembler::Success; 1401 } 1402 1403 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1404 uint64_t Address, 1405 const void *Decoder) { 1406 if (RegNo > 31) 1407 return MCDisassembler::Fail; 1408 1409 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1410 Inst.addOperand(MCOperand::createReg(Reg)); 1411 return MCDisassembler::Success; 1412 } 1413 1414 static DecodeStatus DecodeMem(MCInst &Inst, 1415 unsigned Insn, 1416 uint64_t Address, 1417 const void *Decoder) { 1418 int Offset = SignExtend32<16>(Insn & 0xffff); 1419 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1420 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1421 1422 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1423 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1424 1425 if (Inst.getOpcode() == Mips::SC || 1426 Inst.getOpcode() == Mips::SCD) 1427 Inst.addOperand(MCOperand::createReg(Reg)); 1428 1429 Inst.addOperand(MCOperand::createReg(Reg)); 1430 Inst.addOperand(MCOperand::createReg(Base)); 1431 Inst.addOperand(MCOperand::createImm(Offset)); 1432 1433 return MCDisassembler::Success; 1434 } 1435 1436 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1437 unsigned Insn, 1438 uint64_t Address, 1439 const void *Decoder) { 1440 int Offset = SignExtend32<9>(Insn >> 7); 1441 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1442 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1443 1444 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1445 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1446 1447 if (Inst.getOpcode() == Mips::SCE) 1448 Inst.addOperand(MCOperand::createReg(Reg)); 1449 1450 Inst.addOperand(MCOperand::createReg(Reg)); 1451 Inst.addOperand(MCOperand::createReg(Base)); 1452 Inst.addOperand(MCOperand::createImm(Offset)); 1453 1454 return MCDisassembler::Success; 1455 } 1456 1457 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1458 unsigned Insn, 1459 uint64_t Address, 1460 const void *Decoder) { 1461 int Offset = SignExtend32<9>(Insn & 0x1ff); 1462 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1463 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1464 1465 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1466 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1467 1468 Inst.addOperand(MCOperand::createReg(Reg)); 1469 Inst.addOperand(MCOperand::createReg(Base)); 1470 Inst.addOperand(MCOperand::createImm(Offset)); 1471 1472 return MCDisassembler::Success; 1473 } 1474 1475 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1476 unsigned Insn, 1477 uint64_t Address, 1478 const void *Decoder) { 1479 int Offset = SignExtend32<16>(Insn & 0xffff); 1480 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1481 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1482 1483 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1484 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1485 1486 Inst.addOperand(MCOperand::createReg(Reg)); 1487 Inst.addOperand(MCOperand::createReg(Base)); 1488 Inst.addOperand(MCOperand::createImm(Offset)); 1489 1490 return MCDisassembler::Success; 1491 } 1492 1493 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1494 unsigned Insn, 1495 uint64_t Address, 1496 const void *Decoder) { 1497 int Offset = SignExtend32<16>(Insn & 0xffff); 1498 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1499 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1500 1501 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1502 1503 Inst.addOperand(MCOperand::createReg(Base)); 1504 Inst.addOperand(MCOperand::createImm(Offset)); 1505 Inst.addOperand(MCOperand::createImm(Hint)); 1506 1507 return MCDisassembler::Success; 1508 } 1509 1510 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1511 unsigned Insn, 1512 uint64_t Address, 1513 const void *Decoder) { 1514 int Offset = SignExtend32<12>(Insn & 0xfff); 1515 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1516 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1517 1518 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1519 1520 Inst.addOperand(MCOperand::createReg(Base)); 1521 Inst.addOperand(MCOperand::createImm(Offset)); 1522 Inst.addOperand(MCOperand::createImm(Hint)); 1523 1524 return MCDisassembler::Success; 1525 } 1526 1527 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1528 unsigned Insn, 1529 uint64_t Address, 1530 const void *Decoder) { 1531 int Offset = SignExtend32<9>(Insn & 0x1ff); 1532 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1533 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1534 1535 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1536 1537 Inst.addOperand(MCOperand::createReg(Base)); 1538 Inst.addOperand(MCOperand::createImm(Offset)); 1539 Inst.addOperand(MCOperand::createImm(Hint)); 1540 1541 return MCDisassembler::Success; 1542 } 1543 1544 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1545 unsigned Insn, 1546 uint64_t Address, 1547 const void *Decoder) { 1548 int Offset = SignExtend32<9>(Insn >> 7); 1549 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1550 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1551 1552 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1553 1554 Inst.addOperand(MCOperand::createReg(Base)); 1555 Inst.addOperand(MCOperand::createImm(Offset)); 1556 Inst.addOperand(MCOperand::createImm(Hint)); 1557 1558 return MCDisassembler::Success; 1559 } 1560 1561 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1562 unsigned Insn, 1563 uint64_t Address, 1564 const void *Decoder) { 1565 int Offset = SignExtend32<9>(Insn & 0x1ff); 1566 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1567 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1568 1569 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1570 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1571 1572 Inst.addOperand(MCOperand::createReg(Reg)); 1573 Inst.addOperand(MCOperand::createReg(Base)); 1574 Inst.addOperand(MCOperand::createImm(Offset)); 1575 1576 return MCDisassembler::Success; 1577 } 1578 1579 static DecodeStatus DecodeSyncI(MCInst &Inst, 1580 unsigned Insn, 1581 uint64_t Address, 1582 const void *Decoder) { 1583 int Offset = SignExtend32<16>(Insn & 0xffff); 1584 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1585 1586 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1587 1588 Inst.addOperand(MCOperand::createReg(Base)); 1589 Inst.addOperand(MCOperand::createImm(Offset)); 1590 1591 return MCDisassembler::Success; 1592 } 1593 1594 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1595 unsigned Insn, 1596 uint64_t Address, 1597 const void *Decoder) { 1598 int Immediate = SignExtend32<16>(Insn & 0xffff); 1599 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1600 1601 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1602 1603 Inst.addOperand(MCOperand::createReg(Base)); 1604 Inst.addOperand(MCOperand::createImm(Immediate)); 1605 1606 return MCDisassembler::Success; 1607 } 1608 1609 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1610 uint64_t Address, const void *Decoder) { 1611 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1612 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1613 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1614 1615 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1616 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1617 1618 Inst.addOperand(MCOperand::createReg(Reg)); 1619 Inst.addOperand(MCOperand::createReg(Base)); 1620 1621 // The immediate field of an LD/ST instruction is scaled which means it must 1622 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1623 // data format. 1624 // .b - 1 byte 1625 // .h - 2 bytes 1626 // .w - 4 bytes 1627 // .d - 8 bytes 1628 switch(Inst.getOpcode()) 1629 { 1630 default: 1631 assert(false && "Unexpected instruction"); 1632 return MCDisassembler::Fail; 1633 break; 1634 case Mips::LD_B: 1635 case Mips::ST_B: 1636 Inst.addOperand(MCOperand::createImm(Offset)); 1637 break; 1638 case Mips::LD_H: 1639 case Mips::ST_H: 1640 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1641 break; 1642 case Mips::LD_W: 1643 case Mips::ST_W: 1644 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1645 break; 1646 case Mips::LD_D: 1647 case Mips::ST_D: 1648 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1649 break; 1650 } 1651 1652 return MCDisassembler::Success; 1653 } 1654 1655 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1656 unsigned Insn, 1657 uint64_t Address, 1658 const void *Decoder) { 1659 unsigned Offset = Insn & 0xf; 1660 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1661 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1662 1663 switch (Inst.getOpcode()) { 1664 case Mips::LBU16_MM: 1665 case Mips::LHU16_MM: 1666 case Mips::LW16_MM: 1667 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1668 == MCDisassembler::Fail) 1669 return MCDisassembler::Fail; 1670 break; 1671 case Mips::SB16_MM: 1672 case Mips::SB16_MMR6: 1673 case Mips::SH16_MM: 1674 case Mips::SH16_MMR6: 1675 case Mips::SW16_MM: 1676 case Mips::SW16_MMR6: 1677 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1678 == MCDisassembler::Fail) 1679 return MCDisassembler::Fail; 1680 break; 1681 } 1682 1683 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1684 == MCDisassembler::Fail) 1685 return MCDisassembler::Fail; 1686 1687 switch (Inst.getOpcode()) { 1688 case Mips::LBU16_MM: 1689 if (Offset == 0xf) 1690 Inst.addOperand(MCOperand::createImm(-1)); 1691 else 1692 Inst.addOperand(MCOperand::createImm(Offset)); 1693 break; 1694 case Mips::SB16_MM: 1695 case Mips::SB16_MMR6: 1696 Inst.addOperand(MCOperand::createImm(Offset)); 1697 break; 1698 case Mips::LHU16_MM: 1699 case Mips::SH16_MM: 1700 case Mips::SH16_MMR6: 1701 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1702 break; 1703 case Mips::LW16_MM: 1704 case Mips::SW16_MM: 1705 case Mips::SW16_MMR6: 1706 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1707 break; 1708 } 1709 1710 return MCDisassembler::Success; 1711 } 1712 1713 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1714 unsigned Insn, 1715 uint64_t Address, 1716 const void *Decoder) { 1717 unsigned Offset = Insn & 0x1F; 1718 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1719 1720 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1721 1722 Inst.addOperand(MCOperand::createReg(Reg)); 1723 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1724 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1725 1726 return MCDisassembler::Success; 1727 } 1728 1729 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1730 unsigned Insn, 1731 uint64_t Address, 1732 const void *Decoder) { 1733 unsigned Offset = Insn & 0x7F; 1734 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1735 1736 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1737 1738 Inst.addOperand(MCOperand::createReg(Reg)); 1739 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1740 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1741 1742 return MCDisassembler::Success; 1743 } 1744 1745 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1746 unsigned Insn, 1747 uint64_t Address, 1748 const void *Decoder) { 1749 int Offset; 1750 switch (Inst.getOpcode()) { 1751 case Mips::LWM16_MMR6: 1752 case Mips::SWM16_MMR6: 1753 Offset = fieldFromInstruction(Insn, 4, 4); 1754 break; 1755 default: 1756 Offset = SignExtend32<4>(Insn & 0xf); 1757 break; 1758 } 1759 1760 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1761 == MCDisassembler::Fail) 1762 return MCDisassembler::Fail; 1763 1764 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1765 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1766 1767 return MCDisassembler::Success; 1768 } 1769 1770 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1771 unsigned Insn, 1772 uint64_t Address, 1773 const void *Decoder) { 1774 int Offset = SignExtend32<9>(Insn & 0x1ff); 1775 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1776 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1777 1778 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1779 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1780 1781 if (Inst.getOpcode() == Mips::SCE_MM) 1782 Inst.addOperand(MCOperand::createReg(Reg)); 1783 1784 Inst.addOperand(MCOperand::createReg(Reg)); 1785 Inst.addOperand(MCOperand::createReg(Base)); 1786 Inst.addOperand(MCOperand::createImm(Offset)); 1787 1788 return MCDisassembler::Success; 1789 } 1790 1791 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1792 unsigned Insn, 1793 uint64_t Address, 1794 const void *Decoder) { 1795 int Offset = SignExtend32<12>(Insn & 0x0fff); 1796 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1797 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1798 1799 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1800 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1801 1802 switch (Inst.getOpcode()) { 1803 case Mips::SWM32_MM: 1804 case Mips::LWM32_MM: 1805 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1806 == MCDisassembler::Fail) 1807 return MCDisassembler::Fail; 1808 Inst.addOperand(MCOperand::createReg(Base)); 1809 Inst.addOperand(MCOperand::createImm(Offset)); 1810 break; 1811 case Mips::SC_MM: 1812 Inst.addOperand(MCOperand::createReg(Reg)); 1813 LLVM_FALLTHROUGH; 1814 default: 1815 Inst.addOperand(MCOperand::createReg(Reg)); 1816 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1817 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1818 Inst.addOperand(MCOperand::createReg(Reg+1)); 1819 1820 Inst.addOperand(MCOperand::createReg(Base)); 1821 Inst.addOperand(MCOperand::createImm(Offset)); 1822 } 1823 1824 return MCDisassembler::Success; 1825 } 1826 1827 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1828 unsigned Insn, 1829 uint64_t Address, 1830 const void *Decoder) { 1831 int Offset = SignExtend32<16>(Insn & 0xffff); 1832 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1833 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1834 1835 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1836 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1837 1838 Inst.addOperand(MCOperand::createReg(Reg)); 1839 Inst.addOperand(MCOperand::createReg(Base)); 1840 Inst.addOperand(MCOperand::createImm(Offset)); 1841 1842 return MCDisassembler::Success; 1843 } 1844 1845 static DecodeStatus DecodeFMem(MCInst &Inst, 1846 unsigned Insn, 1847 uint64_t Address, 1848 const void *Decoder) { 1849 int Offset = SignExtend32<16>(Insn & 0xffff); 1850 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1851 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1852 1853 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1854 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1855 1856 Inst.addOperand(MCOperand::createReg(Reg)); 1857 Inst.addOperand(MCOperand::createReg(Base)); 1858 Inst.addOperand(MCOperand::createImm(Offset)); 1859 1860 return MCDisassembler::Success; 1861 } 1862 1863 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1864 uint64_t Address, const void *Decoder) { 1865 // This function is the same as DecodeFMem but with the Reg and Base fields 1866 // swapped according to microMIPS spec. 1867 int Offset = SignExtend32<16>(Insn & 0xffff); 1868 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1869 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1870 1871 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1872 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1873 1874 Inst.addOperand(MCOperand::createReg(Reg)); 1875 Inst.addOperand(MCOperand::createReg(Base)); 1876 Inst.addOperand(MCOperand::createImm(Offset)); 1877 1878 return MCDisassembler::Success; 1879 } 1880 1881 static DecodeStatus DecodeFMem2(MCInst &Inst, 1882 unsigned Insn, 1883 uint64_t Address, 1884 const void *Decoder) { 1885 int Offset = SignExtend32<16>(Insn & 0xffff); 1886 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1887 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1888 1889 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1890 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1891 1892 Inst.addOperand(MCOperand::createReg(Reg)); 1893 Inst.addOperand(MCOperand::createReg(Base)); 1894 Inst.addOperand(MCOperand::createImm(Offset)); 1895 1896 return MCDisassembler::Success; 1897 } 1898 1899 static DecodeStatus DecodeFMem3(MCInst &Inst, 1900 unsigned Insn, 1901 uint64_t Address, 1902 const void *Decoder) { 1903 int Offset = SignExtend32<16>(Insn & 0xffff); 1904 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1905 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1906 1907 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1908 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1909 1910 Inst.addOperand(MCOperand::createReg(Reg)); 1911 Inst.addOperand(MCOperand::createReg(Base)); 1912 Inst.addOperand(MCOperand::createImm(Offset)); 1913 1914 return MCDisassembler::Success; 1915 } 1916 1917 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1918 unsigned Insn, 1919 uint64_t Address, 1920 const void *Decoder) { 1921 int Offset = SignExtend32<11>(Insn & 0x07ff); 1922 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1923 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1924 1925 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1926 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1927 1928 Inst.addOperand(MCOperand::createReg(Reg)); 1929 Inst.addOperand(MCOperand::createReg(Base)); 1930 Inst.addOperand(MCOperand::createImm(Offset)); 1931 1932 return MCDisassembler::Success; 1933 } 1934 1935 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1936 uint64_t Address, const void *Decoder) { 1937 int Offset = SignExtend32<11>(Insn & 0x07ff); 1938 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1939 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1940 1941 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1942 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1943 1944 Inst.addOperand(MCOperand::createReg(Reg)); 1945 Inst.addOperand(MCOperand::createReg(Base)); 1946 Inst.addOperand(MCOperand::createImm(Offset)); 1947 1948 return MCDisassembler::Success; 1949 } 1950 1951 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1952 unsigned Insn, 1953 uint64_t Address, 1954 const void *Decoder) { 1955 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1956 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1957 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1958 1959 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1960 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1961 1962 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1963 Inst.addOperand(MCOperand::createReg(Rt)); 1964 } 1965 1966 Inst.addOperand(MCOperand::createReg(Rt)); 1967 Inst.addOperand(MCOperand::createReg(Base)); 1968 Inst.addOperand(MCOperand::createImm(Offset)); 1969 1970 return MCDisassembler::Success; 1971 } 1972 1973 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1974 unsigned RegNo, 1975 uint64_t Address, 1976 const void *Decoder) { 1977 // Currently only hardware register 29 is supported. 1978 if (RegNo != 29) 1979 return MCDisassembler::Fail; 1980 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1981 return MCDisassembler::Success; 1982 } 1983 1984 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1985 unsigned RegNo, 1986 uint64_t Address, 1987 const void *Decoder) { 1988 if (RegNo > 30 || RegNo %2) 1989 return MCDisassembler::Fail; 1990 1991 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1992 Inst.addOperand(MCOperand::createReg(Reg)); 1993 return MCDisassembler::Success; 1994 } 1995 1996 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1997 unsigned RegNo, 1998 uint64_t Address, 1999 const void *Decoder) { 2000 if (RegNo >= 4) 2001 return MCDisassembler::Fail; 2002 2003 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2004 Inst.addOperand(MCOperand::createReg(Reg)); 2005 return MCDisassembler::Success; 2006 } 2007 2008 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2009 unsigned RegNo, 2010 uint64_t Address, 2011 const void *Decoder) { 2012 if (RegNo >= 4) 2013 return MCDisassembler::Fail; 2014 2015 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2016 Inst.addOperand(MCOperand::createReg(Reg)); 2017 return MCDisassembler::Success; 2018 } 2019 2020 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2021 unsigned RegNo, 2022 uint64_t Address, 2023 const void *Decoder) { 2024 if (RegNo >= 4) 2025 return MCDisassembler::Fail; 2026 2027 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2028 Inst.addOperand(MCOperand::createReg(Reg)); 2029 return MCDisassembler::Success; 2030 } 2031 2032 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2033 unsigned RegNo, 2034 uint64_t Address, 2035 const void *Decoder) { 2036 if (RegNo > 31) 2037 return MCDisassembler::Fail; 2038 2039 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2040 Inst.addOperand(MCOperand::createReg(Reg)); 2041 return MCDisassembler::Success; 2042 } 2043 2044 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2045 unsigned RegNo, 2046 uint64_t Address, 2047 const void *Decoder) { 2048 if (RegNo > 31) 2049 return MCDisassembler::Fail; 2050 2051 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2052 Inst.addOperand(MCOperand::createReg(Reg)); 2053 return MCDisassembler::Success; 2054 } 2055 2056 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2057 unsigned RegNo, 2058 uint64_t Address, 2059 const void *Decoder) { 2060 if (RegNo > 31) 2061 return MCDisassembler::Fail; 2062 2063 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2064 Inst.addOperand(MCOperand::createReg(Reg)); 2065 return MCDisassembler::Success; 2066 } 2067 2068 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2069 unsigned RegNo, 2070 uint64_t Address, 2071 const void *Decoder) { 2072 if (RegNo > 31) 2073 return MCDisassembler::Fail; 2074 2075 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2076 Inst.addOperand(MCOperand::createReg(Reg)); 2077 return MCDisassembler::Success; 2078 } 2079 2080 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2081 unsigned RegNo, 2082 uint64_t Address, 2083 const void *Decoder) { 2084 if (RegNo > 7) 2085 return MCDisassembler::Fail; 2086 2087 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2088 Inst.addOperand(MCOperand::createReg(Reg)); 2089 return MCDisassembler::Success; 2090 } 2091 2092 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2093 unsigned RegNo, 2094 uint64_t Address, 2095 const void *Decoder) { 2096 if (RegNo > 31) 2097 return MCDisassembler::Fail; 2098 2099 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2100 Inst.addOperand(MCOperand::createReg(Reg)); 2101 return MCDisassembler::Success; 2102 } 2103 2104 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2105 unsigned RegNo, 2106 uint64_t Address, 2107 const void *Decoder) { 2108 if (RegNo > 31) 2109 return MCDisassembler::Fail; 2110 2111 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2112 Inst.addOperand(MCOperand::createReg(Reg)); 2113 return MCDisassembler::Success; 2114 } 2115 2116 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2117 unsigned Offset, 2118 uint64_t Address, 2119 const void *Decoder) { 2120 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2121 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2122 return MCDisassembler::Success; 2123 } 2124 2125 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2126 unsigned Offset, 2127 uint64_t Address, 2128 const void *Decoder) { 2129 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2130 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2131 return MCDisassembler::Success; 2132 } 2133 2134 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2135 unsigned Insn, 2136 uint64_t Address, 2137 const void *Decoder) { 2138 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2139 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2140 return MCDisassembler::Success; 2141 } 2142 2143 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2144 unsigned Offset, 2145 uint64_t Address, 2146 const void *Decoder) { 2147 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2148 2149 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2150 return MCDisassembler::Success; 2151 } 2152 2153 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2154 unsigned Offset, 2155 uint64_t Address, 2156 const void *Decoder) { 2157 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2158 2159 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2160 return MCDisassembler::Success; 2161 } 2162 2163 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2164 unsigned Offset, 2165 uint64_t Address, 2166 const void *Decoder) { 2167 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2168 2169 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2170 return MCDisassembler::Success; 2171 } 2172 2173 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2174 unsigned Offset, 2175 uint64_t Address, 2176 const void *Decoder) { 2177 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 2178 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2179 return MCDisassembler::Success; 2180 } 2181 2182 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2183 unsigned Offset, 2184 uint64_t Address, 2185 const void *Decoder) { 2186 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 2187 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2188 return MCDisassembler::Success; 2189 } 2190 2191 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2192 unsigned Offset, 2193 uint64_t Address, 2194 const void *Decoder) { 2195 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2196 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2197 return MCDisassembler::Success; 2198 } 2199 2200 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2201 unsigned Offset, 2202 uint64_t Address, 2203 const void *Decoder) { 2204 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 2205 2206 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2207 return MCDisassembler::Success; 2208 } 2209 2210 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2211 unsigned Insn, 2212 uint64_t Address, 2213 const void *Decoder) { 2214 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2215 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2216 return MCDisassembler::Success; 2217 } 2218 2219 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2220 unsigned Value, 2221 uint64_t Address, 2222 const void *Decoder) { 2223 if (Value == 0) 2224 Inst.addOperand(MCOperand::createImm(1)); 2225 else if (Value == 0x7) 2226 Inst.addOperand(MCOperand::createImm(-1)); 2227 else 2228 Inst.addOperand(MCOperand::createImm(Value << 2)); 2229 return MCDisassembler::Success; 2230 } 2231 2232 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2233 unsigned Value, 2234 uint64_t Address, 2235 const void *Decoder) { 2236 if (Value == 0x7F) 2237 Inst.addOperand(MCOperand::createImm(-1)); 2238 else 2239 Inst.addOperand(MCOperand::createImm(Value)); 2240 return MCDisassembler::Success; 2241 } 2242 2243 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2244 unsigned Value, 2245 uint64_t Address, 2246 const void *Decoder) { 2247 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2248 return MCDisassembler::Success; 2249 } 2250 2251 template <unsigned Bits, int Offset, int Scale> 2252 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2253 uint64_t Address, 2254 const void *Decoder) { 2255 Value &= ((1 << Bits) - 1); 2256 Value *= Scale; 2257 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2258 return MCDisassembler::Success; 2259 } 2260 2261 template <unsigned Bits, int Offset, int ScaleBy> 2262 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2263 uint64_t Address, 2264 const void *Decoder) { 2265 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2266 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2267 return MCDisassembler::Success; 2268 } 2269 2270 static DecodeStatus DecodeInsSize(MCInst &Inst, 2271 unsigned Insn, 2272 uint64_t Address, 2273 const void *Decoder) { 2274 // First we need to grab the pos(lsb) from MCInst. 2275 int Pos = Inst.getOperand(2).getImm(); 2276 int Size = (int) Insn - Pos + 1; 2277 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2278 return MCDisassembler::Success; 2279 } 2280 2281 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2282 uint64_t Address, const void *Decoder) { 2283 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2284 return MCDisassembler::Success; 2285 } 2286 2287 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2288 uint64_t Address, const void *Decoder) { 2289 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2290 return MCDisassembler::Success; 2291 } 2292 2293 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2294 uint64_t Address, const void *Decoder) { 2295 int32_t DecodedValue; 2296 switch (Insn) { 2297 case 0: DecodedValue = 256; break; 2298 case 1: DecodedValue = 257; break; 2299 case 510: DecodedValue = -258; break; 2300 case 511: DecodedValue = -257; break; 2301 default: DecodedValue = SignExtend32<9>(Insn); break; 2302 } 2303 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2304 return MCDisassembler::Success; 2305 } 2306 2307 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2308 uint64_t Address, const void *Decoder) { 2309 // Insn must be >= 0, since it is unsigned that condition is always true. 2310 assert(Insn < 16); 2311 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2312 255, 32768, 65535}; 2313 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2314 return MCDisassembler::Success; 2315 } 2316 2317 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2318 unsigned Insn, 2319 uint64_t Address, 2320 const void *Decoder) { 2321 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2322 Mips::S6, Mips::S7, Mips::FP}; 2323 unsigned RegNum; 2324 2325 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2326 2327 // Empty register lists are not allowed. 2328 if (RegLst == 0) 2329 return MCDisassembler::Fail; 2330 2331 RegNum = RegLst & 0xf; 2332 2333 // RegLst values 10-15, and 26-31 are reserved. 2334 if (RegNum > 9) 2335 return MCDisassembler::Fail; 2336 2337 for (unsigned i = 0; i < RegNum; i++) 2338 Inst.addOperand(MCOperand::createReg(Regs[i])); 2339 2340 if (RegLst & 0x10) 2341 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2342 2343 return MCDisassembler::Success; 2344 } 2345 2346 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2347 uint64_t Address, 2348 const void *Decoder) { 2349 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2350 unsigned RegLst; 2351 switch(Inst.getOpcode()) { 2352 default: 2353 RegLst = fieldFromInstruction(Insn, 4, 2); 2354 break; 2355 case Mips::LWM16_MMR6: 2356 case Mips::SWM16_MMR6: 2357 RegLst = fieldFromInstruction(Insn, 8, 2); 2358 break; 2359 } 2360 unsigned RegNum = RegLst & 0x3; 2361 2362 for (unsigned i = 0; i <= RegNum; i++) 2363 Inst.addOperand(MCOperand::createReg(Regs[i])); 2364 2365 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2366 2367 return MCDisassembler::Success; 2368 } 2369 2370 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2371 uint64_t Address, const void *Decoder) { 2372 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2373 2374 switch (RegPair) { 2375 default: 2376 return MCDisassembler::Fail; 2377 case 0: 2378 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2379 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2380 break; 2381 case 1: 2382 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2383 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2384 break; 2385 case 2: 2386 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2387 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2388 break; 2389 case 3: 2390 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2391 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2392 break; 2393 case 4: 2394 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2395 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2396 break; 2397 case 5: 2398 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2399 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2400 break; 2401 case 6: 2402 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2403 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2404 break; 2405 case 7: 2406 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2407 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2408 break; 2409 } 2410 2411 return MCDisassembler::Success; 2412 } 2413 2414 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2415 uint64_t Address, const void *Decoder) { 2416 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2417 return MCDisassembler::Success; 2418 } 2419 2420 template <typename InsnType> 2421 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2422 uint64_t Address, 2423 const void *Decoder) { 2424 // We have: 2425 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2426 // Invalid if rt == 0 2427 // BGTZALC_MMR6 if rs == 0 && rt != 0 2428 // BLTZALC_MMR6 if rs != 0 && rs == rt 2429 // BLTUC_MMR6 if rs != 0 && rs != rt 2430 2431 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2432 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2433 InsnType Imm = 0; 2434 bool HasRs = false; 2435 bool HasRt = false; 2436 2437 if (Rt == 0) 2438 return MCDisassembler::Fail; 2439 else if (Rs == 0) { 2440 MI.setOpcode(Mips::BGTZALC_MMR6); 2441 HasRt = true; 2442 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2443 } 2444 else if (Rs == Rt) { 2445 MI.setOpcode(Mips::BLTZALC_MMR6); 2446 HasRs = true; 2447 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2448 } 2449 else { 2450 MI.setOpcode(Mips::BLTUC_MMR6); 2451 HasRs = true; 2452 HasRt = true; 2453 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2454 } 2455 2456 if (HasRs) 2457 MI.addOperand( 2458 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2459 2460 if (HasRt) 2461 MI.addOperand( 2462 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2463 2464 MI.addOperand(MCOperand::createImm(Imm)); 2465 2466 return MCDisassembler::Success; 2467 } 2468 2469 template <typename InsnType> 2470 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2471 uint64_t Address, 2472 const void *Decoder) { 2473 // We have: 2474 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2475 // Invalid if rt == 0 2476 // BLEZALC_MMR6 if rs == 0 && rt != 0 2477 // BGEZALC_MMR6 if rs == rt && rt != 0 2478 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2479 2480 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2481 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2482 InsnType Imm = 0; 2483 bool HasRs = false; 2484 2485 if (Rt == 0) 2486 return MCDisassembler::Fail; 2487 else if (Rs == 0) { 2488 MI.setOpcode(Mips::BLEZALC_MMR6); 2489 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2490 } 2491 else if (Rs == Rt) { 2492 MI.setOpcode(Mips::BGEZALC_MMR6); 2493 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2494 } 2495 else { 2496 HasRs = true; 2497 MI.setOpcode(Mips::BGEUC_MMR6); 2498 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2499 } 2500 2501 if (HasRs) 2502 MI.addOperand( 2503 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2504 MI.addOperand( 2505 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2506 2507 MI.addOperand(MCOperand::createImm(Imm)); 2508 2509 return MCDisassembler::Success; 2510 } 2511