1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 /// A disassembler class for Mips. 34 class MipsDisassemblerBase : public MCDisassembler { 35 public: 36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, 37 bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit), 40 IsBigEndian(IsBigEndian) {} 41 42 virtual ~MipsDisassemblerBase() {} 43 44 bool isGP64Bit() const { return IsGP64Bit; } 45 46 private: 47 bool IsGP64Bit; 48 protected: 49 bool IsBigEndian; 50 }; 51 52 /// A disassembler class for Mips32. 53 class MipsDisassembler : public MipsDisassemblerBase { 54 bool IsMicroMips; 55 public: 56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) 57 : MipsDisassemblerBase(STI, Ctx, bigEndian) { 58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 59 } 60 61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } 62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } 63 bool hasMips32r6() const { 64 return STI.getFeatureBits() & Mips::FeatureMips32r6; 65 } 66 67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } 68 69 bool hasCOP3() const { 70 // Only present in MIPS-I and MIPS-II 71 return !hasMips32() && !hasMips3(); 72 } 73 74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 75 ArrayRef<uint8_t> Bytes, uint64_t Address, 76 raw_ostream &VStream, 77 raw_ostream &CStream) const override; 78 }; 79 80 /// A disassembler class for Mips64. 81 class Mips64Disassembler : public MipsDisassemblerBase { 82 public: 83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 84 bool bigEndian) : 85 MipsDisassemblerBase(STI, Ctx, bigEndian) {} 86 87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 88 ArrayRef<uint8_t> Bytes, uint64_t Address, 89 raw_ostream &VStream, 90 raw_ostream &CStream) const override; 91 }; 92 93 } // end anonymous namespace 94 95 // Forward declare these because the autogenerated code will reference them. 96 // Definitions are further down. 97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 98 unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 128 unsigned Insn, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 133 unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 162 unsigned Insn, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 192 unsigned RegNo, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 197 unsigned RegNo, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 202 unsigned RegNo, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 207 unsigned RegNo, 208 uint64_t Address, 209 const void *Decoder); 210 211 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 212 unsigned RegNo, 213 uint64_t Address, 214 const void *Decoder); 215 216 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 217 unsigned Offset, 218 uint64_t Address, 219 const void *Decoder); 220 221 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 222 unsigned Insn, 223 uint64_t Address, 224 const void *Decoder); 225 226 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 227 unsigned Offset, 228 uint64_t Address, 229 const void *Decoder); 230 231 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 232 unsigned Offset, 233 uint64_t Address, 234 const void *Decoder); 235 236 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 237 // shifted left by 1 bit. 238 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 239 unsigned Offset, 240 uint64_t Address, 241 const void *Decoder); 242 243 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 244 // shifted left by 1 bit. 245 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 246 unsigned Offset, 247 uint64_t Address, 248 const void *Decoder); 249 250 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 251 // shifted left by 1 bit. 252 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 253 unsigned Offset, 254 uint64_t Address, 255 const void *Decoder); 256 257 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 258 // shifted left by 1 bit. 259 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 260 unsigned Insn, 261 uint64_t Address, 262 const void *Decoder); 263 264 static DecodeStatus DecodeMem(MCInst &Inst, 265 unsigned Insn, 266 uint64_t Address, 267 const void *Decoder); 268 269 static DecodeStatus DecodeCacheOp(MCInst &Inst, 270 unsigned Insn, 271 uint64_t Address, 272 const void *Decoder); 273 274 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeSyncI(MCInst &Inst, 285 unsigned Insn, 286 uint64_t Address, 287 const void *Decoder); 288 289 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 292 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 313 unsigned Insn, 314 uint64_t Address, 315 const void *Decoder); 316 317 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 318 unsigned Insn, 319 uint64_t Address, 320 const void *Decoder); 321 322 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 323 uint64_t Address, 324 const void *Decoder); 325 326 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 327 uint64_t Address, 328 const void *Decoder); 329 330 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 331 uint64_t Address, 332 const void *Decoder); 333 334 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 344 unsigned Value, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 349 unsigned Value, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 354 unsigned Value, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeSimm4(MCInst &Inst, 359 unsigned Value, 360 uint64_t Address, 361 const void *Decoder); 362 363 static DecodeStatus DecodeSimm16(MCInst &Inst, 364 unsigned Insn, 365 uint64_t Address, 366 const void *Decoder); 367 368 // Decode the immediate field of an LSA instruction which 369 // is off by one. 370 static DecodeStatus DecodeLSAImm(MCInst &Inst, 371 unsigned Insn, 372 uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeInsSize(MCInst &Inst, 376 unsigned Insn, 377 uint64_t Address, 378 const void *Decoder); 379 380 static DecodeStatus DecodeExtSize(MCInst &Inst, 381 unsigned Insn, 382 uint64_t Address, 383 const void *Decoder); 384 385 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 388 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 391 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 394 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 395 uint64_t Address, const void *Decoder); 396 397 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 400 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 401 uint64_t Address, const void *Decoder); 402 403 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 404 /// handle. 405 template <typename InsnType> 406 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 407 const void *Decoder); 408 409 template <typename InsnType> 410 static DecodeStatus 411 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 412 const void *Decoder); 413 414 template <typename InsnType> 415 static DecodeStatus 416 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 417 const void *Decoder); 418 419 template <typename InsnType> 420 static DecodeStatus 421 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 422 const void *Decoder); 423 424 template <typename InsnType> 425 static DecodeStatus 426 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 427 const void *Decoder); 428 429 template <typename InsnType> 430 static DecodeStatus 431 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 432 const void *Decoder); 433 434 template <typename InsnType> 435 static DecodeStatus 436 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 437 const void *Decoder); 438 439 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 440 uint64_t Address, 441 const void *Decoder); 442 443 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 444 uint64_t Address, 445 const void *Decoder); 446 447 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 448 uint64_t Address, 449 const void *Decoder); 450 451 namespace llvm { 452 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 453 TheMips64elTarget; 454 } 455 456 static MCDisassembler *createMipsDisassembler( 457 const Target &T, 458 const MCSubtargetInfo &STI, 459 MCContext &Ctx) { 460 return new MipsDisassembler(STI, Ctx, true); 461 } 462 463 static MCDisassembler *createMipselDisassembler( 464 const Target &T, 465 const MCSubtargetInfo &STI, 466 MCContext &Ctx) { 467 return new MipsDisassembler(STI, Ctx, false); 468 } 469 470 static MCDisassembler *createMips64Disassembler( 471 const Target &T, 472 const MCSubtargetInfo &STI, 473 MCContext &Ctx) { 474 return new Mips64Disassembler(STI, Ctx, true); 475 } 476 477 static MCDisassembler *createMips64elDisassembler( 478 const Target &T, 479 const MCSubtargetInfo &STI, 480 MCContext &Ctx) { 481 return new Mips64Disassembler(STI, Ctx, false); 482 } 483 484 extern "C" void LLVMInitializeMipsDisassembler() { 485 // Register the disassembler. 486 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 487 createMipsDisassembler); 488 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 489 createMipselDisassembler); 490 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 491 createMips64Disassembler); 492 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 493 createMips64elDisassembler); 494 } 495 496 #include "MipsGenDisassemblerTables.inc" 497 498 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 499 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); 500 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 501 return *(RegInfo->getRegClass(RC).begin() + RegNo); 502 } 503 504 template <typename InsnType> 505 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 506 const void *Decoder) { 507 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 508 // The size of the n field depends on the element size 509 // The register class also depends on this. 510 InsnType tmp = fieldFromInstruction(insn, 17, 5); 511 unsigned NSize = 0; 512 DecodeFN RegDecoder = nullptr; 513 if ((tmp & 0x18) == 0x00) { // INSVE_B 514 NSize = 4; 515 RegDecoder = DecodeMSA128BRegisterClass; 516 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 517 NSize = 3; 518 RegDecoder = DecodeMSA128HRegisterClass; 519 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 520 NSize = 2; 521 RegDecoder = DecodeMSA128WRegisterClass; 522 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 523 NSize = 1; 524 RegDecoder = DecodeMSA128DRegisterClass; 525 } else 526 llvm_unreachable("Invalid encoding"); 527 528 assert(NSize != 0 && RegDecoder != nullptr); 529 530 // $wd 531 tmp = fieldFromInstruction(insn, 6, 5); 532 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 533 return MCDisassembler::Fail; 534 // $wd_in 535 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 536 return MCDisassembler::Fail; 537 // $n 538 tmp = fieldFromInstruction(insn, 16, NSize); 539 MI.addOperand(MCOperand::CreateImm(tmp)); 540 // $ws 541 tmp = fieldFromInstruction(insn, 11, 5); 542 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 543 return MCDisassembler::Fail; 544 // $n2 545 MI.addOperand(MCOperand::CreateImm(0)); 546 547 return MCDisassembler::Success; 548 } 549 550 template <typename InsnType> 551 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 552 uint64_t Address, 553 const void *Decoder) { 554 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 555 // (otherwise we would have matched the ADDI instruction from the earlier 556 // ISA's instead). 557 // 558 // We have: 559 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 560 // BOVC if rs >= rt 561 // BEQZALC if rs == 0 && rt != 0 562 // BEQC if rs < rt && rs != 0 563 564 InsnType Rs = fieldFromInstruction(insn, 21, 5); 565 InsnType Rt = fieldFromInstruction(insn, 16, 5); 566 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 567 bool HasRs = false; 568 569 if (Rs >= Rt) { 570 MI.setOpcode(Mips::BOVC); 571 HasRs = true; 572 } else if (Rs != 0 && Rs < Rt) { 573 MI.setOpcode(Mips::BEQC); 574 HasRs = true; 575 } else 576 MI.setOpcode(Mips::BEQZALC); 577 578 if (HasRs) 579 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 580 Rs))); 581 582 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 583 Rt))); 584 MI.addOperand(MCOperand::CreateImm(Imm)); 585 586 return MCDisassembler::Success; 587 } 588 589 template <typename InsnType> 590 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 591 uint64_t Address, 592 const void *Decoder) { 593 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 594 // (otherwise we would have matched the ADDI instruction from the earlier 595 // ISA's instead). 596 // 597 // We have: 598 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 599 // BNVC if rs >= rt 600 // BNEZALC if rs == 0 && rt != 0 601 // BNEC if rs < rt && rs != 0 602 603 InsnType Rs = fieldFromInstruction(insn, 21, 5); 604 InsnType Rt = fieldFromInstruction(insn, 16, 5); 605 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 606 bool HasRs = false; 607 608 if (Rs >= Rt) { 609 MI.setOpcode(Mips::BNVC); 610 HasRs = true; 611 } else if (Rs != 0 && Rs < Rt) { 612 MI.setOpcode(Mips::BNEC); 613 HasRs = true; 614 } else 615 MI.setOpcode(Mips::BNEZALC); 616 617 if (HasRs) 618 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 619 Rs))); 620 621 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 622 Rt))); 623 MI.addOperand(MCOperand::CreateImm(Imm)); 624 625 return MCDisassembler::Success; 626 } 627 628 template <typename InsnType> 629 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 630 uint64_t Address, 631 const void *Decoder) { 632 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 633 // (otherwise we would have matched the BLEZL instruction from the earlier 634 // ISA's instead). 635 // 636 // We have: 637 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 638 // Invalid if rs == 0 639 // BLEZC if rs == 0 && rt != 0 640 // BGEZC if rs == rt && rt != 0 641 // BGEC if rs != rt && rs != 0 && rt != 0 642 643 InsnType Rs = fieldFromInstruction(insn, 21, 5); 644 InsnType Rt = fieldFromInstruction(insn, 16, 5); 645 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 646 bool HasRs = false; 647 648 if (Rt == 0) 649 return MCDisassembler::Fail; 650 else if (Rs == 0) 651 MI.setOpcode(Mips::BLEZC); 652 else if (Rs == Rt) 653 MI.setOpcode(Mips::BGEZC); 654 else { 655 HasRs = true; 656 MI.setOpcode(Mips::BGEC); 657 } 658 659 if (HasRs) 660 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 661 Rs))); 662 663 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 664 Rt))); 665 666 MI.addOperand(MCOperand::CreateImm(Imm)); 667 668 return MCDisassembler::Success; 669 } 670 671 template <typename InsnType> 672 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 673 uint64_t Address, 674 const void *Decoder) { 675 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 676 // (otherwise we would have matched the BGTZL instruction from the earlier 677 // ISA's instead). 678 // 679 // We have: 680 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 681 // Invalid if rs == 0 682 // BGTZC if rs == 0 && rt != 0 683 // BLTZC if rs == rt && rt != 0 684 // BLTC if rs != rt && rs != 0 && rt != 0 685 686 bool HasRs = false; 687 688 InsnType Rs = fieldFromInstruction(insn, 21, 5); 689 InsnType Rt = fieldFromInstruction(insn, 16, 5); 690 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 691 692 if (Rt == 0) 693 return MCDisassembler::Fail; 694 else if (Rs == 0) 695 MI.setOpcode(Mips::BGTZC); 696 else if (Rs == Rt) 697 MI.setOpcode(Mips::BLTZC); 698 else { 699 MI.setOpcode(Mips::BLTC); 700 HasRs = true; 701 } 702 703 if (HasRs) 704 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 705 Rs))); 706 707 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 708 Rt))); 709 710 MI.addOperand(MCOperand::CreateImm(Imm)); 711 712 return MCDisassembler::Success; 713 } 714 715 template <typename InsnType> 716 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 717 uint64_t Address, 718 const void *Decoder) { 719 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 720 // (otherwise we would have matched the BGTZ instruction from the earlier 721 // ISA's instead). 722 // 723 // We have: 724 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 725 // BGTZ if rt == 0 726 // BGTZALC if rs == 0 && rt != 0 727 // BLTZALC if rs != 0 && rs == rt 728 // BLTUC if rs != 0 && rs != rt 729 730 InsnType Rs = fieldFromInstruction(insn, 21, 5); 731 InsnType Rt = fieldFromInstruction(insn, 16, 5); 732 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 733 bool HasRs = false; 734 bool HasRt = false; 735 736 if (Rt == 0) { 737 MI.setOpcode(Mips::BGTZ); 738 HasRs = true; 739 } else if (Rs == 0) { 740 MI.setOpcode(Mips::BGTZALC); 741 HasRt = true; 742 } else if (Rs == Rt) { 743 MI.setOpcode(Mips::BLTZALC); 744 HasRs = true; 745 } else { 746 MI.setOpcode(Mips::BLTUC); 747 HasRs = true; 748 HasRt = true; 749 } 750 751 if (HasRs) 752 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 753 Rs))); 754 755 if (HasRt) 756 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 757 Rt))); 758 759 MI.addOperand(MCOperand::CreateImm(Imm)); 760 761 return MCDisassembler::Success; 762 } 763 764 template <typename InsnType> 765 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 766 uint64_t Address, 767 const void *Decoder) { 768 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 769 // (otherwise we would have matched the BLEZL instruction from the earlier 770 // ISA's instead). 771 // 772 // We have: 773 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 774 // Invalid if rs == 0 775 // BLEZALC if rs == 0 && rt != 0 776 // BGEZALC if rs == rt && rt != 0 777 // BGEUC if rs != rt && rs != 0 && rt != 0 778 779 InsnType Rs = fieldFromInstruction(insn, 21, 5); 780 InsnType Rt = fieldFromInstruction(insn, 16, 5); 781 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 782 bool HasRs = false; 783 784 if (Rt == 0) 785 return MCDisassembler::Fail; 786 else if (Rs == 0) 787 MI.setOpcode(Mips::BLEZALC); 788 else if (Rs == Rt) 789 MI.setOpcode(Mips::BGEZALC); 790 else { 791 HasRs = true; 792 MI.setOpcode(Mips::BGEUC); 793 } 794 795 if (HasRs) 796 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rs))); 798 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 799 Rt))); 800 801 MI.addOperand(MCOperand::CreateImm(Imm)); 802 803 return MCDisassembler::Success; 804 } 805 806 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 807 /// according to the given endianess. 808 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 809 uint64_t &Size, uint32_t &Insn, 810 bool IsBigEndian) { 811 // We want to read exactly 2 Bytes of data. 812 if (Bytes.size() < 2) { 813 Size = 0; 814 return MCDisassembler::Fail; 815 } 816 817 if (IsBigEndian) { 818 Insn = (Bytes[0] << 8) | Bytes[1]; 819 } else { 820 Insn = (Bytes[1] << 8) | Bytes[0]; 821 } 822 823 return MCDisassembler::Success; 824 } 825 826 /// Read four bytes from the ArrayRef and return 32 bit word sorted 827 /// according to the given endianess 828 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 829 uint64_t &Size, uint32_t &Insn, 830 bool IsBigEndian, bool IsMicroMips) { 831 // We want to read exactly 4 Bytes of data. 832 if (Bytes.size() < 4) { 833 Size = 0; 834 return MCDisassembler::Fail; 835 } 836 837 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 838 // always precede the low 16 bits in the instruction stream (that is, they 839 // are placed at lower addresses in the instruction stream). 840 // 841 // microMIPS byte ordering: 842 // Big-endian: 0 | 1 | 2 | 3 843 // Little-endian: 1 | 0 | 3 | 2 844 845 if (IsBigEndian) { 846 // Encoded as a big-endian 32-bit word in the stream. 847 Insn = 848 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 849 } else { 850 if (IsMicroMips) { 851 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 852 (Bytes[1] << 24); 853 } else { 854 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 855 (Bytes[3] << 24); 856 } 857 } 858 859 return MCDisassembler::Success; 860 } 861 862 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 863 ArrayRef<uint8_t> Bytes, 864 uint64_t Address, 865 raw_ostream &VStream, 866 raw_ostream &CStream) const { 867 uint32_t Insn; 868 DecodeStatus Result; 869 870 if (IsMicroMips) { 871 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 872 873 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 874 // Calling the auto-generated decoder function. 875 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 876 this, STI); 877 if (Result != MCDisassembler::Fail) { 878 Size = 2; 879 return Result; 880 } 881 882 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 883 if (Result == MCDisassembler::Fail) 884 return MCDisassembler::Fail; 885 886 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 887 // Calling the auto-generated decoder function. 888 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 889 this, STI); 890 if (Result != MCDisassembler::Fail) { 891 Size = 4; 892 return Result; 893 } 894 return MCDisassembler::Fail; 895 } 896 897 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 898 if (Result == MCDisassembler::Fail) 899 return MCDisassembler::Fail; 900 901 if (hasCOP3()) { 902 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 903 Result = 904 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 905 if (Result != MCDisassembler::Fail) { 906 Size = 4; 907 return Result; 908 } 909 } 910 911 if (hasMips32r6() && isGP64()) { 912 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 913 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 914 Address, this, STI); 915 if (Result != MCDisassembler::Fail) { 916 Size = 4; 917 return Result; 918 } 919 } 920 921 if (hasMips32r6()) { 922 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 923 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 924 Address, this, STI); 925 if (Result != MCDisassembler::Fail) { 926 Size = 4; 927 return Result; 928 } 929 } 930 931 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 932 // Calling the auto-generated decoder function. 933 Result = 934 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 935 if (Result != MCDisassembler::Fail) { 936 Size = 4; 937 return Result; 938 } 939 940 return MCDisassembler::Fail; 941 } 942 943 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size, 944 ArrayRef<uint8_t> Bytes, 945 uint64_t Address, 946 raw_ostream &VStream, 947 raw_ostream &CStream) const { 948 uint32_t Insn; 949 950 DecodeStatus Result = 951 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 952 if (Result == MCDisassembler::Fail) 953 return MCDisassembler::Fail; 954 955 // Calling the auto-generated decoder function. 956 Result = 957 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); 958 if (Result != MCDisassembler::Fail) { 959 Size = 4; 960 return Result; 961 } 962 // If we fail to decode in Mips64 decoder space we can try in Mips32 963 Result = 964 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 965 if (Result != MCDisassembler::Fail) { 966 Size = 4; 967 return Result; 968 } 969 970 return MCDisassembler::Fail; 971 } 972 973 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 974 unsigned RegNo, 975 uint64_t Address, 976 const void *Decoder) { 977 978 return MCDisassembler::Fail; 979 980 } 981 982 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 983 unsigned RegNo, 984 uint64_t Address, 985 const void *Decoder) { 986 987 if (RegNo > 31) 988 return MCDisassembler::Fail; 989 990 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 991 Inst.addOperand(MCOperand::CreateReg(Reg)); 992 return MCDisassembler::Success; 993 } 994 995 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 996 unsigned RegNo, 997 uint64_t Address, 998 const void *Decoder) { 999 if (RegNo > 7) 1000 return MCDisassembler::Fail; 1001 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1002 Inst.addOperand(MCOperand::CreateReg(Reg)); 1003 return MCDisassembler::Success; 1004 } 1005 1006 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1007 unsigned RegNo, 1008 uint64_t Address, 1009 const void *Decoder) { 1010 if (RegNo > 7) 1011 return MCDisassembler::Fail; 1012 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1013 Inst.addOperand(MCOperand::CreateReg(Reg)); 1014 return MCDisassembler::Success; 1015 } 1016 1017 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1018 unsigned RegNo, 1019 uint64_t Address, 1020 const void *Decoder) { 1021 if (RegNo > 7) 1022 return MCDisassembler::Fail; 1023 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1024 Inst.addOperand(MCOperand::CreateReg(Reg)); 1025 return MCDisassembler::Success; 1026 } 1027 1028 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1029 unsigned RegNo, 1030 uint64_t Address, 1031 const void *Decoder) { 1032 if (RegNo > 31) 1033 return MCDisassembler::Fail; 1034 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1035 Inst.addOperand(MCOperand::CreateReg(Reg)); 1036 return MCDisassembler::Success; 1037 } 1038 1039 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1040 unsigned RegNo, 1041 uint64_t Address, 1042 const void *Decoder) { 1043 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit()) 1044 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1045 1046 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1047 } 1048 1049 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1050 unsigned RegNo, 1051 uint64_t Address, 1052 const void *Decoder) { 1053 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1054 } 1055 1056 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1057 unsigned RegNo, 1058 uint64_t Address, 1059 const void *Decoder) { 1060 if (RegNo > 31) 1061 return MCDisassembler::Fail; 1062 1063 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1064 Inst.addOperand(MCOperand::CreateReg(Reg)); 1065 return MCDisassembler::Success; 1066 } 1067 1068 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1069 unsigned RegNo, 1070 uint64_t Address, 1071 const void *Decoder) { 1072 if (RegNo > 31) 1073 return MCDisassembler::Fail; 1074 1075 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1076 Inst.addOperand(MCOperand::CreateReg(Reg)); 1077 return MCDisassembler::Success; 1078 } 1079 1080 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1081 unsigned RegNo, 1082 uint64_t Address, 1083 const void *Decoder) { 1084 if (RegNo > 31) 1085 return MCDisassembler::Fail; 1086 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1087 Inst.addOperand(MCOperand::CreateReg(Reg)); 1088 return MCDisassembler::Success; 1089 } 1090 1091 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1092 unsigned RegNo, 1093 uint64_t Address, 1094 const void *Decoder) { 1095 if (RegNo > 7) 1096 return MCDisassembler::Fail; 1097 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1098 Inst.addOperand(MCOperand::CreateReg(Reg)); 1099 return MCDisassembler::Success; 1100 } 1101 1102 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1103 uint64_t Address, 1104 const void *Decoder) { 1105 if (RegNo > 31) 1106 return MCDisassembler::Fail; 1107 1108 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1109 Inst.addOperand(MCOperand::CreateReg(Reg)); 1110 return MCDisassembler::Success; 1111 } 1112 1113 static DecodeStatus DecodeMem(MCInst &Inst, 1114 unsigned Insn, 1115 uint64_t Address, 1116 const void *Decoder) { 1117 int Offset = SignExtend32<16>(Insn & 0xffff); 1118 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1119 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1120 1121 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1122 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1123 1124 if(Inst.getOpcode() == Mips::SC || 1125 Inst.getOpcode() == Mips::SCD){ 1126 Inst.addOperand(MCOperand::CreateReg(Reg)); 1127 } 1128 1129 Inst.addOperand(MCOperand::CreateReg(Reg)); 1130 Inst.addOperand(MCOperand::CreateReg(Base)); 1131 Inst.addOperand(MCOperand::CreateImm(Offset)); 1132 1133 return MCDisassembler::Success; 1134 } 1135 1136 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1137 unsigned Insn, 1138 uint64_t Address, 1139 const void *Decoder) { 1140 int Offset = SignExtend32<16>(Insn & 0xffff); 1141 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1142 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1143 1144 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1145 1146 Inst.addOperand(MCOperand::CreateReg(Base)); 1147 Inst.addOperand(MCOperand::CreateImm(Offset)); 1148 Inst.addOperand(MCOperand::CreateImm(Hint)); 1149 1150 return MCDisassembler::Success; 1151 } 1152 1153 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1154 unsigned Insn, 1155 uint64_t Address, 1156 const void *Decoder) { 1157 int Offset = SignExtend32<12>(Insn & 0xfff); 1158 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1159 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1160 1161 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1162 1163 Inst.addOperand(MCOperand::CreateReg(Base)); 1164 Inst.addOperand(MCOperand::CreateImm(Offset)); 1165 Inst.addOperand(MCOperand::CreateImm(Hint)); 1166 1167 return MCDisassembler::Success; 1168 } 1169 1170 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 1171 unsigned Insn, 1172 uint64_t Address, 1173 const void *Decoder) { 1174 int Offset = fieldFromInstruction(Insn, 7, 9); 1175 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1176 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1177 1178 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1179 1180 Inst.addOperand(MCOperand::CreateReg(Base)); 1181 Inst.addOperand(MCOperand::CreateImm(Offset)); 1182 Inst.addOperand(MCOperand::CreateImm(Hint)); 1183 1184 return MCDisassembler::Success; 1185 } 1186 1187 static DecodeStatus DecodeSyncI(MCInst &Inst, 1188 unsigned Insn, 1189 uint64_t Address, 1190 const void *Decoder) { 1191 int Offset = SignExtend32<16>(Insn & 0xffff); 1192 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1193 1194 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1195 1196 Inst.addOperand(MCOperand::CreateReg(Base)); 1197 Inst.addOperand(MCOperand::CreateImm(Offset)); 1198 1199 return MCDisassembler::Success; 1200 } 1201 1202 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1203 uint64_t Address, const void *Decoder) { 1204 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1205 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1206 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1207 1208 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1209 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1210 1211 Inst.addOperand(MCOperand::CreateReg(Reg)); 1212 Inst.addOperand(MCOperand::CreateReg(Base)); 1213 1214 // The immediate field of an LD/ST instruction is scaled which means it must 1215 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1216 // data format. 1217 // .b - 1 byte 1218 // .h - 2 bytes 1219 // .w - 4 bytes 1220 // .d - 8 bytes 1221 switch(Inst.getOpcode()) 1222 { 1223 default: 1224 assert (0 && "Unexpected instruction"); 1225 return MCDisassembler::Fail; 1226 break; 1227 case Mips::LD_B: 1228 case Mips::ST_B: 1229 Inst.addOperand(MCOperand::CreateImm(Offset)); 1230 break; 1231 case Mips::LD_H: 1232 case Mips::ST_H: 1233 Inst.addOperand(MCOperand::CreateImm(Offset * 2)); 1234 break; 1235 case Mips::LD_W: 1236 case Mips::ST_W: 1237 Inst.addOperand(MCOperand::CreateImm(Offset * 4)); 1238 break; 1239 case Mips::LD_D: 1240 case Mips::ST_D: 1241 Inst.addOperand(MCOperand::CreateImm(Offset * 8)); 1242 break; 1243 } 1244 1245 return MCDisassembler::Success; 1246 } 1247 1248 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1249 unsigned Insn, 1250 uint64_t Address, 1251 const void *Decoder) { 1252 unsigned Offset = Insn & 0xf; 1253 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1254 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1255 1256 switch (Inst.getOpcode()) { 1257 case Mips::LBU16_MM: 1258 case Mips::LHU16_MM: 1259 case Mips::LW16_MM: 1260 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1261 == MCDisassembler::Fail) 1262 return MCDisassembler::Fail; 1263 break; 1264 case Mips::SB16_MM: 1265 case Mips::SH16_MM: 1266 case Mips::SW16_MM: 1267 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1268 == MCDisassembler::Fail) 1269 return MCDisassembler::Fail; 1270 break; 1271 } 1272 1273 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1274 == MCDisassembler::Fail) 1275 return MCDisassembler::Fail; 1276 1277 switch (Inst.getOpcode()) { 1278 case Mips::LBU16_MM: 1279 if (Offset == 0xf) 1280 Inst.addOperand(MCOperand::CreateImm(-1)); 1281 else 1282 Inst.addOperand(MCOperand::CreateImm(Offset)); 1283 break; 1284 case Mips::SB16_MM: 1285 Inst.addOperand(MCOperand::CreateImm(Offset)); 1286 break; 1287 case Mips::LHU16_MM: 1288 case Mips::SH16_MM: 1289 Inst.addOperand(MCOperand::CreateImm(Offset << 1)); 1290 break; 1291 case Mips::LW16_MM: 1292 case Mips::SW16_MM: 1293 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1294 break; 1295 } 1296 1297 return MCDisassembler::Success; 1298 } 1299 1300 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1301 unsigned Insn, 1302 uint64_t Address, 1303 const void *Decoder) { 1304 unsigned Offset = Insn & 0x1F; 1305 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1306 1307 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1308 1309 Inst.addOperand(MCOperand::CreateReg(Reg)); 1310 Inst.addOperand(MCOperand::CreateReg(Mips::SP)); 1311 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1312 1313 return MCDisassembler::Success; 1314 } 1315 1316 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1317 unsigned Insn, 1318 uint64_t Address, 1319 const void *Decoder) { 1320 unsigned Offset = Insn & 0x7F; 1321 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1322 1323 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1324 1325 Inst.addOperand(MCOperand::CreateReg(Reg)); 1326 Inst.addOperand(MCOperand::CreateReg(Mips::GP)); 1327 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1328 1329 return MCDisassembler::Success; 1330 } 1331 1332 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1333 unsigned Insn, 1334 uint64_t Address, 1335 const void *Decoder) { 1336 int Offset = SignExtend32<4>(Insn & 0xf); 1337 1338 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1339 == MCDisassembler::Fail) 1340 return MCDisassembler::Fail; 1341 1342 Inst.addOperand(MCOperand::CreateReg(Mips::SP)); 1343 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1344 1345 return MCDisassembler::Success; 1346 } 1347 1348 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1349 unsigned Insn, 1350 uint64_t Address, 1351 const void *Decoder) { 1352 int Offset = SignExtend32<12>(Insn & 0x0fff); 1353 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1354 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1355 1356 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1357 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1358 1359 switch (Inst.getOpcode()) { 1360 case Mips::SWM32_MM: 1361 case Mips::LWM32_MM: 1362 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1363 == MCDisassembler::Fail) 1364 return MCDisassembler::Fail; 1365 Inst.addOperand(MCOperand::CreateReg(Base)); 1366 Inst.addOperand(MCOperand::CreateImm(Offset)); 1367 break; 1368 case Mips::SC_MM: 1369 Inst.addOperand(MCOperand::CreateReg(Reg)); 1370 // fallthrough 1371 default: 1372 Inst.addOperand(MCOperand::CreateReg(Reg)); 1373 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1374 Inst.addOperand(MCOperand::CreateReg(Reg+1)); 1375 1376 Inst.addOperand(MCOperand::CreateReg(Base)); 1377 Inst.addOperand(MCOperand::CreateImm(Offset)); 1378 } 1379 1380 return MCDisassembler::Success; 1381 } 1382 1383 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1384 unsigned Insn, 1385 uint64_t Address, 1386 const void *Decoder) { 1387 int Offset = SignExtend32<16>(Insn & 0xffff); 1388 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1389 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1390 1391 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1392 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1393 1394 Inst.addOperand(MCOperand::CreateReg(Reg)); 1395 Inst.addOperand(MCOperand::CreateReg(Base)); 1396 Inst.addOperand(MCOperand::CreateImm(Offset)); 1397 1398 return MCDisassembler::Success; 1399 } 1400 1401 static DecodeStatus DecodeFMem(MCInst &Inst, 1402 unsigned Insn, 1403 uint64_t Address, 1404 const void *Decoder) { 1405 int Offset = SignExtend32<16>(Insn & 0xffff); 1406 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1407 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1408 1409 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1410 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1411 1412 Inst.addOperand(MCOperand::CreateReg(Reg)); 1413 Inst.addOperand(MCOperand::CreateReg(Base)); 1414 Inst.addOperand(MCOperand::CreateImm(Offset)); 1415 1416 return MCDisassembler::Success; 1417 } 1418 1419 static DecodeStatus DecodeFMem2(MCInst &Inst, 1420 unsigned Insn, 1421 uint64_t Address, 1422 const void *Decoder) { 1423 int Offset = SignExtend32<16>(Insn & 0xffff); 1424 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1425 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1426 1427 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1428 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1429 1430 Inst.addOperand(MCOperand::CreateReg(Reg)); 1431 Inst.addOperand(MCOperand::CreateReg(Base)); 1432 Inst.addOperand(MCOperand::CreateImm(Offset)); 1433 1434 return MCDisassembler::Success; 1435 } 1436 1437 static DecodeStatus DecodeFMem3(MCInst &Inst, 1438 unsigned Insn, 1439 uint64_t Address, 1440 const void *Decoder) { 1441 int Offset = SignExtend32<16>(Insn & 0xffff); 1442 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1443 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1444 1445 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1446 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1447 1448 Inst.addOperand(MCOperand::CreateReg(Reg)); 1449 Inst.addOperand(MCOperand::CreateReg(Base)); 1450 Inst.addOperand(MCOperand::CreateImm(Offset)); 1451 1452 return MCDisassembler::Success; 1453 } 1454 1455 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1456 unsigned Insn, 1457 uint64_t Address, 1458 const void *Decoder) { 1459 int Offset = SignExtend32<11>(Insn & 0x07ff); 1460 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1461 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1462 1463 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1464 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1465 1466 Inst.addOperand(MCOperand::CreateReg(Reg)); 1467 Inst.addOperand(MCOperand::CreateReg(Base)); 1468 Inst.addOperand(MCOperand::CreateImm(Offset)); 1469 1470 return MCDisassembler::Success; 1471 } 1472 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1473 unsigned Insn, 1474 uint64_t Address, 1475 const void *Decoder) { 1476 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1477 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1478 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1479 1480 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1481 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1482 1483 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1484 Inst.addOperand(MCOperand::CreateReg(Rt)); 1485 } 1486 1487 Inst.addOperand(MCOperand::CreateReg(Rt)); 1488 Inst.addOperand(MCOperand::CreateReg(Base)); 1489 Inst.addOperand(MCOperand::CreateImm(Offset)); 1490 1491 return MCDisassembler::Success; 1492 } 1493 1494 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1495 unsigned RegNo, 1496 uint64_t Address, 1497 const void *Decoder) { 1498 // Currently only hardware register 29 is supported. 1499 if (RegNo != 29) 1500 return MCDisassembler::Fail; 1501 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); 1502 return MCDisassembler::Success; 1503 } 1504 1505 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1506 unsigned RegNo, 1507 uint64_t Address, 1508 const void *Decoder) { 1509 if (RegNo > 30 || RegNo %2) 1510 return MCDisassembler::Fail; 1511 1512 ; 1513 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1514 Inst.addOperand(MCOperand::CreateReg(Reg)); 1515 return MCDisassembler::Success; 1516 } 1517 1518 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1519 unsigned RegNo, 1520 uint64_t Address, 1521 const void *Decoder) { 1522 if (RegNo >= 4) 1523 return MCDisassembler::Fail; 1524 1525 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1526 Inst.addOperand(MCOperand::CreateReg(Reg)); 1527 return MCDisassembler::Success; 1528 } 1529 1530 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1531 unsigned RegNo, 1532 uint64_t Address, 1533 const void *Decoder) { 1534 if (RegNo >= 4) 1535 return MCDisassembler::Fail; 1536 1537 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1538 Inst.addOperand(MCOperand::CreateReg(Reg)); 1539 return MCDisassembler::Success; 1540 } 1541 1542 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1543 unsigned RegNo, 1544 uint64_t Address, 1545 const void *Decoder) { 1546 if (RegNo >= 4) 1547 return MCDisassembler::Fail; 1548 1549 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1550 Inst.addOperand(MCOperand::CreateReg(Reg)); 1551 return MCDisassembler::Success; 1552 } 1553 1554 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1555 unsigned RegNo, 1556 uint64_t Address, 1557 const void *Decoder) { 1558 if (RegNo > 31) 1559 return MCDisassembler::Fail; 1560 1561 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1562 Inst.addOperand(MCOperand::CreateReg(Reg)); 1563 return MCDisassembler::Success; 1564 } 1565 1566 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1567 unsigned RegNo, 1568 uint64_t Address, 1569 const void *Decoder) { 1570 if (RegNo > 31) 1571 return MCDisassembler::Fail; 1572 1573 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1574 Inst.addOperand(MCOperand::CreateReg(Reg)); 1575 return MCDisassembler::Success; 1576 } 1577 1578 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1579 unsigned RegNo, 1580 uint64_t Address, 1581 const void *Decoder) { 1582 if (RegNo > 31) 1583 return MCDisassembler::Fail; 1584 1585 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1586 Inst.addOperand(MCOperand::CreateReg(Reg)); 1587 return MCDisassembler::Success; 1588 } 1589 1590 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1591 unsigned RegNo, 1592 uint64_t Address, 1593 const void *Decoder) { 1594 if (RegNo > 31) 1595 return MCDisassembler::Fail; 1596 1597 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1598 Inst.addOperand(MCOperand::CreateReg(Reg)); 1599 return MCDisassembler::Success; 1600 } 1601 1602 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1603 unsigned RegNo, 1604 uint64_t Address, 1605 const void *Decoder) { 1606 if (RegNo > 7) 1607 return MCDisassembler::Fail; 1608 1609 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1610 Inst.addOperand(MCOperand::CreateReg(Reg)); 1611 return MCDisassembler::Success; 1612 } 1613 1614 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1615 unsigned RegNo, 1616 uint64_t Address, 1617 const void *Decoder) { 1618 if (RegNo > 31) 1619 return MCDisassembler::Fail; 1620 1621 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1622 Inst.addOperand(MCOperand::CreateReg(Reg)); 1623 return MCDisassembler::Success; 1624 } 1625 1626 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1627 unsigned Offset, 1628 uint64_t Address, 1629 const void *Decoder) { 1630 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1631 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1632 return MCDisassembler::Success; 1633 } 1634 1635 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1636 unsigned Insn, 1637 uint64_t Address, 1638 const void *Decoder) { 1639 1640 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1641 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1642 return MCDisassembler::Success; 1643 } 1644 1645 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1646 unsigned Offset, 1647 uint64_t Address, 1648 const void *Decoder) { 1649 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1650 1651 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1652 return MCDisassembler::Success; 1653 } 1654 1655 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1656 unsigned Offset, 1657 uint64_t Address, 1658 const void *Decoder) { 1659 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1660 1661 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1662 return MCDisassembler::Success; 1663 } 1664 1665 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1666 unsigned Offset, 1667 uint64_t Address, 1668 const void *Decoder) { 1669 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1670 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1671 return MCDisassembler::Success; 1672 } 1673 1674 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1675 unsigned Offset, 1676 uint64_t Address, 1677 const void *Decoder) { 1678 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1679 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1680 return MCDisassembler::Success; 1681 } 1682 1683 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1684 unsigned Offset, 1685 uint64_t Address, 1686 const void *Decoder) { 1687 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1688 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1689 return MCDisassembler::Success; 1690 } 1691 1692 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1693 unsigned Insn, 1694 uint64_t Address, 1695 const void *Decoder) { 1696 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1697 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1698 return MCDisassembler::Success; 1699 } 1700 1701 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1702 unsigned Value, 1703 uint64_t Address, 1704 const void *Decoder) { 1705 if (Value == 0) 1706 Inst.addOperand(MCOperand::CreateImm(1)); 1707 else if (Value == 0x7) 1708 Inst.addOperand(MCOperand::CreateImm(-1)); 1709 else 1710 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1711 return MCDisassembler::Success; 1712 } 1713 1714 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1715 unsigned Value, 1716 uint64_t Address, 1717 const void *Decoder) { 1718 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1719 return MCDisassembler::Success; 1720 } 1721 1722 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1723 unsigned Value, 1724 uint64_t Address, 1725 const void *Decoder) { 1726 if (Value == 0x7F) 1727 Inst.addOperand(MCOperand::CreateImm(-1)); 1728 else 1729 Inst.addOperand(MCOperand::CreateImm(Value)); 1730 return MCDisassembler::Success; 1731 } 1732 1733 static DecodeStatus DecodeSimm4(MCInst &Inst, 1734 unsigned Value, 1735 uint64_t Address, 1736 const void *Decoder) { 1737 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value))); 1738 return MCDisassembler::Success; 1739 } 1740 1741 static DecodeStatus DecodeSimm16(MCInst &Inst, 1742 unsigned Insn, 1743 uint64_t Address, 1744 const void *Decoder) { 1745 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 1746 return MCDisassembler::Success; 1747 } 1748 1749 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1750 unsigned Insn, 1751 uint64_t Address, 1752 const void *Decoder) { 1753 // We add one to the immediate field as it was encoded as 'imm - 1'. 1754 Inst.addOperand(MCOperand::CreateImm(Insn + 1)); 1755 return MCDisassembler::Success; 1756 } 1757 1758 static DecodeStatus DecodeInsSize(MCInst &Inst, 1759 unsigned Insn, 1760 uint64_t Address, 1761 const void *Decoder) { 1762 // First we need to grab the pos(lsb) from MCInst. 1763 int Pos = Inst.getOperand(2).getImm(); 1764 int Size = (int) Insn - Pos + 1; 1765 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1766 return MCDisassembler::Success; 1767 } 1768 1769 static DecodeStatus DecodeExtSize(MCInst &Inst, 1770 unsigned Insn, 1771 uint64_t Address, 1772 const void *Decoder) { 1773 int Size = (int) Insn + 1; 1774 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1775 return MCDisassembler::Success; 1776 } 1777 1778 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1779 uint64_t Address, const void *Decoder) { 1780 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4)); 1781 return MCDisassembler::Success; 1782 } 1783 1784 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1785 uint64_t Address, const void *Decoder) { 1786 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8)); 1787 return MCDisassembler::Success; 1788 } 1789 1790 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1791 uint64_t Address, const void *Decoder) { 1792 int32_t DecodedValue; 1793 switch (Insn) { 1794 case 0: DecodedValue = 256; break; 1795 case 1: DecodedValue = 257; break; 1796 case 510: DecodedValue = -258; break; 1797 case 511: DecodedValue = -257; break; 1798 default: DecodedValue = SignExtend32<9>(Insn); break; 1799 } 1800 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4)); 1801 return MCDisassembler::Success; 1802 } 1803 1804 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1805 uint64_t Address, const void *Decoder) { 1806 // Insn must be >= 0, since it is unsigned that condition is always true. 1807 assert(Insn < 16); 1808 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1809 255, 32768, 65535}; 1810 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn])); 1811 return MCDisassembler::Success; 1812 } 1813 1814 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1815 uint64_t Address, const void *Decoder) { 1816 Inst.addOperand(MCOperand::CreateImm(Insn << 2)); 1817 return MCDisassembler::Success; 1818 } 1819 1820 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1821 unsigned Insn, 1822 uint64_t Address, 1823 const void *Decoder) { 1824 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1825 Mips::S6, Mips::FP}; 1826 unsigned RegNum; 1827 1828 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1829 // Empty register lists are not allowed. 1830 if (RegLst == 0) 1831 return MCDisassembler::Fail; 1832 1833 RegNum = RegLst & 0xf; 1834 for (unsigned i = 0; i < RegNum; i++) 1835 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1836 1837 if (RegLst & 0x10) 1838 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1839 1840 return MCDisassembler::Success; 1841 } 1842 1843 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 1844 uint64_t Address, 1845 const void *Decoder) { 1846 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 1847 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 1848 unsigned RegNum = RegLst & 0x3; 1849 1850 for (unsigned i = 0; i <= RegNum; i++) 1851 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1852 1853 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1854 1855 return MCDisassembler::Success; 1856 } 1857 1858 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 1859 uint64_t Address, const void *Decoder) { 1860 1861 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 1862 1863 switch (RegPair) { 1864 default: 1865 return MCDisassembler::Fail; 1866 case 0: 1867 Inst.addOperand(MCOperand::CreateReg(Mips::A1)); 1868 Inst.addOperand(MCOperand::CreateReg(Mips::A2)); 1869 break; 1870 case 1: 1871 Inst.addOperand(MCOperand::CreateReg(Mips::A1)); 1872 Inst.addOperand(MCOperand::CreateReg(Mips::A3)); 1873 break; 1874 case 2: 1875 Inst.addOperand(MCOperand::CreateReg(Mips::A2)); 1876 Inst.addOperand(MCOperand::CreateReg(Mips::A3)); 1877 break; 1878 case 3: 1879 Inst.addOperand(MCOperand::CreateReg(Mips::A0)); 1880 Inst.addOperand(MCOperand::CreateReg(Mips::S5)); 1881 break; 1882 case 4: 1883 Inst.addOperand(MCOperand::CreateReg(Mips::A0)); 1884 Inst.addOperand(MCOperand::CreateReg(Mips::S6)); 1885 break; 1886 case 5: 1887 Inst.addOperand(MCOperand::CreateReg(Mips::A0)); 1888 Inst.addOperand(MCOperand::CreateReg(Mips::A1)); 1889 break; 1890 case 6: 1891 Inst.addOperand(MCOperand::CreateReg(Mips::A0)); 1892 Inst.addOperand(MCOperand::CreateReg(Mips::A2)); 1893 break; 1894 case 7: 1895 Inst.addOperand(MCOperand::CreateReg(Mips::A0)); 1896 Inst.addOperand(MCOperand::CreateReg(Mips::A3)); 1897 break; 1898 } 1899 1900 return MCDisassembler::Success; 1901 } 1902 1903 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 1904 uint64_t Address, const void *Decoder) { 1905 Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2)); 1906 return MCDisassembler::Success; 1907 } 1908