1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 48 49 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 50 51 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 52 53 bool hasCOP3() const { 54 // Only present in MIPS-I and MIPS-II 55 return !hasMips32() && !hasMips3(); 56 } 57 58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 59 ArrayRef<uint8_t> Bytes, uint64_t Address, 60 raw_ostream &VStream, 61 raw_ostream &CStream) const override; 62 }; 63 64 } // end anonymous namespace 65 66 // Forward declare these because the autogenerated code will reference them. 67 // Definitions are further down. 68 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 69 unsigned RegNo, 70 uint64_t Address, 71 const void *Decoder); 72 73 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 74 unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 78 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 79 unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 83 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 99 unsigned Insn, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 114 unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 133 unsigned Insn, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 193 unsigned Offset, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 198 unsigned Insn, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 203 unsigned Offset, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 213 // shifted left by 1 bit. 214 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 215 unsigned Offset, 216 uint64_t Address, 217 const void *Decoder); 218 219 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 220 // shifted left by 1 bit. 221 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 222 unsigned Offset, 223 uint64_t Address, 224 const void *Decoder); 225 226 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 227 // shifted left by 1 bit. 228 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 229 unsigned Offset, 230 uint64_t Address, 231 const void *Decoder); 232 233 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 234 // shifted left by 1 bit. 235 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 236 unsigned Offset, 237 uint64_t Address, 238 const void *Decoder); 239 240 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 241 // shifted left by 1 bit. 242 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 243 unsigned Insn, 244 uint64_t Address, 245 const void *Decoder); 246 247 static DecodeStatus DecodeMem(MCInst &Inst, 248 unsigned Insn, 249 uint64_t Address, 250 const void *Decoder); 251 252 static DecodeStatus DecodeMemEVA(MCInst &Inst, 253 unsigned Insn, 254 uint64_t Address, 255 const void *Decoder); 256 257 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 262 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 263 unsigned Insn, 264 uint64_t Address, 265 const void *Decoder); 266 267 static DecodeStatus DecodeCacheOp(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeSyncI(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeSynciR6(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 305 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 321 unsigned Insn, 322 uint64_t Address, 323 const void *Decoder); 324 325 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 326 unsigned Insn, 327 uint64_t Address, 328 const void *Decoder); 329 330 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 331 unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 336 unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 341 uint64_t Address, 342 const void *Decoder); 343 344 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 349 uint64_t Address, 350 const void *Decoder); 351 352 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 357 unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 362 unsigned Value, 363 uint64_t Address, 364 const void *Decoder); 365 366 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 367 unsigned Value, 368 uint64_t Address, 369 const void *Decoder); 370 371 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 372 unsigned Value, 373 uint64_t Address, 374 const void *Decoder); 375 376 template <unsigned Bits, int Offset, int Scale> 377 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 378 uint64_t Address, 379 const void *Decoder); 380 381 template <unsigned Bits, int Offset> 382 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 383 uint64_t Address, 384 const void *Decoder) { 385 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 386 Decoder); 387 } 388 389 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 390 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 391 uint64_t Address, 392 const void *Decoder); 393 394 static DecodeStatus DecodeInsSize(MCInst &Inst, 395 unsigned Insn, 396 uint64_t Address, 397 const void *Decoder); 398 399 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 400 uint64_t Address, const void *Decoder); 401 402 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 403 uint64_t Address, const void *Decoder); 404 405 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 406 uint64_t Address, const void *Decoder); 407 408 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 409 uint64_t Address, const void *Decoder); 410 411 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 412 uint64_t Address, const void *Decoder); 413 414 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 415 /// handle. 416 template <typename InsnType> 417 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 418 const void *Decoder); 419 420 template <typename InsnType> 421 static DecodeStatus 422 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 423 const void *Decoder); 424 425 template <typename InsnType> 426 static DecodeStatus 427 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 428 const void *Decoder); 429 430 template <typename InsnType> 431 static DecodeStatus 432 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 433 const void *Decoder); 434 435 template <typename InsnType> 436 static DecodeStatus 437 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 438 const void *Decoder); 439 440 template <typename InsnType> 441 static DecodeStatus 442 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus 447 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus 452 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 453 const void *Decoder); 454 455 template <typename InsnType> 456 static DecodeStatus 457 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 458 const void *Decoder); 459 460 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 461 uint64_t Address, 462 const void *Decoder); 463 464 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 465 uint64_t Address, 466 const void *Decoder); 467 468 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 469 uint64_t Address, 470 const void *Decoder); 471 472 namespace llvm { 473 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 474 TheMips64elTarget; 475 } 476 477 static MCDisassembler *createMipsDisassembler( 478 const Target &T, 479 const MCSubtargetInfo &STI, 480 MCContext &Ctx) { 481 return new MipsDisassembler(STI, Ctx, true); 482 } 483 484 static MCDisassembler *createMipselDisassembler( 485 const Target &T, 486 const MCSubtargetInfo &STI, 487 MCContext &Ctx) { 488 return new MipsDisassembler(STI, Ctx, false); 489 } 490 491 extern "C" void LLVMInitializeMipsDisassembler() { 492 // Register the disassembler. 493 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 494 createMipsDisassembler); 495 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 496 createMipselDisassembler); 497 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 498 createMipsDisassembler); 499 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 500 createMipselDisassembler); 501 } 502 503 #include "MipsGenDisassemblerTables.inc" 504 505 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 506 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 507 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 508 return *(RegInfo->getRegClass(RC).begin() + RegNo); 509 } 510 511 template <typename InsnType> 512 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 513 const void *Decoder) { 514 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 515 // The size of the n field depends on the element size 516 // The register class also depends on this. 517 InsnType tmp = fieldFromInstruction(insn, 17, 5); 518 unsigned NSize = 0; 519 DecodeFN RegDecoder = nullptr; 520 if ((tmp & 0x18) == 0x00) { // INSVE_B 521 NSize = 4; 522 RegDecoder = DecodeMSA128BRegisterClass; 523 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 524 NSize = 3; 525 RegDecoder = DecodeMSA128HRegisterClass; 526 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 527 NSize = 2; 528 RegDecoder = DecodeMSA128WRegisterClass; 529 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 530 NSize = 1; 531 RegDecoder = DecodeMSA128DRegisterClass; 532 } else 533 llvm_unreachable("Invalid encoding"); 534 535 assert(NSize != 0 && RegDecoder != nullptr); 536 537 // $wd 538 tmp = fieldFromInstruction(insn, 6, 5); 539 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 540 return MCDisassembler::Fail; 541 // $wd_in 542 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 543 return MCDisassembler::Fail; 544 // $n 545 tmp = fieldFromInstruction(insn, 16, NSize); 546 MI.addOperand(MCOperand::createImm(tmp)); 547 // $ws 548 tmp = fieldFromInstruction(insn, 11, 5); 549 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 550 return MCDisassembler::Fail; 551 // $n2 552 MI.addOperand(MCOperand::createImm(0)); 553 554 return MCDisassembler::Success; 555 } 556 557 template <typename InsnType> 558 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 559 uint64_t Address, 560 const void *Decoder) { 561 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 562 // (otherwise we would have matched the ADDI instruction from the earlier 563 // ISA's instead). 564 // 565 // We have: 566 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 567 // BOVC if rs >= rt 568 // BEQZALC if rs == 0 && rt != 0 569 // BEQC if rs < rt && rs != 0 570 571 InsnType Rs = fieldFromInstruction(insn, 21, 5); 572 InsnType Rt = fieldFromInstruction(insn, 16, 5); 573 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 574 bool HasRs = false; 575 576 if (Rs >= Rt) { 577 MI.setOpcode(Mips::BOVC); 578 HasRs = true; 579 } else if (Rs != 0 && Rs < Rt) { 580 MI.setOpcode(Mips::BEQC); 581 HasRs = true; 582 } else 583 MI.setOpcode(Mips::BEQZALC); 584 585 if (HasRs) 586 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 587 Rs))); 588 589 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 590 Rt))); 591 MI.addOperand(MCOperand::createImm(Imm)); 592 593 return MCDisassembler::Success; 594 } 595 596 template <typename InsnType> 597 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 598 uint64_t Address, 599 const void *Decoder) { 600 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 601 // (otherwise we would have matched the ADDI instruction from the earlier 602 // ISA's instead). 603 // 604 // We have: 605 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 606 // BNVC if rs >= rt 607 // BNEZALC if rs == 0 && rt != 0 608 // BNEC if rs < rt && rs != 0 609 610 InsnType Rs = fieldFromInstruction(insn, 21, 5); 611 InsnType Rt = fieldFromInstruction(insn, 16, 5); 612 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 613 bool HasRs = false; 614 615 if (Rs >= Rt) { 616 MI.setOpcode(Mips::BNVC); 617 HasRs = true; 618 } else if (Rs != 0 && Rs < Rt) { 619 MI.setOpcode(Mips::BNEC); 620 HasRs = true; 621 } else 622 MI.setOpcode(Mips::BNEZALC); 623 624 if (HasRs) 625 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 626 Rs))); 627 628 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 629 Rt))); 630 MI.addOperand(MCOperand::createImm(Imm)); 631 632 return MCDisassembler::Success; 633 } 634 635 template <typename InsnType> 636 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 637 uint64_t Address, 638 const void *Decoder) { 639 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 640 // (otherwise we would have matched the BLEZL instruction from the earlier 641 // ISA's instead). 642 // 643 // We have: 644 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 645 // Invalid if rs == 0 646 // BLEZC if rs == 0 && rt != 0 647 // BGEZC if rs == rt && rt != 0 648 // BGEC if rs != rt && rs != 0 && rt != 0 649 650 InsnType Rs = fieldFromInstruction(insn, 21, 5); 651 InsnType Rt = fieldFromInstruction(insn, 16, 5); 652 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 653 bool HasRs = false; 654 655 if (Rt == 0) 656 return MCDisassembler::Fail; 657 else if (Rs == 0) 658 MI.setOpcode(Mips::BLEZC); 659 else if (Rs == Rt) 660 MI.setOpcode(Mips::BGEZC); 661 else { 662 HasRs = true; 663 MI.setOpcode(Mips::BGEC); 664 } 665 666 if (HasRs) 667 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 668 Rs))); 669 670 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 671 Rt))); 672 673 MI.addOperand(MCOperand::createImm(Imm)); 674 675 return MCDisassembler::Success; 676 } 677 678 template <typename InsnType> 679 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 680 uint64_t Address, 681 const void *Decoder) { 682 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 683 // (otherwise we would have matched the BGTZL instruction from the earlier 684 // ISA's instead). 685 // 686 // We have: 687 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 688 // Invalid if rs == 0 689 // BGTZC if rs == 0 && rt != 0 690 // BLTZC if rs == rt && rt != 0 691 // BLTC if rs != rt && rs != 0 && rt != 0 692 693 bool HasRs = false; 694 695 InsnType Rs = fieldFromInstruction(insn, 21, 5); 696 InsnType Rt = fieldFromInstruction(insn, 16, 5); 697 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 698 699 if (Rt == 0) 700 return MCDisassembler::Fail; 701 else if (Rs == 0) 702 MI.setOpcode(Mips::BGTZC); 703 else if (Rs == Rt) 704 MI.setOpcode(Mips::BLTZC); 705 else { 706 MI.setOpcode(Mips::BLTC); 707 HasRs = true; 708 } 709 710 if (HasRs) 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rs))); 713 714 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 715 Rt))); 716 717 MI.addOperand(MCOperand::createImm(Imm)); 718 719 return MCDisassembler::Success; 720 } 721 722 template <typename InsnType> 723 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 724 uint64_t Address, 725 const void *Decoder) { 726 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 727 // (otherwise we would have matched the BGTZ instruction from the earlier 728 // ISA's instead). 729 // 730 // We have: 731 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 732 // BGTZ if rt == 0 733 // BGTZALC if rs == 0 && rt != 0 734 // BLTZALC if rs != 0 && rs == rt 735 // BLTUC if rs != 0 && rs != rt 736 737 InsnType Rs = fieldFromInstruction(insn, 21, 5); 738 InsnType Rt = fieldFromInstruction(insn, 16, 5); 739 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 740 bool HasRs = false; 741 bool HasRt = false; 742 743 if (Rt == 0) { 744 MI.setOpcode(Mips::BGTZ); 745 HasRs = true; 746 } else if (Rs == 0) { 747 MI.setOpcode(Mips::BGTZALC); 748 HasRt = true; 749 } else if (Rs == Rt) { 750 MI.setOpcode(Mips::BLTZALC); 751 HasRs = true; 752 } else { 753 MI.setOpcode(Mips::BLTUC); 754 HasRs = true; 755 HasRt = true; 756 } 757 758 if (HasRs) 759 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 760 Rs))); 761 762 if (HasRt) 763 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 764 Rt))); 765 766 MI.addOperand(MCOperand::createImm(Imm)); 767 768 return MCDisassembler::Success; 769 } 770 771 template <typename InsnType> 772 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 773 uint64_t Address, 774 const void *Decoder) { 775 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 776 // (otherwise we would have matched the BLEZL instruction from the earlier 777 // ISA's instead). 778 // 779 // We have: 780 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 781 // Invalid if rs == 0 782 // BLEZALC if rs == 0 && rt != 0 783 // BGEZALC if rs == rt && rt != 0 784 // BGEUC if rs != rt && rs != 0 && rt != 0 785 786 InsnType Rs = fieldFromInstruction(insn, 21, 5); 787 InsnType Rt = fieldFromInstruction(insn, 16, 5); 788 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 789 bool HasRs = false; 790 791 if (Rt == 0) 792 return MCDisassembler::Fail; 793 else if (Rs == 0) 794 MI.setOpcode(Mips::BLEZALC); 795 else if (Rs == Rt) 796 MI.setOpcode(Mips::BGEZALC); 797 else { 798 HasRs = true; 799 MI.setOpcode(Mips::BGEUC); 800 } 801 802 if (HasRs) 803 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 804 Rs))); 805 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 806 Rt))); 807 808 MI.addOperand(MCOperand::createImm(Imm)); 809 810 return MCDisassembler::Success; 811 } 812 813 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 814 /// according to the given endianess. 815 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 816 uint64_t &Size, uint32_t &Insn, 817 bool IsBigEndian) { 818 // We want to read exactly 2 Bytes of data. 819 if (Bytes.size() < 2) { 820 Size = 0; 821 return MCDisassembler::Fail; 822 } 823 824 if (IsBigEndian) { 825 Insn = (Bytes[0] << 8) | Bytes[1]; 826 } else { 827 Insn = (Bytes[1] << 8) | Bytes[0]; 828 } 829 830 return MCDisassembler::Success; 831 } 832 833 /// Read four bytes from the ArrayRef and return 32 bit word sorted 834 /// according to the given endianess 835 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 836 uint64_t &Size, uint32_t &Insn, 837 bool IsBigEndian, bool IsMicroMips) { 838 // We want to read exactly 4 Bytes of data. 839 if (Bytes.size() < 4) { 840 Size = 0; 841 return MCDisassembler::Fail; 842 } 843 844 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 845 // always precede the low 16 bits in the instruction stream (that is, they 846 // are placed at lower addresses in the instruction stream). 847 // 848 // microMIPS byte ordering: 849 // Big-endian: 0 | 1 | 2 | 3 850 // Little-endian: 1 | 0 | 3 | 2 851 852 if (IsBigEndian) { 853 // Encoded as a big-endian 32-bit word in the stream. 854 Insn = 855 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 856 } else { 857 if (IsMicroMips) { 858 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 859 (Bytes[1] << 24); 860 } else { 861 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 862 (Bytes[3] << 24); 863 } 864 } 865 866 return MCDisassembler::Success; 867 } 868 869 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 870 ArrayRef<uint8_t> Bytes, 871 uint64_t Address, 872 raw_ostream &VStream, 873 raw_ostream &CStream) const { 874 uint32_t Insn; 875 DecodeStatus Result; 876 877 if (IsMicroMips) { 878 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 879 if (Result == MCDisassembler::Fail) 880 return MCDisassembler::Fail; 881 882 if (hasMips32r6()) { 883 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 884 // Calling the auto-generated decoder function for microMIPS32R6 885 // (and microMIPS64R6) 16-bit instructions. 886 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 887 Address, this, STI); 888 if (Result != MCDisassembler::Fail) { 889 Size = 2; 890 return Result; 891 } 892 } 893 894 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 895 // Calling the auto-generated decoder function for microMIPS 16-bit 896 // instructions. 897 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 898 this, STI); 899 if (Result != MCDisassembler::Fail) { 900 Size = 2; 901 return Result; 902 } 903 904 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 905 if (Result == MCDisassembler::Fail) 906 return MCDisassembler::Fail; 907 908 if (hasMips32r6()) { 909 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 910 // Calling the auto-generated decoder function. 911 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 912 this, STI); 913 if (Result != MCDisassembler::Fail) { 914 Size = 4; 915 return Result; 916 } 917 } 918 919 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 920 // Calling the auto-generated decoder function. 921 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 922 this, STI); 923 if (Result != MCDisassembler::Fail) { 924 Size = 4; 925 return Result; 926 } 927 928 if (hasMips32r6() && isFP64()) { 929 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 930 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 931 Address, this, STI); 932 if (Result != MCDisassembler::Fail) { 933 Size = 4; 934 return Result; 935 } 936 } 937 938 // This is an invalid instruction. Let the disassembler move forward by the 939 // minimum instruction size. 940 Size = 2; 941 return MCDisassembler::Fail; 942 } 943 944 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 945 if (Result == MCDisassembler::Fail) { 946 Size = 4; 947 return MCDisassembler::Fail; 948 } 949 950 if (hasCOP3()) { 951 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 952 Result = 953 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 954 if (Result != MCDisassembler::Fail) { 955 Size = 4; 956 return Result; 957 } 958 } 959 960 if (hasMips32r6() && isGP64()) { 961 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 962 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 963 Address, this, STI); 964 if (Result != MCDisassembler::Fail) { 965 Size = 4; 966 return Result; 967 } 968 } 969 970 if (hasMips32r6()) { 971 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 972 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 973 Address, this, STI); 974 if (Result != MCDisassembler::Fail) { 975 Size = 4; 976 return Result; 977 } 978 } 979 980 if (hasCnMips()) { 981 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 982 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 983 Address, this, STI); 984 if (Result != MCDisassembler::Fail) { 985 Size = 4; 986 return Result; 987 } 988 } 989 990 if (isGP64()) { 991 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 992 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 993 Address, this, STI); 994 if (Result != MCDisassembler::Fail) { 995 Size = 4; 996 return Result; 997 } 998 } 999 1000 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1001 // Calling the auto-generated decoder function. 1002 Result = 1003 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1004 if (Result != MCDisassembler::Fail) { 1005 Size = 4; 1006 return Result; 1007 } 1008 1009 Size = 4; 1010 return MCDisassembler::Fail; 1011 } 1012 1013 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1014 unsigned RegNo, 1015 uint64_t Address, 1016 const void *Decoder) { 1017 1018 return MCDisassembler::Fail; 1019 1020 } 1021 1022 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1023 unsigned RegNo, 1024 uint64_t Address, 1025 const void *Decoder) { 1026 1027 if (RegNo > 31) 1028 return MCDisassembler::Fail; 1029 1030 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1031 Inst.addOperand(MCOperand::createReg(Reg)); 1032 return MCDisassembler::Success; 1033 } 1034 1035 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1036 unsigned RegNo, 1037 uint64_t Address, 1038 const void *Decoder) { 1039 if (RegNo > 7) 1040 return MCDisassembler::Fail; 1041 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1042 Inst.addOperand(MCOperand::createReg(Reg)); 1043 return MCDisassembler::Success; 1044 } 1045 1046 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1047 unsigned RegNo, 1048 uint64_t Address, 1049 const void *Decoder) { 1050 if (RegNo > 7) 1051 return MCDisassembler::Fail; 1052 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1053 Inst.addOperand(MCOperand::createReg(Reg)); 1054 return MCDisassembler::Success; 1055 } 1056 1057 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1058 unsigned RegNo, 1059 uint64_t Address, 1060 const void *Decoder) { 1061 if (RegNo > 7) 1062 return MCDisassembler::Fail; 1063 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1064 Inst.addOperand(MCOperand::createReg(Reg)); 1065 return MCDisassembler::Success; 1066 } 1067 1068 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1069 unsigned RegNo, 1070 uint64_t Address, 1071 const void *Decoder) { 1072 if (RegNo > 31) 1073 return MCDisassembler::Fail; 1074 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1075 Inst.addOperand(MCOperand::createReg(Reg)); 1076 return MCDisassembler::Success; 1077 } 1078 1079 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1080 unsigned RegNo, 1081 uint64_t Address, 1082 const void *Decoder) { 1083 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1084 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1085 1086 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1087 } 1088 1089 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1090 unsigned RegNo, 1091 uint64_t Address, 1092 const void *Decoder) { 1093 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1094 } 1095 1096 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1097 unsigned RegNo, 1098 uint64_t Address, 1099 const void *Decoder) { 1100 if (RegNo > 31) 1101 return MCDisassembler::Fail; 1102 1103 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1104 Inst.addOperand(MCOperand::createReg(Reg)); 1105 return MCDisassembler::Success; 1106 } 1107 1108 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1109 unsigned RegNo, 1110 uint64_t Address, 1111 const void *Decoder) { 1112 if (RegNo > 31) 1113 return MCDisassembler::Fail; 1114 1115 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1116 Inst.addOperand(MCOperand::createReg(Reg)); 1117 return MCDisassembler::Success; 1118 } 1119 1120 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1121 unsigned RegNo, 1122 uint64_t Address, 1123 const void *Decoder) { 1124 if (RegNo > 31) 1125 return MCDisassembler::Fail; 1126 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1127 Inst.addOperand(MCOperand::createReg(Reg)); 1128 return MCDisassembler::Success; 1129 } 1130 1131 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1132 unsigned RegNo, 1133 uint64_t Address, 1134 const void *Decoder) { 1135 if (RegNo > 7) 1136 return MCDisassembler::Fail; 1137 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1138 Inst.addOperand(MCOperand::createReg(Reg)); 1139 return MCDisassembler::Success; 1140 } 1141 1142 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1143 uint64_t Address, 1144 const void *Decoder) { 1145 if (RegNo > 31) 1146 return MCDisassembler::Fail; 1147 1148 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1149 Inst.addOperand(MCOperand::createReg(Reg)); 1150 return MCDisassembler::Success; 1151 } 1152 1153 static DecodeStatus DecodeMem(MCInst &Inst, 1154 unsigned Insn, 1155 uint64_t Address, 1156 const void *Decoder) { 1157 int Offset = SignExtend32<16>(Insn & 0xffff); 1158 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1159 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1160 1161 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1162 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1163 1164 if (Inst.getOpcode() == Mips::SC || 1165 Inst.getOpcode() == Mips::SCD) 1166 Inst.addOperand(MCOperand::createReg(Reg)); 1167 1168 Inst.addOperand(MCOperand::createReg(Reg)); 1169 Inst.addOperand(MCOperand::createReg(Base)); 1170 Inst.addOperand(MCOperand::createImm(Offset)); 1171 1172 return MCDisassembler::Success; 1173 } 1174 1175 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1176 unsigned Insn, 1177 uint64_t Address, 1178 const void *Decoder) { 1179 int Offset = SignExtend32<9>(Insn >> 7); 1180 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1181 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1182 1183 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1184 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1185 1186 if (Inst.getOpcode() == Mips::SCE) 1187 Inst.addOperand(MCOperand::createReg(Reg)); 1188 1189 Inst.addOperand(MCOperand::createReg(Reg)); 1190 Inst.addOperand(MCOperand::createReg(Base)); 1191 Inst.addOperand(MCOperand::createImm(Offset)); 1192 1193 return MCDisassembler::Success; 1194 } 1195 1196 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1197 unsigned Insn, 1198 uint64_t Address, 1199 const void *Decoder) { 1200 int Offset = SignExtend32<9>(Insn & 0x1ff); 1201 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1202 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1203 1204 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1205 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1206 1207 Inst.addOperand(MCOperand::createReg(Reg)); 1208 Inst.addOperand(MCOperand::createReg(Base)); 1209 Inst.addOperand(MCOperand::createImm(Offset)); 1210 1211 return MCDisassembler::Success; 1212 } 1213 1214 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1215 unsigned Insn, 1216 uint64_t Address, 1217 const void *Decoder) { 1218 int Offset = SignExtend32<16>(Insn & 0xffff); 1219 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1220 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1221 1222 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1223 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1224 1225 Inst.addOperand(MCOperand::createReg(Reg)); 1226 Inst.addOperand(MCOperand::createReg(Base)); 1227 Inst.addOperand(MCOperand::createImm(Offset)); 1228 1229 return MCDisassembler::Success; 1230 } 1231 1232 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1233 unsigned Insn, 1234 uint64_t Address, 1235 const void *Decoder) { 1236 int Offset = SignExtend32<16>(Insn & 0xffff); 1237 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1238 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1239 1240 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1241 1242 Inst.addOperand(MCOperand::createReg(Base)); 1243 Inst.addOperand(MCOperand::createImm(Offset)); 1244 Inst.addOperand(MCOperand::createImm(Hint)); 1245 1246 return MCDisassembler::Success; 1247 } 1248 1249 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1250 unsigned Insn, 1251 uint64_t Address, 1252 const void *Decoder) { 1253 int Offset = SignExtend32<12>(Insn & 0xfff); 1254 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1255 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1256 1257 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1258 1259 Inst.addOperand(MCOperand::createReg(Base)); 1260 Inst.addOperand(MCOperand::createImm(Offset)); 1261 Inst.addOperand(MCOperand::createImm(Hint)); 1262 1263 return MCDisassembler::Success; 1264 } 1265 1266 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1267 unsigned Insn, 1268 uint64_t Address, 1269 const void *Decoder) { 1270 int Offset = SignExtend32<9>(Insn & 0x1ff); 1271 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1272 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1273 1274 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1275 1276 Inst.addOperand(MCOperand::createReg(Base)); 1277 Inst.addOperand(MCOperand::createImm(Offset)); 1278 Inst.addOperand(MCOperand::createImm(Hint)); 1279 1280 return MCDisassembler::Success; 1281 } 1282 1283 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1284 unsigned Insn, 1285 uint64_t Address, 1286 const void *Decoder) { 1287 int Offset = SignExtend32<9>(Insn >> 7); 1288 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1289 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1290 1291 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1292 1293 Inst.addOperand(MCOperand::createReg(Base)); 1294 Inst.addOperand(MCOperand::createImm(Offset)); 1295 Inst.addOperand(MCOperand::createImm(Hint)); 1296 1297 return MCDisassembler::Success; 1298 } 1299 1300 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1301 unsigned Insn, 1302 uint64_t Address, 1303 const void *Decoder) { 1304 int Offset = SignExtend32<9>(Insn & 0x1ff); 1305 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1306 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1307 1308 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1309 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1310 1311 Inst.addOperand(MCOperand::createReg(Reg)); 1312 Inst.addOperand(MCOperand::createReg(Base)); 1313 Inst.addOperand(MCOperand::createImm(Offset)); 1314 1315 return MCDisassembler::Success; 1316 } 1317 1318 static DecodeStatus DecodeSyncI(MCInst &Inst, 1319 unsigned Insn, 1320 uint64_t Address, 1321 const void *Decoder) { 1322 int Offset = SignExtend32<16>(Insn & 0xffff); 1323 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1324 1325 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1326 1327 Inst.addOperand(MCOperand::createReg(Base)); 1328 Inst.addOperand(MCOperand::createImm(Offset)); 1329 1330 return MCDisassembler::Success; 1331 } 1332 1333 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1334 unsigned Insn, 1335 uint64_t Address, 1336 const void *Decoder) { 1337 int Immediate = SignExtend32<16>(Insn & 0xffff); 1338 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1339 1340 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1341 1342 Inst.addOperand(MCOperand::createReg(Base)); 1343 Inst.addOperand(MCOperand::createImm(Immediate)); 1344 1345 return MCDisassembler::Success; 1346 } 1347 1348 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1349 uint64_t Address, const void *Decoder) { 1350 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1351 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1352 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1353 1354 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1355 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1356 1357 Inst.addOperand(MCOperand::createReg(Reg)); 1358 Inst.addOperand(MCOperand::createReg(Base)); 1359 1360 // The immediate field of an LD/ST instruction is scaled which means it must 1361 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1362 // data format. 1363 // .b - 1 byte 1364 // .h - 2 bytes 1365 // .w - 4 bytes 1366 // .d - 8 bytes 1367 switch(Inst.getOpcode()) 1368 { 1369 default: 1370 assert (0 && "Unexpected instruction"); 1371 return MCDisassembler::Fail; 1372 break; 1373 case Mips::LD_B: 1374 case Mips::ST_B: 1375 Inst.addOperand(MCOperand::createImm(Offset)); 1376 break; 1377 case Mips::LD_H: 1378 case Mips::ST_H: 1379 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1380 break; 1381 case Mips::LD_W: 1382 case Mips::ST_W: 1383 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1384 break; 1385 case Mips::LD_D: 1386 case Mips::ST_D: 1387 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1388 break; 1389 } 1390 1391 return MCDisassembler::Success; 1392 } 1393 1394 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1395 unsigned Insn, 1396 uint64_t Address, 1397 const void *Decoder) { 1398 unsigned Offset = Insn & 0xf; 1399 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1400 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1401 1402 switch (Inst.getOpcode()) { 1403 case Mips::LBU16_MM: 1404 case Mips::LHU16_MM: 1405 case Mips::LW16_MM: 1406 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1407 == MCDisassembler::Fail) 1408 return MCDisassembler::Fail; 1409 break; 1410 case Mips::SB16_MM: 1411 case Mips::SB16_MMR6: 1412 case Mips::SH16_MM: 1413 case Mips::SH16_MMR6: 1414 case Mips::SW16_MM: 1415 case Mips::SW16_MMR6: 1416 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1417 == MCDisassembler::Fail) 1418 return MCDisassembler::Fail; 1419 break; 1420 } 1421 1422 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1423 == MCDisassembler::Fail) 1424 return MCDisassembler::Fail; 1425 1426 switch (Inst.getOpcode()) { 1427 case Mips::LBU16_MM: 1428 if (Offset == 0xf) 1429 Inst.addOperand(MCOperand::createImm(-1)); 1430 else 1431 Inst.addOperand(MCOperand::createImm(Offset)); 1432 break; 1433 case Mips::SB16_MM: 1434 case Mips::SB16_MMR6: 1435 Inst.addOperand(MCOperand::createImm(Offset)); 1436 break; 1437 case Mips::LHU16_MM: 1438 case Mips::SH16_MM: 1439 case Mips::SH16_MMR6: 1440 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1441 break; 1442 case Mips::LW16_MM: 1443 case Mips::SW16_MM: 1444 case Mips::SW16_MMR6: 1445 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1446 break; 1447 } 1448 1449 return MCDisassembler::Success; 1450 } 1451 1452 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1453 unsigned Insn, 1454 uint64_t Address, 1455 const void *Decoder) { 1456 unsigned Offset = Insn & 0x1F; 1457 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1458 1459 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1460 1461 Inst.addOperand(MCOperand::createReg(Reg)); 1462 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1463 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1464 1465 return MCDisassembler::Success; 1466 } 1467 1468 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1469 unsigned Insn, 1470 uint64_t Address, 1471 const void *Decoder) { 1472 unsigned Offset = Insn & 0x7F; 1473 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1474 1475 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1476 1477 Inst.addOperand(MCOperand::createReg(Reg)); 1478 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1479 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1480 1481 return MCDisassembler::Success; 1482 } 1483 1484 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1485 unsigned Insn, 1486 uint64_t Address, 1487 const void *Decoder) { 1488 int Offset; 1489 switch (Inst.getOpcode()) { 1490 case Mips::LWM16_MMR6: 1491 case Mips::SWM16_MMR6: 1492 Offset = fieldFromInstruction(Insn, 4, 4); 1493 break; 1494 default: 1495 Offset = SignExtend32<4>(Insn & 0xf); 1496 break; 1497 } 1498 1499 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1500 == MCDisassembler::Fail) 1501 return MCDisassembler::Fail; 1502 1503 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1504 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1505 1506 return MCDisassembler::Success; 1507 } 1508 1509 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1510 unsigned Insn, 1511 uint64_t Address, 1512 const void *Decoder) { 1513 int Offset = SignExtend32<9>(Insn & 0x1ff); 1514 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1515 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1516 1517 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1518 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1519 1520 if (Inst.getOpcode() == Mips::SCE_MM) 1521 Inst.addOperand(MCOperand::createReg(Reg)); 1522 1523 Inst.addOperand(MCOperand::createReg(Reg)); 1524 Inst.addOperand(MCOperand::createReg(Base)); 1525 Inst.addOperand(MCOperand::createImm(Offset)); 1526 1527 return MCDisassembler::Success; 1528 } 1529 1530 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1531 unsigned Insn, 1532 uint64_t Address, 1533 const void *Decoder) { 1534 int Offset = SignExtend32<12>(Insn & 0x0fff); 1535 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1536 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1537 1538 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1539 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1540 1541 switch (Inst.getOpcode()) { 1542 case Mips::SWM32_MM: 1543 case Mips::LWM32_MM: 1544 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1545 == MCDisassembler::Fail) 1546 return MCDisassembler::Fail; 1547 Inst.addOperand(MCOperand::createReg(Base)); 1548 Inst.addOperand(MCOperand::createImm(Offset)); 1549 break; 1550 case Mips::SC_MM: 1551 Inst.addOperand(MCOperand::createReg(Reg)); 1552 // fallthrough 1553 default: 1554 Inst.addOperand(MCOperand::createReg(Reg)); 1555 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1556 Inst.addOperand(MCOperand::createReg(Reg+1)); 1557 1558 Inst.addOperand(MCOperand::createReg(Base)); 1559 Inst.addOperand(MCOperand::createImm(Offset)); 1560 } 1561 1562 return MCDisassembler::Success; 1563 } 1564 1565 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1566 unsigned Insn, 1567 uint64_t Address, 1568 const void *Decoder) { 1569 int Offset = SignExtend32<16>(Insn & 0xffff); 1570 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1571 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1572 1573 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1574 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1575 1576 Inst.addOperand(MCOperand::createReg(Reg)); 1577 Inst.addOperand(MCOperand::createReg(Base)); 1578 Inst.addOperand(MCOperand::createImm(Offset)); 1579 1580 return MCDisassembler::Success; 1581 } 1582 1583 static DecodeStatus DecodeFMem(MCInst &Inst, 1584 unsigned Insn, 1585 uint64_t Address, 1586 const void *Decoder) { 1587 int Offset = SignExtend32<16>(Insn & 0xffff); 1588 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1589 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1590 1591 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1592 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1593 1594 Inst.addOperand(MCOperand::createReg(Reg)); 1595 Inst.addOperand(MCOperand::createReg(Base)); 1596 Inst.addOperand(MCOperand::createImm(Offset)); 1597 1598 return MCDisassembler::Success; 1599 } 1600 1601 static DecodeStatus DecodeFMem2(MCInst &Inst, 1602 unsigned Insn, 1603 uint64_t Address, 1604 const void *Decoder) { 1605 int Offset = SignExtend32<16>(Insn & 0xffff); 1606 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1607 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1608 1609 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1610 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1611 1612 Inst.addOperand(MCOperand::createReg(Reg)); 1613 Inst.addOperand(MCOperand::createReg(Base)); 1614 Inst.addOperand(MCOperand::createImm(Offset)); 1615 1616 return MCDisassembler::Success; 1617 } 1618 1619 static DecodeStatus DecodeFMem3(MCInst &Inst, 1620 unsigned Insn, 1621 uint64_t Address, 1622 const void *Decoder) { 1623 int Offset = SignExtend32<16>(Insn & 0xffff); 1624 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1625 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1626 1627 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1628 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1629 1630 Inst.addOperand(MCOperand::createReg(Reg)); 1631 Inst.addOperand(MCOperand::createReg(Base)); 1632 Inst.addOperand(MCOperand::createImm(Offset)); 1633 1634 return MCDisassembler::Success; 1635 } 1636 1637 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1638 unsigned Insn, 1639 uint64_t Address, 1640 const void *Decoder) { 1641 int Offset = SignExtend32<11>(Insn & 0x07ff); 1642 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1643 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1644 1645 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1646 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1647 1648 Inst.addOperand(MCOperand::createReg(Reg)); 1649 Inst.addOperand(MCOperand::createReg(Base)); 1650 Inst.addOperand(MCOperand::createImm(Offset)); 1651 1652 return MCDisassembler::Success; 1653 } 1654 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1655 unsigned Insn, 1656 uint64_t Address, 1657 const void *Decoder) { 1658 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1659 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1660 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1661 1662 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1663 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1664 1665 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1666 Inst.addOperand(MCOperand::createReg(Rt)); 1667 } 1668 1669 Inst.addOperand(MCOperand::createReg(Rt)); 1670 Inst.addOperand(MCOperand::createReg(Base)); 1671 Inst.addOperand(MCOperand::createImm(Offset)); 1672 1673 return MCDisassembler::Success; 1674 } 1675 1676 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1677 unsigned RegNo, 1678 uint64_t Address, 1679 const void *Decoder) { 1680 // Currently only hardware register 29 is supported. 1681 if (RegNo != 29) 1682 return MCDisassembler::Fail; 1683 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1684 return MCDisassembler::Success; 1685 } 1686 1687 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1688 unsigned RegNo, 1689 uint64_t Address, 1690 const void *Decoder) { 1691 if (RegNo > 30 || RegNo %2) 1692 return MCDisassembler::Fail; 1693 1694 ; 1695 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1696 Inst.addOperand(MCOperand::createReg(Reg)); 1697 return MCDisassembler::Success; 1698 } 1699 1700 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1701 unsigned RegNo, 1702 uint64_t Address, 1703 const void *Decoder) { 1704 if (RegNo >= 4) 1705 return MCDisassembler::Fail; 1706 1707 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1708 Inst.addOperand(MCOperand::createReg(Reg)); 1709 return MCDisassembler::Success; 1710 } 1711 1712 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1713 unsigned RegNo, 1714 uint64_t Address, 1715 const void *Decoder) { 1716 if (RegNo >= 4) 1717 return MCDisassembler::Fail; 1718 1719 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1720 Inst.addOperand(MCOperand::createReg(Reg)); 1721 return MCDisassembler::Success; 1722 } 1723 1724 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1725 unsigned RegNo, 1726 uint64_t Address, 1727 const void *Decoder) { 1728 if (RegNo >= 4) 1729 return MCDisassembler::Fail; 1730 1731 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1732 Inst.addOperand(MCOperand::createReg(Reg)); 1733 return MCDisassembler::Success; 1734 } 1735 1736 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1737 unsigned RegNo, 1738 uint64_t Address, 1739 const void *Decoder) { 1740 if (RegNo > 31) 1741 return MCDisassembler::Fail; 1742 1743 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1744 Inst.addOperand(MCOperand::createReg(Reg)); 1745 return MCDisassembler::Success; 1746 } 1747 1748 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1749 unsigned RegNo, 1750 uint64_t Address, 1751 const void *Decoder) { 1752 if (RegNo > 31) 1753 return MCDisassembler::Fail; 1754 1755 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1756 Inst.addOperand(MCOperand::createReg(Reg)); 1757 return MCDisassembler::Success; 1758 } 1759 1760 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1761 unsigned RegNo, 1762 uint64_t Address, 1763 const void *Decoder) { 1764 if (RegNo > 31) 1765 return MCDisassembler::Fail; 1766 1767 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1768 Inst.addOperand(MCOperand::createReg(Reg)); 1769 return MCDisassembler::Success; 1770 } 1771 1772 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1773 unsigned RegNo, 1774 uint64_t Address, 1775 const void *Decoder) { 1776 if (RegNo > 31) 1777 return MCDisassembler::Fail; 1778 1779 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1780 Inst.addOperand(MCOperand::createReg(Reg)); 1781 return MCDisassembler::Success; 1782 } 1783 1784 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1785 unsigned RegNo, 1786 uint64_t Address, 1787 const void *Decoder) { 1788 if (RegNo > 7) 1789 return MCDisassembler::Fail; 1790 1791 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1792 Inst.addOperand(MCOperand::createReg(Reg)); 1793 return MCDisassembler::Success; 1794 } 1795 1796 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1797 unsigned RegNo, 1798 uint64_t Address, 1799 const void *Decoder) { 1800 if (RegNo > 31) 1801 return MCDisassembler::Fail; 1802 1803 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1804 Inst.addOperand(MCOperand::createReg(Reg)); 1805 return MCDisassembler::Success; 1806 } 1807 1808 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1809 unsigned RegNo, 1810 uint64_t Address, 1811 const void *Decoder) { 1812 if (RegNo > 31) 1813 return MCDisassembler::Fail; 1814 1815 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1816 Inst.addOperand(MCOperand::createReg(Reg)); 1817 return MCDisassembler::Success; 1818 } 1819 1820 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1821 unsigned Offset, 1822 uint64_t Address, 1823 const void *Decoder) { 1824 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1825 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1830 unsigned Insn, 1831 uint64_t Address, 1832 const void *Decoder) { 1833 1834 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1835 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1836 return MCDisassembler::Success; 1837 } 1838 1839 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1840 unsigned Offset, 1841 uint64_t Address, 1842 const void *Decoder) { 1843 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1844 1845 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1846 return MCDisassembler::Success; 1847 } 1848 1849 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1850 unsigned Offset, 1851 uint64_t Address, 1852 const void *Decoder) { 1853 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1854 1855 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1856 return MCDisassembler::Success; 1857 } 1858 1859 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1860 unsigned Offset, 1861 uint64_t Address, 1862 const void *Decoder) { 1863 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1864 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1865 return MCDisassembler::Success; 1866 } 1867 1868 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1869 unsigned Offset, 1870 uint64_t Address, 1871 const void *Decoder) { 1872 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1873 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1874 return MCDisassembler::Success; 1875 } 1876 1877 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1878 unsigned Offset, 1879 uint64_t Address, 1880 const void *Decoder) { 1881 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1882 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1883 return MCDisassembler::Success; 1884 } 1885 1886 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 1887 unsigned Offset, 1888 uint64_t Address, 1889 const void *Decoder) { 1890 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 1891 1892 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1893 return MCDisassembler::Success; 1894 } 1895 1896 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1897 unsigned Insn, 1898 uint64_t Address, 1899 const void *Decoder) { 1900 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1901 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1902 return MCDisassembler::Success; 1903 } 1904 1905 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1906 unsigned Value, 1907 uint64_t Address, 1908 const void *Decoder) { 1909 if (Value == 0) 1910 Inst.addOperand(MCOperand::createImm(1)); 1911 else if (Value == 0x7) 1912 Inst.addOperand(MCOperand::createImm(-1)); 1913 else 1914 Inst.addOperand(MCOperand::createImm(Value << 2)); 1915 return MCDisassembler::Success; 1916 } 1917 1918 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 1919 unsigned Value, 1920 uint64_t Address, 1921 const void *Decoder) { 1922 if (Value == 0x7F) 1923 Inst.addOperand(MCOperand::createImm(-1)); 1924 else 1925 Inst.addOperand(MCOperand::createImm(Value)); 1926 return MCDisassembler::Success; 1927 } 1928 1929 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1930 unsigned Value, 1931 uint64_t Address, 1932 const void *Decoder) { 1933 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1934 return MCDisassembler::Success; 1935 } 1936 1937 template <unsigned Bits, int Offset, int Scale> 1938 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1939 uint64_t Address, 1940 const void *Decoder) { 1941 Value &= ((1 << Bits) - 1); 1942 Value *= Scale; 1943 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1944 return MCDisassembler::Success; 1945 } 1946 1947 template <unsigned Bits, int Offset, int ScaleBy> 1948 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1949 uint64_t Address, 1950 const void *Decoder) { 1951 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 1952 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 1953 return MCDisassembler::Success; 1954 } 1955 1956 static DecodeStatus DecodeInsSize(MCInst &Inst, 1957 unsigned Insn, 1958 uint64_t Address, 1959 const void *Decoder) { 1960 // First we need to grab the pos(lsb) from MCInst. 1961 int Pos = Inst.getOperand(2).getImm(); 1962 int Size = (int) Insn - Pos + 1; 1963 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1964 return MCDisassembler::Success; 1965 } 1966 1967 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1968 uint64_t Address, const void *Decoder) { 1969 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1970 return MCDisassembler::Success; 1971 } 1972 1973 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1976 return MCDisassembler::Success; 1977 } 1978 1979 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1980 uint64_t Address, const void *Decoder) { 1981 int32_t DecodedValue; 1982 switch (Insn) { 1983 case 0: DecodedValue = 256; break; 1984 case 1: DecodedValue = 257; break; 1985 case 510: DecodedValue = -258; break; 1986 case 511: DecodedValue = -257; break; 1987 default: DecodedValue = SignExtend32<9>(Insn); break; 1988 } 1989 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1990 return MCDisassembler::Success; 1991 } 1992 1993 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1994 uint64_t Address, const void *Decoder) { 1995 // Insn must be >= 0, since it is unsigned that condition is always true. 1996 assert(Insn < 16); 1997 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1998 255, 32768, 65535}; 1999 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2000 return MCDisassembler::Success; 2001 } 2002 2003 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2004 unsigned Insn, 2005 uint64_t Address, 2006 const void *Decoder) { 2007 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2008 Mips::S6, Mips::S7, Mips::FP}; 2009 unsigned RegNum; 2010 2011 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2012 2013 // Empty register lists are not allowed. 2014 if (RegLst == 0) 2015 return MCDisassembler::Fail; 2016 2017 RegNum = RegLst & 0xf; 2018 2019 // RegLst values 10-15, and 26-31 are reserved. 2020 if (RegNum > 9) 2021 return MCDisassembler::Fail; 2022 2023 for (unsigned i = 0; i < RegNum; i++) 2024 Inst.addOperand(MCOperand::createReg(Regs[i])); 2025 2026 if (RegLst & 0x10) 2027 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2028 2029 return MCDisassembler::Success; 2030 } 2031 2032 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2033 uint64_t Address, 2034 const void *Decoder) { 2035 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2036 unsigned RegLst; 2037 switch(Inst.getOpcode()) { 2038 default: 2039 RegLst = fieldFromInstruction(Insn, 4, 2); 2040 break; 2041 case Mips::LWM16_MMR6: 2042 case Mips::SWM16_MMR6: 2043 RegLst = fieldFromInstruction(Insn, 8, 2); 2044 break; 2045 } 2046 unsigned RegNum = RegLst & 0x3; 2047 2048 for (unsigned i = 0; i <= RegNum; i++) 2049 Inst.addOperand(MCOperand::createReg(Regs[i])); 2050 2051 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2052 2053 return MCDisassembler::Success; 2054 } 2055 2056 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2057 uint64_t Address, const void *Decoder) { 2058 2059 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2060 2061 switch (RegPair) { 2062 default: 2063 return MCDisassembler::Fail; 2064 case 0: 2065 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2066 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2067 break; 2068 case 1: 2069 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2070 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2071 break; 2072 case 2: 2073 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2074 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2075 break; 2076 case 3: 2077 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2078 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2079 break; 2080 case 4: 2081 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2082 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2083 break; 2084 case 5: 2085 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2086 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2087 break; 2088 case 6: 2089 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2090 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2091 break; 2092 case 7: 2093 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2094 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2095 break; 2096 } 2097 2098 return MCDisassembler::Success; 2099 } 2100 2101 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2102 uint64_t Address, const void *Decoder) { 2103 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2104 return MCDisassembler::Success; 2105 } 2106 2107 template <typename InsnType> 2108 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2109 uint64_t Address, 2110 const void *Decoder) { 2111 // We have: 2112 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2113 // Invalid if rt == 0 2114 // BGTZALC_MMR6 if rs == 0 && rt != 0 2115 // BLTZALC_MMR6 if rs != 0 && rs == rt 2116 // BLTUC_MMR6 if rs != 0 && rs != rt 2117 2118 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2119 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2120 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2121 bool HasRs = false; 2122 bool HasRt = false; 2123 2124 if (Rt == 0) 2125 return MCDisassembler::Fail; 2126 else if (Rs == 0) { 2127 MI.setOpcode(Mips::BGTZALC_MMR6); 2128 HasRt = true; 2129 } 2130 else if (Rs == Rt) { 2131 MI.setOpcode(Mips::BLTZALC_MMR6); 2132 HasRs = true; 2133 } 2134 else { 2135 MI.setOpcode(Mips::BLTUC_MMR6); 2136 HasRs = true; 2137 HasRt = true; 2138 } 2139 2140 if (HasRs) 2141 MI.addOperand( 2142 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2143 2144 if (HasRt) 2145 MI.addOperand( 2146 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2147 2148 MI.addOperand(MCOperand::createImm(Imm)); 2149 2150 return MCDisassembler::Success; 2151 } 2152 2153 template <typename InsnType> 2154 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2155 uint64_t Address, 2156 const void *Decoder) { 2157 // We have: 2158 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2159 // Invalid if rs == 0 2160 // BLEZALC_MMR6 if rs == 0 && rt != 0 2161 // BGEZALC_MMR6 if rs == rt && rt != 0 2162 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2163 2164 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2165 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2166 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2167 bool HasRs = false; 2168 2169 if (Rt == 0) 2170 return MCDisassembler::Fail; 2171 else if (Rs == 0) 2172 MI.setOpcode(Mips::BLEZALC_MMR6); 2173 else if (Rs == Rt) 2174 MI.setOpcode(Mips::BGEZALC_MMR6); 2175 else { 2176 HasRs = true; 2177 MI.setOpcode(Mips::BGEUC_MMR6); 2178 } 2179 2180 if (HasRs) 2181 MI.addOperand( 2182 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2183 MI.addOperand( 2184 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2185 2186 MI.addOperand(MCOperand::createImm(Imm)); 2187 2188 return MCDisassembler::Success; 2189 } 2190