1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCDisassembler.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/Support/MathExtras.h" 22 #include "llvm/Support/MemoryObject.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 typedef MCDisassembler::DecodeStatus DecodeStatus; 28 29 namespace { 30 31 /// MipsDisassemblerBase - a disasembler class for Mips. 32 class MipsDisassemblerBase : public MCDisassembler { 33 public: 34 /// Constructor - Initializes the disassembler. 35 /// 36 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, 37 bool bigEndian) : 38 MCDisassembler(STI), RegInfo(Info), 39 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {} 40 41 virtual ~MipsDisassemblerBase() {} 42 43 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } 44 45 bool isN64() const { return IsN64; } 46 47 private: 48 OwningPtr<const MCRegisterInfo> RegInfo; 49 bool IsN64; 50 protected: 51 bool isBigEndian; 52 }; 53 54 /// MipsDisassembler - a disasembler class for Mips32. 55 class MipsDisassembler : public MipsDisassemblerBase { 56 bool IsMicroMips; 57 public: 58 /// Constructor - Initializes the disassembler. 59 /// 60 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, 61 bool bigEndian) : 62 MipsDisassemblerBase(STI, Info, bigEndian) { 63 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 64 } 65 66 /// getInstruction - See MCDisassembler. 67 virtual DecodeStatus getInstruction(MCInst &instr, 68 uint64_t &size, 69 const MemoryObject ®ion, 70 uint64_t address, 71 raw_ostream &vStream, 72 raw_ostream &cStream) const; 73 }; 74 75 76 /// Mips64Disassembler - a disasembler class for Mips64. 77 class Mips64Disassembler : public MipsDisassemblerBase { 78 public: 79 /// Constructor - Initializes the disassembler. 80 /// 81 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, 82 bool bigEndian) : 83 MipsDisassemblerBase(STI, Info, bigEndian) {} 84 85 /// getInstruction - See MCDisassembler. 86 virtual DecodeStatus getInstruction(MCInst &instr, 87 uint64_t &size, 88 const MemoryObject ®ion, 89 uint64_t address, 90 raw_ostream &vStream, 91 raw_ostream &cStream) const; 92 }; 93 94 } // end anonymous namespace 95 96 // Forward declare these because the autogenerated code will reference them. 97 // Definitions are further down. 98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 99 unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 114 unsigned Insn, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 129 unsigned RegNo, 130 uint64_t Address, 131 const void *Decoder); 132 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, 134 unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder); 137 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 139 unsigned RegNo, 140 uint64_t Address, 141 const void *Decoder); 142 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 144 unsigned RegNo, 145 uint64_t Address, 146 const void *Decoder); 147 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 149 unsigned Insn, 150 uint64_t Address, 151 const void *Decoder); 152 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 154 unsigned RegNo, 155 uint64_t Address, 156 const void *Decoder); 157 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 159 unsigned RegNo, 160 uint64_t Address, 161 const void *Decoder); 162 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder); 167 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 169 unsigned RegNo, 170 uint64_t Address, 171 const void *Decoder); 172 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 174 unsigned RegNo, 175 uint64_t Address, 176 const void *Decoder); 177 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 179 unsigned RegNo, 180 uint64_t Address, 181 const void *Decoder); 182 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 184 unsigned RegNo, 185 uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 189 unsigned RegNo, 190 uint64_t Address, 191 const void *Decoder); 192 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 194 unsigned RegNo, 195 uint64_t Address, 196 const void *Decoder); 197 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 199 unsigned Offset, 200 uint64_t Address, 201 const void *Decoder); 202 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 209 // shifted left by 1 bit. 210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 216 // shifted left by 1 bit. 217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 218 unsigned Insn, 219 uint64_t Address, 220 const void *Decoder); 221 222 static DecodeStatus DecodeMem(MCInst &Inst, 223 unsigned Insn, 224 uint64_t Address, 225 const void *Decoder); 226 227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 231 unsigned Insn, 232 uint64_t Address, 233 const void *Decoder); 234 235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 236 unsigned Insn, 237 uint64_t Address, 238 const void *Decoder); 239 240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 241 uint64_t Address, 242 const void *Decoder); 243 244 static DecodeStatus DecodeSimm16(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 249 // Decode the immediate field of an LSA instruction which 250 // is off by one. 251 static DecodeStatus DecodeLSAImm(MCInst &Inst, 252 unsigned Insn, 253 uint64_t Address, 254 const void *Decoder); 255 256 static DecodeStatus DecodeInsSize(MCInst &Inst, 257 unsigned Insn, 258 uint64_t Address, 259 const void *Decoder); 260 261 static DecodeStatus DecodeExtSize(MCInst &Inst, 262 unsigned Insn, 263 uint64_t Address, 264 const void *Decoder); 265 266 namespace llvm { 267 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 268 TheMips64elTarget; 269 } 270 271 static MCDisassembler *createMipsDisassembler( 272 const Target &T, 273 const MCSubtargetInfo &STI) { 274 return new MipsDisassembler(STI, T.createMCRegInfo(""), true); 275 } 276 277 static MCDisassembler *createMipselDisassembler( 278 const Target &T, 279 const MCSubtargetInfo &STI) { 280 return new MipsDisassembler(STI, T.createMCRegInfo(""), false); 281 } 282 283 static MCDisassembler *createMips64Disassembler( 284 const Target &T, 285 const MCSubtargetInfo &STI) { 286 return new Mips64Disassembler(STI, T.createMCRegInfo(""), true); 287 } 288 289 static MCDisassembler *createMips64elDisassembler( 290 const Target &T, 291 const MCSubtargetInfo &STI) { 292 return new Mips64Disassembler(STI, T.createMCRegInfo(""), false); 293 } 294 295 extern "C" void LLVMInitializeMipsDisassembler() { 296 // Register the disassembler. 297 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 298 createMipsDisassembler); 299 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 300 createMipselDisassembler); 301 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 302 createMips64Disassembler); 303 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 304 createMips64elDisassembler); 305 } 306 307 308 #include "MipsGenDisassemblerTables.inc" 309 310 /// readInstruction - read four bytes from the MemoryObject 311 /// and return 32 bit word sorted according to the given endianess 312 static DecodeStatus readInstruction32(const MemoryObject ®ion, 313 uint64_t address, 314 uint64_t &size, 315 uint32_t &insn, 316 bool isBigEndian, 317 bool IsMicroMips) { 318 uint8_t Bytes[4]; 319 320 // We want to read exactly 4 Bytes of data. 321 if (region.readBytes(address, 4, Bytes) == -1) { 322 size = 0; 323 return MCDisassembler::Fail; 324 } 325 326 if (isBigEndian) { 327 // Encoded as a big-endian 32-bit word in the stream. 328 insn = (Bytes[3] << 0) | 329 (Bytes[2] << 8) | 330 (Bytes[1] << 16) | 331 (Bytes[0] << 24); 332 } 333 else { 334 // Encoded as a small-endian 32-bit word in the stream. 335 // Little-endian byte ordering: 336 // mips32r2: 4 | 3 | 2 | 1 337 // microMIPS: 2 | 1 | 4 | 3 338 if (IsMicroMips) { 339 insn = (Bytes[2] << 0) | 340 (Bytes[3] << 8) | 341 (Bytes[0] << 16) | 342 (Bytes[1] << 24); 343 } else { 344 insn = (Bytes[0] << 0) | 345 (Bytes[1] << 8) | 346 (Bytes[2] << 16) | 347 (Bytes[3] << 24); 348 } 349 } 350 351 return MCDisassembler::Success; 352 } 353 354 DecodeStatus 355 MipsDisassembler::getInstruction(MCInst &instr, 356 uint64_t &Size, 357 const MemoryObject &Region, 358 uint64_t Address, 359 raw_ostream &vStream, 360 raw_ostream &cStream) const { 361 uint32_t Insn; 362 363 DecodeStatus Result = readInstruction32(Region, Address, Size, 364 Insn, isBigEndian, IsMicroMips); 365 if (Result == MCDisassembler::Fail) 366 return MCDisassembler::Fail; 367 368 if (IsMicroMips) { 369 // Calling the auto-generated decoder function. 370 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, 371 this, STI); 372 if (Result != MCDisassembler::Fail) { 373 Size = 4; 374 return Result; 375 } 376 return MCDisassembler::Fail; 377 } 378 379 // Calling the auto-generated decoder function. 380 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, 381 this, STI); 382 if (Result != MCDisassembler::Fail) { 383 Size = 4; 384 return Result; 385 } 386 387 return MCDisassembler::Fail; 388 } 389 390 DecodeStatus 391 Mips64Disassembler::getInstruction(MCInst &instr, 392 uint64_t &Size, 393 const MemoryObject &Region, 394 uint64_t Address, 395 raw_ostream &vStream, 396 raw_ostream &cStream) const { 397 uint32_t Insn; 398 399 DecodeStatus Result = readInstruction32(Region, Address, Size, 400 Insn, isBigEndian, false); 401 if (Result == MCDisassembler::Fail) 402 return MCDisassembler::Fail; 403 404 // Calling the auto-generated decoder function. 405 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, 406 this, STI); 407 if (Result != MCDisassembler::Fail) { 408 Size = 4; 409 return Result; 410 } 411 // If we fail to decode in Mips64 decoder space we can try in Mips32 412 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, 413 this, STI); 414 if (Result != MCDisassembler::Fail) { 415 Size = 4; 416 return Result; 417 } 418 419 return MCDisassembler::Fail; 420 } 421 422 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 423 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); 424 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); 425 } 426 427 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 428 unsigned RegNo, 429 uint64_t Address, 430 const void *Decoder) { 431 432 return MCDisassembler::Fail; 433 434 } 435 436 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 437 unsigned RegNo, 438 uint64_t Address, 439 const void *Decoder) { 440 441 if (RegNo > 31) 442 return MCDisassembler::Fail; 443 444 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 445 Inst.addOperand(MCOperand::CreateReg(Reg)); 446 return MCDisassembler::Success; 447 } 448 449 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 450 unsigned RegNo, 451 uint64_t Address, 452 const void *Decoder) { 453 if (RegNo > 31) 454 return MCDisassembler::Fail; 455 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 456 Inst.addOperand(MCOperand::CreateReg(Reg)); 457 return MCDisassembler::Success; 458 } 459 460 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 461 unsigned RegNo, 462 uint64_t Address, 463 const void *Decoder) { 464 if (static_cast<const MipsDisassembler *>(Decoder)->isN64()) 465 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 466 467 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 468 } 469 470 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 471 unsigned RegNo, 472 uint64_t Address, 473 const void *Decoder) { 474 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 475 } 476 477 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 478 unsigned RegNo, 479 uint64_t Address, 480 const void *Decoder) { 481 if (RegNo > 31) 482 return MCDisassembler::Fail; 483 484 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 485 Inst.addOperand(MCOperand::CreateReg(Reg)); 486 return MCDisassembler::Success; 487 } 488 489 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 490 unsigned RegNo, 491 uint64_t Address, 492 const void *Decoder) { 493 if (RegNo > 31) 494 return MCDisassembler::Fail; 495 496 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 497 Inst.addOperand(MCOperand::CreateReg(Reg)); 498 return MCDisassembler::Success; 499 } 500 501 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, 502 unsigned RegNo, 503 uint64_t Address, 504 const void *Decoder) { 505 if (RegNo > 31) 506 return MCDisassembler::Fail; 507 508 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo); 509 Inst.addOperand(MCOperand::CreateReg(Reg)); 510 return MCDisassembler::Success; 511 } 512 513 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 514 unsigned RegNo, 515 uint64_t Address, 516 const void *Decoder) { 517 if (RegNo > 31) 518 return MCDisassembler::Fail; 519 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 520 Inst.addOperand(MCOperand::CreateReg(Reg)); 521 return MCDisassembler::Success; 522 } 523 524 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 525 unsigned RegNo, 526 uint64_t Address, 527 const void *Decoder) { 528 if (RegNo > 7) 529 return MCDisassembler::Fail; 530 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 531 Inst.addOperand(MCOperand::CreateReg(Reg)); 532 return MCDisassembler::Success; 533 } 534 535 static DecodeStatus DecodeMem(MCInst &Inst, 536 unsigned Insn, 537 uint64_t Address, 538 const void *Decoder) { 539 int Offset = SignExtend32<16>(Insn & 0xffff); 540 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 541 unsigned Base = fieldFromInstruction(Insn, 21, 5); 542 543 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 544 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 545 546 if(Inst.getOpcode() == Mips::SC){ 547 Inst.addOperand(MCOperand::CreateReg(Reg)); 548 } 549 550 Inst.addOperand(MCOperand::CreateReg(Reg)); 551 Inst.addOperand(MCOperand::CreateReg(Base)); 552 Inst.addOperand(MCOperand::CreateImm(Offset)); 553 554 return MCDisassembler::Success; 555 } 556 557 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 558 uint64_t Address, const void *Decoder) { 559 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 560 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 561 unsigned Base = fieldFromInstruction(Insn, 11, 5); 562 563 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 564 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 565 566 Inst.addOperand(MCOperand::CreateReg(Reg)); 567 Inst.addOperand(MCOperand::CreateReg(Base)); 568 569 // The immediate field of an LD/ST instruction is scaled which means it must 570 // be multiplied (when decoding) by the size (in bytes) of the instructions' 571 // data format. 572 // .b - 1 byte 573 // .h - 2 bytes 574 // .w - 4 bytes 575 // .d - 8 bytes 576 switch(Inst.getOpcode()) 577 { 578 default: 579 assert (0 && "Unexpected instruction"); 580 return MCDisassembler::Fail; 581 break; 582 case Mips::LD_B: 583 case Mips::ST_B: 584 Inst.addOperand(MCOperand::CreateImm(Offset)); 585 break; 586 case Mips::LD_H: 587 case Mips::ST_H: 588 Inst.addOperand(MCOperand::CreateImm(Offset << 1)); 589 break; 590 case Mips::LD_W: 591 case Mips::ST_W: 592 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 593 break; 594 case Mips::LD_D: 595 case Mips::ST_D: 596 Inst.addOperand(MCOperand::CreateImm(Offset << 3)); 597 break; 598 } 599 600 return MCDisassembler::Success; 601 } 602 603 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 604 unsigned Insn, 605 uint64_t Address, 606 const void *Decoder) { 607 int Offset = SignExtend32<12>(Insn & 0x0fff); 608 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 609 unsigned Base = fieldFromInstruction(Insn, 16, 5); 610 611 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 612 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 613 614 Inst.addOperand(MCOperand::CreateReg(Reg)); 615 Inst.addOperand(MCOperand::CreateReg(Base)); 616 Inst.addOperand(MCOperand::CreateImm(Offset)); 617 618 return MCDisassembler::Success; 619 } 620 621 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 622 unsigned Insn, 623 uint64_t Address, 624 const void *Decoder) { 625 int Offset = SignExtend32<16>(Insn & 0xffff); 626 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 627 unsigned Base = fieldFromInstruction(Insn, 16, 5); 628 629 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 630 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 631 632 Inst.addOperand(MCOperand::CreateReg(Reg)); 633 Inst.addOperand(MCOperand::CreateReg(Base)); 634 Inst.addOperand(MCOperand::CreateImm(Offset)); 635 636 return MCDisassembler::Success; 637 } 638 639 static DecodeStatus DecodeFMem(MCInst &Inst, 640 unsigned Insn, 641 uint64_t Address, 642 const void *Decoder) { 643 int Offset = SignExtend32<16>(Insn & 0xffff); 644 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 645 unsigned Base = fieldFromInstruction(Insn, 21, 5); 646 647 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 648 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 649 650 Inst.addOperand(MCOperand::CreateReg(Reg)); 651 Inst.addOperand(MCOperand::CreateReg(Base)); 652 Inst.addOperand(MCOperand::CreateImm(Offset)); 653 654 return MCDisassembler::Success; 655 } 656 657 658 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 659 unsigned RegNo, 660 uint64_t Address, 661 const void *Decoder) { 662 // Currently only hardware register 29 is supported. 663 if (RegNo != 29) 664 return MCDisassembler::Fail; 665 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); 666 return MCDisassembler::Success; 667 } 668 669 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 670 unsigned RegNo, 671 uint64_t Address, 672 const void *Decoder) { 673 if (RegNo > 30 || RegNo %2) 674 return MCDisassembler::Fail; 675 676 ; 677 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 678 Inst.addOperand(MCOperand::CreateReg(Reg)); 679 return MCDisassembler::Success; 680 } 681 682 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 683 unsigned RegNo, 684 uint64_t Address, 685 const void *Decoder) { 686 if (RegNo >= 4) 687 return MCDisassembler::Fail; 688 689 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 690 Inst.addOperand(MCOperand::CreateReg(Reg)); 691 return MCDisassembler::Success; 692 } 693 694 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 695 unsigned RegNo, 696 uint64_t Address, 697 const void *Decoder) { 698 if (RegNo >= 4) 699 return MCDisassembler::Fail; 700 701 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 702 Inst.addOperand(MCOperand::CreateReg(Reg)); 703 return MCDisassembler::Success; 704 } 705 706 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 707 unsigned RegNo, 708 uint64_t Address, 709 const void *Decoder) { 710 if (RegNo >= 4) 711 return MCDisassembler::Fail; 712 713 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 714 Inst.addOperand(MCOperand::CreateReg(Reg)); 715 return MCDisassembler::Success; 716 } 717 718 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 719 unsigned RegNo, 720 uint64_t Address, 721 const void *Decoder) { 722 if (RegNo > 31) 723 return MCDisassembler::Fail; 724 725 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 726 Inst.addOperand(MCOperand::CreateReg(Reg)); 727 return MCDisassembler::Success; 728 } 729 730 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 731 unsigned RegNo, 732 uint64_t Address, 733 const void *Decoder) { 734 if (RegNo > 31) 735 return MCDisassembler::Fail; 736 737 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 738 Inst.addOperand(MCOperand::CreateReg(Reg)); 739 return MCDisassembler::Success; 740 } 741 742 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 743 unsigned RegNo, 744 uint64_t Address, 745 const void *Decoder) { 746 if (RegNo > 31) 747 return MCDisassembler::Fail; 748 749 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 750 Inst.addOperand(MCOperand::CreateReg(Reg)); 751 return MCDisassembler::Success; 752 } 753 754 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 755 unsigned RegNo, 756 uint64_t Address, 757 const void *Decoder) { 758 if (RegNo > 31) 759 return MCDisassembler::Fail; 760 761 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 762 Inst.addOperand(MCOperand::CreateReg(Reg)); 763 return MCDisassembler::Success; 764 } 765 766 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 767 unsigned RegNo, 768 uint64_t Address, 769 const void *Decoder) { 770 if (RegNo > 7) 771 return MCDisassembler::Fail; 772 773 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 774 Inst.addOperand(MCOperand::CreateReg(Reg)); 775 return MCDisassembler::Success; 776 } 777 778 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 779 unsigned Offset, 780 uint64_t Address, 781 const void *Decoder) { 782 unsigned BranchOffset = Offset & 0xffff; 783 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4; 784 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 785 return MCDisassembler::Success; 786 } 787 788 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 789 unsigned Insn, 790 uint64_t Address, 791 const void *Decoder) { 792 793 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 794 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 795 return MCDisassembler::Success; 796 } 797 798 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 799 unsigned Offset, 800 uint64_t Address, 801 const void *Decoder) { 802 unsigned BranchOffset = Offset & 0xffff; 803 BranchOffset = SignExtend32<18>(BranchOffset << 1); 804 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 805 return MCDisassembler::Success; 806 } 807 808 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 809 unsigned Insn, 810 uint64_t Address, 811 const void *Decoder) { 812 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 813 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 814 return MCDisassembler::Success; 815 } 816 817 static DecodeStatus DecodeSimm16(MCInst &Inst, 818 unsigned Insn, 819 uint64_t Address, 820 const void *Decoder) { 821 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 822 return MCDisassembler::Success; 823 } 824 825 static DecodeStatus DecodeLSAImm(MCInst &Inst, 826 unsigned Insn, 827 uint64_t Address, 828 const void *Decoder) { 829 // We add one to the immediate field as it was encoded as 'imm - 1'. 830 Inst.addOperand(MCOperand::CreateImm(Insn + 1)); 831 return MCDisassembler::Success; 832 } 833 834 static DecodeStatus DecodeInsSize(MCInst &Inst, 835 unsigned Insn, 836 uint64_t Address, 837 const void *Decoder) { 838 // First we need to grab the pos(lsb) from MCInst. 839 int Pos = Inst.getOperand(2).getImm(); 840 int Size = (int) Insn - Pos + 1; 841 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 842 return MCDisassembler::Success; 843 } 844 845 static DecodeStatus DecodeExtSize(MCInst &Inst, 846 unsigned Insn, 847 uint64_t Address, 848 const void *Decoder) { 849 int Size = (int) Insn + 1; 850 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 851 return MCDisassembler::Success; 852 } 853