1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 43 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 44 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 45 bool hasMips32r6() const { 46 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 47 } 48 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 49 50 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 51 52 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 53 54 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 55 56 bool hasCOP3() const { 57 // Only present in MIPS-I and MIPS-II 58 return !hasMips32() && !hasMips3(); 59 } 60 61 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 62 ArrayRef<uint8_t> Bytes, uint64_t Address, 63 raw_ostream &VStream, 64 raw_ostream &CStream) const override; 65 }; 66 67 } // end anonymous namespace 68 69 // Forward declare these because the autogenerated code will reference them. 70 // Definitions are further down. 71 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 72 unsigned RegNo, 73 uint64_t Address, 74 const void *Decoder); 75 76 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 77 unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 81 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 102 unsigned Insn, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 112 unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 136 unsigned Insn, 137 uint64_t Address, 138 const void *Decoder); 139 140 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 141 unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 146 unsigned RegNo, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 196 unsigned Offset, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 201 unsigned Offset, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 216 unsigned Offset, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 235 unsigned Offset, 236 uint64_t Address, 237 const void *Decoder); 238 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 240 // shifted left by 1 bit. 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 242 unsigned Offset, 243 uint64_t Address, 244 const void *Decoder); 245 246 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 247 // shifted left by 1 bit. 248 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 249 unsigned Offset, 250 uint64_t Address, 251 const void *Decoder); 252 253 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 254 // shifted left by 1 bit. 255 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 260 static DecodeStatus DecodeMem(MCInst &Inst, 261 unsigned Insn, 262 uint64_t Address, 263 const void *Decoder); 264 265 static DecodeStatus DecodeMemEVA(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeCacheOp(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 291 unsigned Insn, 292 uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 296 unsigned Insn, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 301 unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodeSyncI(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSynciR6(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 318 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 319 unsigned Insn, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 324 unsigned Insn, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 334 unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 354 uint64_t Address, 355 const void *Decoder); 356 357 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 374 uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 378 unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 383 unsigned Value, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 template <unsigned Bits, int Offset, int Scale> 398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset> 403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder) { 406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 407 Decoder); 408 } 409 410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 412 uint64_t Address, 413 const void *Decoder); 414 415 static DecodeStatus DecodeInsSize(MCInst &Inst, 416 unsigned Insn, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 421 uint64_t Address, const void *Decoder); 422 423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void *Decoder); 425 426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void *Decoder); 428 429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 436 /// handle. 437 template <typename InsnType> 438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 439 const void *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 447 const void *Decoder); 448 449 template <typename InsnType> 450 static DecodeStatus 451 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 452 const void *Decoder); 453 454 template <typename InsnType> 455 static DecodeStatus 456 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 457 const void *Decoder); 458 459 template <typename InsnType> 460 static DecodeStatus 461 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 462 const void *Decoder); 463 464 template <typename InsnType> 465 static DecodeStatus 466 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 467 const void *Decoder); 468 469 template <typename InsnType> 470 static DecodeStatus 471 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 472 const void *Decoder); 473 474 template <typename InsnType> 475 static DecodeStatus 476 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 477 const void *Decoder); 478 479 template <typename InsnType> 480 static DecodeStatus 481 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 482 const void *Decoder); 483 484 template <typename InsnType> 485 static DecodeStatus 486 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 487 const void *Decoder); 488 489 template <typename InsnType> 490 static DecodeStatus 491 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 492 const void *Decoder); 493 494 template <typename InsnType> 495 static DecodeStatus 496 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 497 const void *Decoder); 498 499 template <typename InsnType> 500 static DecodeStatus 501 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 502 const void *Decoder); 503 504 template <typename InsnType> 505 static DecodeStatus 506 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 507 const void *Decoder); 508 509 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 510 uint64_t Address, 511 const void *Decoder); 512 513 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 514 uint64_t Address, 515 const void *Decoder); 516 517 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 518 uint64_t Address, 519 const void *Decoder); 520 521 namespace llvm { 522 Target &getTheMipselTarget(); 523 Target &getTheMipsTarget(); 524 Target &getTheMips64Target(); 525 Target &getTheMips64elTarget(); 526 } 527 528 static MCDisassembler *createMipsDisassembler( 529 const Target &T, 530 const MCSubtargetInfo &STI, 531 MCContext &Ctx) { 532 return new MipsDisassembler(STI, Ctx, true); 533 } 534 535 static MCDisassembler *createMipselDisassembler( 536 const Target &T, 537 const MCSubtargetInfo &STI, 538 MCContext &Ctx) { 539 return new MipsDisassembler(STI, Ctx, false); 540 } 541 542 extern "C" void LLVMInitializeMipsDisassembler() { 543 // Register the disassembler. 544 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 545 createMipsDisassembler); 546 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 547 createMipselDisassembler); 548 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 549 createMipsDisassembler); 550 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 551 createMipselDisassembler); 552 } 553 554 #include "MipsGenDisassemblerTables.inc" 555 556 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 557 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 558 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 559 return *(RegInfo->getRegClass(RC).begin() + RegNo); 560 } 561 562 template <typename InsnType> 563 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 564 const void *Decoder) { 565 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 566 // The size of the n field depends on the element size 567 // The register class also depends on this. 568 InsnType tmp = fieldFromInstruction(insn, 17, 5); 569 unsigned NSize = 0; 570 DecodeFN RegDecoder = nullptr; 571 if ((tmp & 0x18) == 0x00) { // INSVE_B 572 NSize = 4; 573 RegDecoder = DecodeMSA128BRegisterClass; 574 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 575 NSize = 3; 576 RegDecoder = DecodeMSA128HRegisterClass; 577 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 578 NSize = 2; 579 RegDecoder = DecodeMSA128WRegisterClass; 580 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 581 NSize = 1; 582 RegDecoder = DecodeMSA128DRegisterClass; 583 } else 584 llvm_unreachable("Invalid encoding"); 585 586 assert(NSize != 0 && RegDecoder != nullptr); 587 588 // $wd 589 tmp = fieldFromInstruction(insn, 6, 5); 590 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 591 return MCDisassembler::Fail; 592 // $wd_in 593 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 594 return MCDisassembler::Fail; 595 // $n 596 tmp = fieldFromInstruction(insn, 16, NSize); 597 MI.addOperand(MCOperand::createImm(tmp)); 598 // $ws 599 tmp = fieldFromInstruction(insn, 11, 5); 600 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 601 return MCDisassembler::Fail; 602 // $n2 603 MI.addOperand(MCOperand::createImm(0)); 604 605 return MCDisassembler::Success; 606 } 607 608 template <typename InsnType> 609 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 610 const void *Decoder) { 611 InsnType Rt = fieldFromInstruction(insn, 16, 5); 612 InsnType Imm = fieldFromInstruction(insn, 0, 16); 613 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 614 Rt))); 615 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 616 Rt))); 617 MI.addOperand(MCOperand::createImm(Imm)); 618 619 return MCDisassembler::Success; 620 } 621 622 template <typename InsnType> 623 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 624 const void *Decoder) { 625 InsnType Rt = fieldFromInstruction(insn, 21, 5); 626 InsnType Imm = fieldFromInstruction(insn, 0, 16); 627 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 628 Rt))); 629 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 630 Rt))); 631 MI.addOperand(MCOperand::createImm(Imm)); 632 633 return MCDisassembler::Success; 634 } 635 636 template <typename InsnType> 637 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 638 uint64_t Address, 639 const void *Decoder) { 640 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 641 // (otherwise we would have matched the ADDI instruction from the earlier 642 // ISA's instead). 643 // 644 // We have: 645 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 646 // BOVC if rs >= rt 647 // BEQZALC if rs == 0 && rt != 0 648 // BEQC if rs < rt && rs != 0 649 650 InsnType Rs = fieldFromInstruction(insn, 21, 5); 651 InsnType Rt = fieldFromInstruction(insn, 16, 5); 652 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 653 bool HasRs = false; 654 655 if (Rs >= Rt) { 656 MI.setOpcode(Mips::BOVC); 657 HasRs = true; 658 } else if (Rs != 0 && Rs < Rt) { 659 MI.setOpcode(Mips::BEQC); 660 HasRs = true; 661 } else 662 MI.setOpcode(Mips::BEQZALC); 663 664 if (HasRs) 665 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 666 Rs))); 667 668 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 669 Rt))); 670 MI.addOperand(MCOperand::createImm(Imm)); 671 672 return MCDisassembler::Success; 673 } 674 675 template <typename InsnType> 676 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 677 uint64_t Address, 678 const void *Decoder) { 679 InsnType Rt = fieldFromInstruction(insn, 21, 5); 680 InsnType Rs = fieldFromInstruction(insn, 16, 5); 681 int64_t Imm = 0; 682 683 if (Rs >= Rt) { 684 MI.setOpcode(Mips::BOVC_MMR6); 685 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 686 Rt))); 687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 688 Rs))); 689 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 690 } else if (Rs != 0 && Rs < Rt) { 691 MI.setOpcode(Mips::BEQC_MMR6); 692 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 693 Rs))); 694 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 695 Rt))); 696 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 697 } else { 698 MI.setOpcode(Mips::BEQZALC_MMR6); 699 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 700 Rt))); 701 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 702 } 703 704 MI.addOperand(MCOperand::createImm(Imm)); 705 706 return MCDisassembler::Success; 707 } 708 709 template <typename InsnType> 710 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 711 uint64_t Address, 712 const void *Decoder) { 713 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 714 // (otherwise we would have matched the ADDI instruction from the earlier 715 // ISA's instead). 716 // 717 // We have: 718 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 719 // BNVC if rs >= rt 720 // BNEZALC if rs == 0 && rt != 0 721 // BNEC if rs < rt && rs != 0 722 723 InsnType Rs = fieldFromInstruction(insn, 21, 5); 724 InsnType Rt = fieldFromInstruction(insn, 16, 5); 725 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 726 bool HasRs = false; 727 728 if (Rs >= Rt) { 729 MI.setOpcode(Mips::BNVC); 730 HasRs = true; 731 } else if (Rs != 0 && Rs < Rt) { 732 MI.setOpcode(Mips::BNEC); 733 HasRs = true; 734 } else 735 MI.setOpcode(Mips::BNEZALC); 736 737 if (HasRs) 738 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 739 Rs))); 740 741 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 742 Rt))); 743 MI.addOperand(MCOperand::createImm(Imm)); 744 745 return MCDisassembler::Success; 746 } 747 748 template <typename InsnType> 749 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 750 uint64_t Address, 751 const void *Decoder) { 752 InsnType Rt = fieldFromInstruction(insn, 21, 5); 753 InsnType Rs = fieldFromInstruction(insn, 16, 5); 754 int64_t Imm = 0; 755 756 if (Rs >= Rt) { 757 MI.setOpcode(Mips::BNVC_MMR6); 758 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 759 Rt))); 760 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 761 Rs))); 762 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 763 } else if (Rs != 0 && Rs < Rt) { 764 MI.setOpcode(Mips::BNEC_MMR6); 765 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 766 Rs))); 767 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 768 Rt))); 769 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 770 } else { 771 MI.setOpcode(Mips::BNEZALC_MMR6); 772 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 773 Rt))); 774 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 775 } 776 777 MI.addOperand(MCOperand::createImm(Imm)); 778 779 return MCDisassembler::Success; 780 } 781 782 template <typename InsnType> 783 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 784 uint64_t Address, 785 const void *Decoder) { 786 // We have: 787 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 788 // Invalid if rt == 0 789 // BGTZC_MMR6 if rs == 0 && rt != 0 790 // BLTZC_MMR6 if rs == rt && rt != 0 791 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 792 793 InsnType Rt = fieldFromInstruction(insn, 21, 5); 794 InsnType Rs = fieldFromInstruction(insn, 16, 5); 795 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 796 bool HasRs = false; 797 798 if (Rt == 0) 799 return MCDisassembler::Fail; 800 else if (Rs == 0) 801 MI.setOpcode(Mips::BGTZC_MMR6); 802 else if (Rs == Rt) 803 MI.setOpcode(Mips::BLTZC_MMR6); 804 else { 805 MI.setOpcode(Mips::BLTC_MMR6); 806 HasRs = true; 807 } 808 809 if (HasRs) 810 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 811 Rs))); 812 813 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 814 Rt))); 815 816 MI.addOperand(MCOperand::createImm(Imm)); 817 818 return MCDisassembler::Success; 819 } 820 821 template <typename InsnType> 822 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 823 uint64_t Address, 824 const void *Decoder) { 825 // We have: 826 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 827 // Invalid if rt == 0 828 // BLEZC_MMR6 if rs == 0 && rt != 0 829 // BGEZC_MMR6 if rs == rt && rt != 0 830 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 831 832 InsnType Rt = fieldFromInstruction(insn, 21, 5); 833 InsnType Rs = fieldFromInstruction(insn, 16, 5); 834 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 835 bool HasRs = false; 836 837 if (Rt == 0) 838 return MCDisassembler::Fail; 839 else if (Rs == 0) 840 MI.setOpcode(Mips::BLEZC_MMR6); 841 else if (Rs == Rt) 842 MI.setOpcode(Mips::BGEZC_MMR6); 843 else { 844 HasRs = true; 845 MI.setOpcode(Mips::BGEC_MMR6); 846 } 847 848 if (HasRs) 849 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 850 Rs))); 851 852 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 853 Rt))); 854 855 MI.addOperand(MCOperand::createImm(Imm)); 856 857 return MCDisassembler::Success; 858 } 859 860 template <typename InsnType> 861 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 862 uint64_t Address, 863 const void *Decoder) { 864 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 865 // (otherwise we would have matched the BLEZL instruction from the earlier 866 // ISA's instead). 867 // 868 // We have: 869 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 870 // Invalid if rs == 0 871 // BLEZC if rs == 0 && rt != 0 872 // BGEZC if rs == rt && rt != 0 873 // BGEC if rs != rt && rs != 0 && rt != 0 874 875 InsnType Rs = fieldFromInstruction(insn, 21, 5); 876 InsnType Rt = fieldFromInstruction(insn, 16, 5); 877 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 878 bool HasRs = false; 879 880 if (Rt == 0) 881 return MCDisassembler::Fail; 882 else if (Rs == 0) 883 MI.setOpcode(Mips::BLEZC); 884 else if (Rs == Rt) 885 MI.setOpcode(Mips::BGEZC); 886 else { 887 HasRs = true; 888 MI.setOpcode(Mips::BGEC); 889 } 890 891 if (HasRs) 892 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 893 Rs))); 894 895 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 896 Rt))); 897 898 MI.addOperand(MCOperand::createImm(Imm)); 899 900 return MCDisassembler::Success; 901 } 902 903 template <typename InsnType> 904 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 905 uint64_t Address, 906 const void *Decoder) { 907 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 908 // (otherwise we would have matched the BGTZL instruction from the earlier 909 // ISA's instead). 910 // 911 // We have: 912 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 913 // Invalid if rs == 0 914 // BGTZC if rs == 0 && rt != 0 915 // BLTZC if rs == rt && rt != 0 916 // BLTC if rs != rt && rs != 0 && rt != 0 917 918 bool HasRs = false; 919 920 InsnType Rs = fieldFromInstruction(insn, 21, 5); 921 InsnType Rt = fieldFromInstruction(insn, 16, 5); 922 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 923 924 if (Rt == 0) 925 return MCDisassembler::Fail; 926 else if (Rs == 0) 927 MI.setOpcode(Mips::BGTZC); 928 else if (Rs == Rt) 929 MI.setOpcode(Mips::BLTZC); 930 else { 931 MI.setOpcode(Mips::BLTC); 932 HasRs = true; 933 } 934 935 if (HasRs) 936 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 937 Rs))); 938 939 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 940 Rt))); 941 942 MI.addOperand(MCOperand::createImm(Imm)); 943 944 return MCDisassembler::Success; 945 } 946 947 template <typename InsnType> 948 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 949 uint64_t Address, 950 const void *Decoder) { 951 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 952 // (otherwise we would have matched the BGTZ instruction from the earlier 953 // ISA's instead). 954 // 955 // We have: 956 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 957 // BGTZ if rt == 0 958 // BGTZALC if rs == 0 && rt != 0 959 // BLTZALC if rs != 0 && rs == rt 960 // BLTUC if rs != 0 && rs != rt 961 962 InsnType Rs = fieldFromInstruction(insn, 21, 5); 963 InsnType Rt = fieldFromInstruction(insn, 16, 5); 964 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 965 bool HasRs = false; 966 bool HasRt = false; 967 968 if (Rt == 0) { 969 MI.setOpcode(Mips::BGTZ); 970 HasRs = true; 971 } else if (Rs == 0) { 972 MI.setOpcode(Mips::BGTZALC); 973 HasRt = true; 974 } else if (Rs == Rt) { 975 MI.setOpcode(Mips::BLTZALC); 976 HasRs = true; 977 } else { 978 MI.setOpcode(Mips::BLTUC); 979 HasRs = true; 980 HasRt = true; 981 } 982 983 if (HasRs) 984 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 985 Rs))); 986 987 if (HasRt) 988 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 989 Rt))); 990 991 MI.addOperand(MCOperand::createImm(Imm)); 992 993 return MCDisassembler::Success; 994 } 995 996 template <typename InsnType> 997 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 998 uint64_t Address, 999 const void *Decoder) { 1000 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1001 // (otherwise we would have matched the BLEZL instruction from the earlier 1002 // ISA's instead). 1003 // 1004 // We have: 1005 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1006 // Invalid if rs == 0 1007 // BLEZALC if rs == 0 && rt != 0 1008 // BGEZALC if rs == rt && rt != 0 1009 // BGEUC if rs != rt && rs != 0 && rt != 0 1010 1011 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1012 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1013 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1014 bool HasRs = false; 1015 1016 if (Rt == 0) 1017 return MCDisassembler::Fail; 1018 else if (Rs == 0) 1019 MI.setOpcode(Mips::BLEZALC); 1020 else if (Rs == Rt) 1021 MI.setOpcode(Mips::BGEZALC); 1022 else { 1023 HasRs = true; 1024 MI.setOpcode(Mips::BGEUC); 1025 } 1026 1027 if (HasRs) 1028 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1029 Rs))); 1030 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1031 Rt))); 1032 1033 MI.addOperand(MCOperand::createImm(Imm)); 1034 1035 return MCDisassembler::Success; 1036 } 1037 1038 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1039 /// according to the given endianess. 1040 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1041 uint64_t &Size, uint32_t &Insn, 1042 bool IsBigEndian) { 1043 // We want to read exactly 2 Bytes of data. 1044 if (Bytes.size() < 2) { 1045 Size = 0; 1046 return MCDisassembler::Fail; 1047 } 1048 1049 if (IsBigEndian) { 1050 Insn = (Bytes[0] << 8) | Bytes[1]; 1051 } else { 1052 Insn = (Bytes[1] << 8) | Bytes[0]; 1053 } 1054 1055 return MCDisassembler::Success; 1056 } 1057 1058 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1059 /// according to the given endianess 1060 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1061 uint64_t &Size, uint32_t &Insn, 1062 bool IsBigEndian, bool IsMicroMips) { 1063 // We want to read exactly 4 Bytes of data. 1064 if (Bytes.size() < 4) { 1065 Size = 0; 1066 return MCDisassembler::Fail; 1067 } 1068 1069 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1070 // always precede the low 16 bits in the instruction stream (that is, they 1071 // are placed at lower addresses in the instruction stream). 1072 // 1073 // microMIPS byte ordering: 1074 // Big-endian: 0 | 1 | 2 | 3 1075 // Little-endian: 1 | 0 | 3 | 2 1076 1077 if (IsBigEndian) { 1078 // Encoded as a big-endian 32-bit word in the stream. 1079 Insn = 1080 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1081 } else { 1082 if (IsMicroMips) { 1083 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1084 (Bytes[1] << 24); 1085 } else { 1086 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1087 (Bytes[3] << 24); 1088 } 1089 } 1090 1091 return MCDisassembler::Success; 1092 } 1093 1094 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1095 ArrayRef<uint8_t> Bytes, 1096 uint64_t Address, 1097 raw_ostream &VStream, 1098 raw_ostream &CStream) const { 1099 uint32_t Insn; 1100 DecodeStatus Result; 1101 1102 if (IsMicroMips) { 1103 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1104 if (Result == MCDisassembler::Fail) 1105 return MCDisassembler::Fail; 1106 1107 if (hasMips32r6()) { 1108 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1109 // Calling the auto-generated decoder function for microMIPS32R6 1110 // (and microMIPS64R6) 16-bit instructions. 1111 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1112 Address, this, STI); 1113 if (Result != MCDisassembler::Fail) { 1114 Size = 2; 1115 return Result; 1116 } 1117 } 1118 1119 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1120 // Calling the auto-generated decoder function for microMIPS 16-bit 1121 // instructions. 1122 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1123 this, STI); 1124 if (Result != MCDisassembler::Fail) { 1125 Size = 2; 1126 return Result; 1127 } 1128 1129 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1130 if (Result == MCDisassembler::Fail) 1131 return MCDisassembler::Fail; 1132 1133 if (hasMips32r6()) { 1134 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1135 // Calling the auto-generated decoder function. 1136 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1137 this, STI); 1138 if (Result != MCDisassembler::Fail) { 1139 Size = 4; 1140 return Result; 1141 } 1142 } 1143 1144 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1145 // Calling the auto-generated decoder function. 1146 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1147 this, STI); 1148 if (Result != MCDisassembler::Fail) { 1149 Size = 4; 1150 return Result; 1151 } 1152 1153 if (hasMips32r6() && isFP64()) { 1154 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 1155 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 1156 Address, this, STI); 1157 if (Result != MCDisassembler::Fail) { 1158 Size = 4; 1159 return Result; 1160 } 1161 } 1162 1163 // This is an invalid instruction. Let the disassembler move forward by the 1164 // minimum instruction size. 1165 Size = 2; 1166 return MCDisassembler::Fail; 1167 } 1168 1169 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1170 if (Result == MCDisassembler::Fail) { 1171 Size = 4; 1172 return MCDisassembler::Fail; 1173 } 1174 1175 if (hasCOP3()) { 1176 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1177 Result = 1178 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1179 if (Result != MCDisassembler::Fail) { 1180 Size = 4; 1181 return Result; 1182 } 1183 } 1184 1185 if (hasMips32r6() && isGP64()) { 1186 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1187 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1188 Address, this, STI); 1189 if (Result != MCDisassembler::Fail) { 1190 Size = 4; 1191 return Result; 1192 } 1193 } 1194 1195 if (hasMips32r6() && isPTR64()) { 1196 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1197 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1198 Address, this, STI); 1199 if (Result != MCDisassembler::Fail) { 1200 Size = 4; 1201 return Result; 1202 } 1203 } 1204 1205 if (hasMips32r6()) { 1206 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1207 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1208 Address, this, STI); 1209 if (Result != MCDisassembler::Fail) { 1210 Size = 4; 1211 return Result; 1212 } 1213 } 1214 1215 if (hasMips2() && isPTR64()) { 1216 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1217 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1218 Address, this, STI); 1219 if (Result != MCDisassembler::Fail) { 1220 Size = 4; 1221 return Result; 1222 } 1223 } 1224 1225 if (hasCnMips()) { 1226 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1227 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1228 Address, this, STI); 1229 if (Result != MCDisassembler::Fail) { 1230 Size = 4; 1231 return Result; 1232 } 1233 } 1234 1235 if (isGP64()) { 1236 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1237 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1238 Address, this, STI); 1239 if (Result != MCDisassembler::Fail) { 1240 Size = 4; 1241 return Result; 1242 } 1243 } 1244 1245 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1246 // Calling the auto-generated decoder function. 1247 Result = 1248 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1249 if (Result != MCDisassembler::Fail) { 1250 Size = 4; 1251 return Result; 1252 } 1253 1254 Size = 4; 1255 return MCDisassembler::Fail; 1256 } 1257 1258 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1259 unsigned RegNo, 1260 uint64_t Address, 1261 const void *Decoder) { 1262 1263 return MCDisassembler::Fail; 1264 1265 } 1266 1267 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1268 unsigned RegNo, 1269 uint64_t Address, 1270 const void *Decoder) { 1271 1272 if (RegNo > 31) 1273 return MCDisassembler::Fail; 1274 1275 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1276 Inst.addOperand(MCOperand::createReg(Reg)); 1277 return MCDisassembler::Success; 1278 } 1279 1280 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1281 unsigned RegNo, 1282 uint64_t Address, 1283 const void *Decoder) { 1284 if (RegNo > 7) 1285 return MCDisassembler::Fail; 1286 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1287 Inst.addOperand(MCOperand::createReg(Reg)); 1288 return MCDisassembler::Success; 1289 } 1290 1291 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1292 unsigned RegNo, 1293 uint64_t Address, 1294 const void *Decoder) { 1295 if (RegNo > 7) 1296 return MCDisassembler::Fail; 1297 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1298 Inst.addOperand(MCOperand::createReg(Reg)); 1299 return MCDisassembler::Success; 1300 } 1301 1302 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1303 unsigned RegNo, 1304 uint64_t Address, 1305 const void *Decoder) { 1306 if (RegNo > 7) 1307 return MCDisassembler::Fail; 1308 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1309 Inst.addOperand(MCOperand::createReg(Reg)); 1310 return MCDisassembler::Success; 1311 } 1312 1313 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1314 unsigned RegNo, 1315 uint64_t Address, 1316 const void *Decoder) { 1317 if (RegNo > 31) 1318 return MCDisassembler::Fail; 1319 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1320 Inst.addOperand(MCOperand::createReg(Reg)); 1321 return MCDisassembler::Success; 1322 } 1323 1324 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1325 unsigned RegNo, 1326 uint64_t Address, 1327 const void *Decoder) { 1328 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1329 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1330 1331 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1332 } 1333 1334 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1335 unsigned RegNo, 1336 uint64_t Address, 1337 const void *Decoder) { 1338 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1339 } 1340 1341 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1342 unsigned RegNo, 1343 uint64_t Address, 1344 const void *Decoder) { 1345 if (RegNo > 31) 1346 return MCDisassembler::Fail; 1347 1348 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1349 Inst.addOperand(MCOperand::createReg(Reg)); 1350 return MCDisassembler::Success; 1351 } 1352 1353 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1354 unsigned RegNo, 1355 uint64_t Address, 1356 const void *Decoder) { 1357 if (RegNo > 31) 1358 return MCDisassembler::Fail; 1359 1360 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1361 Inst.addOperand(MCOperand::createReg(Reg)); 1362 return MCDisassembler::Success; 1363 } 1364 1365 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1366 unsigned RegNo, 1367 uint64_t Address, 1368 const void *Decoder) { 1369 if (RegNo > 31) 1370 return MCDisassembler::Fail; 1371 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1372 Inst.addOperand(MCOperand::createReg(Reg)); 1373 return MCDisassembler::Success; 1374 } 1375 1376 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1377 unsigned RegNo, 1378 uint64_t Address, 1379 const void *Decoder) { 1380 if (RegNo > 7) 1381 return MCDisassembler::Fail; 1382 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1383 Inst.addOperand(MCOperand::createReg(Reg)); 1384 return MCDisassembler::Success; 1385 } 1386 1387 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1388 uint64_t Address, 1389 const void *Decoder) { 1390 if (RegNo > 31) 1391 return MCDisassembler::Fail; 1392 1393 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1394 Inst.addOperand(MCOperand::createReg(Reg)); 1395 return MCDisassembler::Success; 1396 } 1397 1398 static DecodeStatus DecodeMem(MCInst &Inst, 1399 unsigned Insn, 1400 uint64_t Address, 1401 const void *Decoder) { 1402 int Offset = SignExtend32<16>(Insn & 0xffff); 1403 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1404 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1405 1406 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1407 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1408 1409 if (Inst.getOpcode() == Mips::SC || 1410 Inst.getOpcode() == Mips::SCD) 1411 Inst.addOperand(MCOperand::createReg(Reg)); 1412 1413 Inst.addOperand(MCOperand::createReg(Reg)); 1414 Inst.addOperand(MCOperand::createReg(Base)); 1415 Inst.addOperand(MCOperand::createImm(Offset)); 1416 1417 return MCDisassembler::Success; 1418 } 1419 1420 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1421 unsigned Insn, 1422 uint64_t Address, 1423 const void *Decoder) { 1424 int Offset = SignExtend32<9>(Insn >> 7); 1425 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1426 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1427 1428 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1429 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1430 1431 if (Inst.getOpcode() == Mips::SCE) 1432 Inst.addOperand(MCOperand::createReg(Reg)); 1433 1434 Inst.addOperand(MCOperand::createReg(Reg)); 1435 Inst.addOperand(MCOperand::createReg(Base)); 1436 Inst.addOperand(MCOperand::createImm(Offset)); 1437 1438 return MCDisassembler::Success; 1439 } 1440 1441 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1442 unsigned Insn, 1443 uint64_t Address, 1444 const void *Decoder) { 1445 int Offset = SignExtend32<9>(Insn & 0x1ff); 1446 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1447 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1448 1449 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1450 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1451 1452 Inst.addOperand(MCOperand::createReg(Reg)); 1453 Inst.addOperand(MCOperand::createReg(Base)); 1454 Inst.addOperand(MCOperand::createImm(Offset)); 1455 1456 return MCDisassembler::Success; 1457 } 1458 1459 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1460 unsigned Insn, 1461 uint64_t Address, 1462 const void *Decoder) { 1463 int Offset = SignExtend32<16>(Insn & 0xffff); 1464 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1465 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1466 1467 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1468 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1469 1470 Inst.addOperand(MCOperand::createReg(Reg)); 1471 Inst.addOperand(MCOperand::createReg(Base)); 1472 Inst.addOperand(MCOperand::createImm(Offset)); 1473 1474 return MCDisassembler::Success; 1475 } 1476 1477 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1478 unsigned Insn, 1479 uint64_t Address, 1480 const void *Decoder) { 1481 int Offset = SignExtend32<16>(Insn & 0xffff); 1482 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1483 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1484 1485 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1486 1487 Inst.addOperand(MCOperand::createReg(Base)); 1488 Inst.addOperand(MCOperand::createImm(Offset)); 1489 Inst.addOperand(MCOperand::createImm(Hint)); 1490 1491 return MCDisassembler::Success; 1492 } 1493 1494 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1495 unsigned Insn, 1496 uint64_t Address, 1497 const void *Decoder) { 1498 int Offset = SignExtend32<12>(Insn & 0xfff); 1499 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1500 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1501 1502 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1503 1504 Inst.addOperand(MCOperand::createReg(Base)); 1505 Inst.addOperand(MCOperand::createImm(Offset)); 1506 Inst.addOperand(MCOperand::createImm(Hint)); 1507 1508 return MCDisassembler::Success; 1509 } 1510 1511 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1512 unsigned Insn, 1513 uint64_t Address, 1514 const void *Decoder) { 1515 int Offset = SignExtend32<9>(Insn & 0x1ff); 1516 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1517 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1518 1519 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1520 1521 Inst.addOperand(MCOperand::createReg(Base)); 1522 Inst.addOperand(MCOperand::createImm(Offset)); 1523 Inst.addOperand(MCOperand::createImm(Hint)); 1524 1525 return MCDisassembler::Success; 1526 } 1527 1528 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1529 unsigned Insn, 1530 uint64_t Address, 1531 const void *Decoder) { 1532 int Offset = SignExtend32<9>(Insn >> 7); 1533 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1534 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1535 1536 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1537 1538 Inst.addOperand(MCOperand::createReg(Base)); 1539 Inst.addOperand(MCOperand::createImm(Offset)); 1540 Inst.addOperand(MCOperand::createImm(Hint)); 1541 1542 return MCDisassembler::Success; 1543 } 1544 1545 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1546 unsigned Insn, 1547 uint64_t Address, 1548 const void *Decoder) { 1549 int Offset = SignExtend32<9>(Insn & 0x1ff); 1550 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1551 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1552 1553 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1554 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1555 1556 Inst.addOperand(MCOperand::createReg(Reg)); 1557 Inst.addOperand(MCOperand::createReg(Base)); 1558 Inst.addOperand(MCOperand::createImm(Offset)); 1559 1560 return MCDisassembler::Success; 1561 } 1562 1563 static DecodeStatus DecodeSyncI(MCInst &Inst, 1564 unsigned Insn, 1565 uint64_t Address, 1566 const void *Decoder) { 1567 int Offset = SignExtend32<16>(Insn & 0xffff); 1568 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1569 1570 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1571 1572 Inst.addOperand(MCOperand::createReg(Base)); 1573 Inst.addOperand(MCOperand::createImm(Offset)); 1574 1575 return MCDisassembler::Success; 1576 } 1577 1578 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1579 unsigned Insn, 1580 uint64_t Address, 1581 const void *Decoder) { 1582 int Immediate = SignExtend32<16>(Insn & 0xffff); 1583 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1584 1585 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1586 1587 Inst.addOperand(MCOperand::createReg(Base)); 1588 Inst.addOperand(MCOperand::createImm(Immediate)); 1589 1590 return MCDisassembler::Success; 1591 } 1592 1593 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1594 uint64_t Address, const void *Decoder) { 1595 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1596 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1597 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1598 1599 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1600 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1601 1602 Inst.addOperand(MCOperand::createReg(Reg)); 1603 Inst.addOperand(MCOperand::createReg(Base)); 1604 1605 // The immediate field of an LD/ST instruction is scaled which means it must 1606 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1607 // data format. 1608 // .b - 1 byte 1609 // .h - 2 bytes 1610 // .w - 4 bytes 1611 // .d - 8 bytes 1612 switch(Inst.getOpcode()) 1613 { 1614 default: 1615 assert (0 && "Unexpected instruction"); 1616 return MCDisassembler::Fail; 1617 break; 1618 case Mips::LD_B: 1619 case Mips::ST_B: 1620 Inst.addOperand(MCOperand::createImm(Offset)); 1621 break; 1622 case Mips::LD_H: 1623 case Mips::ST_H: 1624 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1625 break; 1626 case Mips::LD_W: 1627 case Mips::ST_W: 1628 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1629 break; 1630 case Mips::LD_D: 1631 case Mips::ST_D: 1632 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1633 break; 1634 } 1635 1636 return MCDisassembler::Success; 1637 } 1638 1639 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1640 unsigned Insn, 1641 uint64_t Address, 1642 const void *Decoder) { 1643 unsigned Offset = Insn & 0xf; 1644 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1645 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1646 1647 switch (Inst.getOpcode()) { 1648 case Mips::LBU16_MM: 1649 case Mips::LHU16_MM: 1650 case Mips::LW16_MM: 1651 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1652 == MCDisassembler::Fail) 1653 return MCDisassembler::Fail; 1654 break; 1655 case Mips::SB16_MM: 1656 case Mips::SB16_MMR6: 1657 case Mips::SH16_MM: 1658 case Mips::SH16_MMR6: 1659 case Mips::SW16_MM: 1660 case Mips::SW16_MMR6: 1661 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1662 == MCDisassembler::Fail) 1663 return MCDisassembler::Fail; 1664 break; 1665 } 1666 1667 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1668 == MCDisassembler::Fail) 1669 return MCDisassembler::Fail; 1670 1671 switch (Inst.getOpcode()) { 1672 case Mips::LBU16_MM: 1673 if (Offset == 0xf) 1674 Inst.addOperand(MCOperand::createImm(-1)); 1675 else 1676 Inst.addOperand(MCOperand::createImm(Offset)); 1677 break; 1678 case Mips::SB16_MM: 1679 case Mips::SB16_MMR6: 1680 Inst.addOperand(MCOperand::createImm(Offset)); 1681 break; 1682 case Mips::LHU16_MM: 1683 case Mips::SH16_MM: 1684 case Mips::SH16_MMR6: 1685 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1686 break; 1687 case Mips::LW16_MM: 1688 case Mips::SW16_MM: 1689 case Mips::SW16_MMR6: 1690 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1691 break; 1692 } 1693 1694 return MCDisassembler::Success; 1695 } 1696 1697 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1698 unsigned Insn, 1699 uint64_t Address, 1700 const void *Decoder) { 1701 unsigned Offset = Insn & 0x1F; 1702 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1703 1704 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1705 1706 Inst.addOperand(MCOperand::createReg(Reg)); 1707 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1708 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1709 1710 return MCDisassembler::Success; 1711 } 1712 1713 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1714 unsigned Insn, 1715 uint64_t Address, 1716 const void *Decoder) { 1717 unsigned Offset = Insn & 0x7F; 1718 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1719 1720 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1721 1722 Inst.addOperand(MCOperand::createReg(Reg)); 1723 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1724 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1725 1726 return MCDisassembler::Success; 1727 } 1728 1729 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1730 unsigned Insn, 1731 uint64_t Address, 1732 const void *Decoder) { 1733 int Offset; 1734 switch (Inst.getOpcode()) { 1735 case Mips::LWM16_MMR6: 1736 case Mips::SWM16_MMR6: 1737 Offset = fieldFromInstruction(Insn, 4, 4); 1738 break; 1739 default: 1740 Offset = SignExtend32<4>(Insn & 0xf); 1741 break; 1742 } 1743 1744 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1745 == MCDisassembler::Fail) 1746 return MCDisassembler::Fail; 1747 1748 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1749 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1750 1751 return MCDisassembler::Success; 1752 } 1753 1754 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1755 unsigned Insn, 1756 uint64_t Address, 1757 const void *Decoder) { 1758 int Offset = SignExtend32<9>(Insn & 0x1ff); 1759 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1760 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1761 1762 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1763 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1764 1765 if (Inst.getOpcode() == Mips::SCE_MM) 1766 Inst.addOperand(MCOperand::createReg(Reg)); 1767 1768 Inst.addOperand(MCOperand::createReg(Reg)); 1769 Inst.addOperand(MCOperand::createReg(Base)); 1770 Inst.addOperand(MCOperand::createImm(Offset)); 1771 1772 return MCDisassembler::Success; 1773 } 1774 1775 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1776 unsigned Insn, 1777 uint64_t Address, 1778 const void *Decoder) { 1779 int Offset = SignExtend32<12>(Insn & 0x0fff); 1780 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1781 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1782 1783 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1784 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1785 1786 switch (Inst.getOpcode()) { 1787 case Mips::SWM32_MM: 1788 case Mips::LWM32_MM: 1789 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1790 == MCDisassembler::Fail) 1791 return MCDisassembler::Fail; 1792 Inst.addOperand(MCOperand::createReg(Base)); 1793 Inst.addOperand(MCOperand::createImm(Offset)); 1794 break; 1795 case Mips::SC_MM: 1796 Inst.addOperand(MCOperand::createReg(Reg)); 1797 LLVM_FALLTHROUGH; 1798 default: 1799 Inst.addOperand(MCOperand::createReg(Reg)); 1800 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1801 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1802 Inst.addOperand(MCOperand::createReg(Reg+1)); 1803 1804 Inst.addOperand(MCOperand::createReg(Base)); 1805 Inst.addOperand(MCOperand::createImm(Offset)); 1806 } 1807 1808 return MCDisassembler::Success; 1809 } 1810 1811 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1812 unsigned Insn, 1813 uint64_t Address, 1814 const void *Decoder) { 1815 int Offset = SignExtend32<16>(Insn & 0xffff); 1816 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1817 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1818 1819 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1820 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1821 1822 Inst.addOperand(MCOperand::createReg(Reg)); 1823 Inst.addOperand(MCOperand::createReg(Base)); 1824 Inst.addOperand(MCOperand::createImm(Offset)); 1825 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeFMem(MCInst &Inst, 1830 unsigned Insn, 1831 uint64_t Address, 1832 const void *Decoder) { 1833 int Offset = SignExtend32<16>(Insn & 0xffff); 1834 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1835 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1836 1837 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1838 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1839 1840 Inst.addOperand(MCOperand::createReg(Reg)); 1841 Inst.addOperand(MCOperand::createReg(Base)); 1842 Inst.addOperand(MCOperand::createImm(Offset)); 1843 1844 return MCDisassembler::Success; 1845 } 1846 1847 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1848 uint64_t Address, const void *Decoder) { 1849 // This function is the same as DecodeFMem but with the Reg and Base fields 1850 // swapped according to microMIPS spec. 1851 int Offset = SignExtend32<16>(Insn & 0xffff); 1852 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1853 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1854 1855 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1856 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1857 1858 Inst.addOperand(MCOperand::createReg(Reg)); 1859 Inst.addOperand(MCOperand::createReg(Base)); 1860 Inst.addOperand(MCOperand::createImm(Offset)); 1861 1862 return MCDisassembler::Success; 1863 } 1864 1865 static DecodeStatus DecodeFMem2(MCInst &Inst, 1866 unsigned Insn, 1867 uint64_t Address, 1868 const void *Decoder) { 1869 int Offset = SignExtend32<16>(Insn & 0xffff); 1870 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1871 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1872 1873 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1874 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1875 1876 Inst.addOperand(MCOperand::createReg(Reg)); 1877 Inst.addOperand(MCOperand::createReg(Base)); 1878 Inst.addOperand(MCOperand::createImm(Offset)); 1879 1880 return MCDisassembler::Success; 1881 } 1882 1883 static DecodeStatus DecodeFMem3(MCInst &Inst, 1884 unsigned Insn, 1885 uint64_t Address, 1886 const void *Decoder) { 1887 int Offset = SignExtend32<16>(Insn & 0xffff); 1888 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1889 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1890 1891 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1892 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1893 1894 Inst.addOperand(MCOperand::createReg(Reg)); 1895 Inst.addOperand(MCOperand::createReg(Base)); 1896 Inst.addOperand(MCOperand::createImm(Offset)); 1897 1898 return MCDisassembler::Success; 1899 } 1900 1901 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1902 unsigned Insn, 1903 uint64_t Address, 1904 const void *Decoder) { 1905 int Offset = SignExtend32<11>(Insn & 0x07ff); 1906 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1907 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1908 1909 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1910 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1911 1912 Inst.addOperand(MCOperand::createReg(Reg)); 1913 Inst.addOperand(MCOperand::createReg(Base)); 1914 Inst.addOperand(MCOperand::createImm(Offset)); 1915 1916 return MCDisassembler::Success; 1917 } 1918 1919 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1920 uint64_t Address, const void *Decoder) { 1921 int Offset = SignExtend32<11>(Insn & 0x07ff); 1922 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1923 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1924 1925 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1926 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1927 1928 Inst.addOperand(MCOperand::createReg(Reg)); 1929 Inst.addOperand(MCOperand::createReg(Base)); 1930 Inst.addOperand(MCOperand::createImm(Offset)); 1931 1932 return MCDisassembler::Success; 1933 } 1934 1935 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1936 unsigned Insn, 1937 uint64_t Address, 1938 const void *Decoder) { 1939 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1940 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1941 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1942 1943 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1944 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1945 1946 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1947 Inst.addOperand(MCOperand::createReg(Rt)); 1948 } 1949 1950 Inst.addOperand(MCOperand::createReg(Rt)); 1951 Inst.addOperand(MCOperand::createReg(Base)); 1952 Inst.addOperand(MCOperand::createImm(Offset)); 1953 1954 return MCDisassembler::Success; 1955 } 1956 1957 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1958 unsigned RegNo, 1959 uint64_t Address, 1960 const void *Decoder) { 1961 // Currently only hardware register 29 is supported. 1962 if (RegNo != 29) 1963 return MCDisassembler::Fail; 1964 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1965 return MCDisassembler::Success; 1966 } 1967 1968 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1969 unsigned RegNo, 1970 uint64_t Address, 1971 const void *Decoder) { 1972 if (RegNo > 30 || RegNo %2) 1973 return MCDisassembler::Fail; 1974 1975 ; 1976 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1977 Inst.addOperand(MCOperand::createReg(Reg)); 1978 return MCDisassembler::Success; 1979 } 1980 1981 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1982 unsigned RegNo, 1983 uint64_t Address, 1984 const void *Decoder) { 1985 if (RegNo >= 4) 1986 return MCDisassembler::Fail; 1987 1988 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1989 Inst.addOperand(MCOperand::createReg(Reg)); 1990 return MCDisassembler::Success; 1991 } 1992 1993 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1994 unsigned RegNo, 1995 uint64_t Address, 1996 const void *Decoder) { 1997 if (RegNo >= 4) 1998 return MCDisassembler::Fail; 1999 2000 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2001 Inst.addOperand(MCOperand::createReg(Reg)); 2002 return MCDisassembler::Success; 2003 } 2004 2005 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2006 unsigned RegNo, 2007 uint64_t Address, 2008 const void *Decoder) { 2009 if (RegNo >= 4) 2010 return MCDisassembler::Fail; 2011 2012 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2013 Inst.addOperand(MCOperand::createReg(Reg)); 2014 return MCDisassembler::Success; 2015 } 2016 2017 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2018 unsigned RegNo, 2019 uint64_t Address, 2020 const void *Decoder) { 2021 if (RegNo > 31) 2022 return MCDisassembler::Fail; 2023 2024 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2025 Inst.addOperand(MCOperand::createReg(Reg)); 2026 return MCDisassembler::Success; 2027 } 2028 2029 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2030 unsigned RegNo, 2031 uint64_t Address, 2032 const void *Decoder) { 2033 if (RegNo > 31) 2034 return MCDisassembler::Fail; 2035 2036 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2037 Inst.addOperand(MCOperand::createReg(Reg)); 2038 return MCDisassembler::Success; 2039 } 2040 2041 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2042 unsigned RegNo, 2043 uint64_t Address, 2044 const void *Decoder) { 2045 if (RegNo > 31) 2046 return MCDisassembler::Fail; 2047 2048 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2049 Inst.addOperand(MCOperand::createReg(Reg)); 2050 return MCDisassembler::Success; 2051 } 2052 2053 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2054 unsigned RegNo, 2055 uint64_t Address, 2056 const void *Decoder) { 2057 if (RegNo > 31) 2058 return MCDisassembler::Fail; 2059 2060 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2061 Inst.addOperand(MCOperand::createReg(Reg)); 2062 return MCDisassembler::Success; 2063 } 2064 2065 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2066 unsigned RegNo, 2067 uint64_t Address, 2068 const void *Decoder) { 2069 if (RegNo > 7) 2070 return MCDisassembler::Fail; 2071 2072 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2073 Inst.addOperand(MCOperand::createReg(Reg)); 2074 return MCDisassembler::Success; 2075 } 2076 2077 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2078 unsigned RegNo, 2079 uint64_t Address, 2080 const void *Decoder) { 2081 if (RegNo > 31) 2082 return MCDisassembler::Fail; 2083 2084 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2085 Inst.addOperand(MCOperand::createReg(Reg)); 2086 return MCDisassembler::Success; 2087 } 2088 2089 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2090 unsigned RegNo, 2091 uint64_t Address, 2092 const void *Decoder) { 2093 if (RegNo > 31) 2094 return MCDisassembler::Fail; 2095 2096 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2097 Inst.addOperand(MCOperand::createReg(Reg)); 2098 return MCDisassembler::Success; 2099 } 2100 2101 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2102 unsigned Offset, 2103 uint64_t Address, 2104 const void *Decoder) { 2105 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2106 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2107 return MCDisassembler::Success; 2108 } 2109 2110 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2111 unsigned Offset, 2112 uint64_t Address, 2113 const void *Decoder) { 2114 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2115 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2116 return MCDisassembler::Success; 2117 } 2118 2119 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2120 unsigned Insn, 2121 uint64_t Address, 2122 const void *Decoder) { 2123 2124 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2125 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2126 return MCDisassembler::Success; 2127 } 2128 2129 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2130 unsigned Offset, 2131 uint64_t Address, 2132 const void *Decoder) { 2133 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2134 2135 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2136 return MCDisassembler::Success; 2137 } 2138 2139 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2140 unsigned Offset, 2141 uint64_t Address, 2142 const void *Decoder) { 2143 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2144 2145 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2146 return MCDisassembler::Success; 2147 } 2148 2149 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2150 unsigned Offset, 2151 uint64_t Address, 2152 const void *Decoder) { 2153 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2154 2155 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2156 return MCDisassembler::Success; 2157 } 2158 2159 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2160 unsigned Offset, 2161 uint64_t Address, 2162 const void *Decoder) { 2163 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 2164 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2165 return MCDisassembler::Success; 2166 } 2167 2168 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2169 unsigned Offset, 2170 uint64_t Address, 2171 const void *Decoder) { 2172 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 2173 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2174 return MCDisassembler::Success; 2175 } 2176 2177 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2178 unsigned Offset, 2179 uint64_t Address, 2180 const void *Decoder) { 2181 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2182 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2183 return MCDisassembler::Success; 2184 } 2185 2186 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2187 unsigned Offset, 2188 uint64_t Address, 2189 const void *Decoder) { 2190 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 2191 2192 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2193 return MCDisassembler::Success; 2194 } 2195 2196 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2197 unsigned Insn, 2198 uint64_t Address, 2199 const void *Decoder) { 2200 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2201 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2202 return MCDisassembler::Success; 2203 } 2204 2205 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2206 unsigned Value, 2207 uint64_t Address, 2208 const void *Decoder) { 2209 if (Value == 0) 2210 Inst.addOperand(MCOperand::createImm(1)); 2211 else if (Value == 0x7) 2212 Inst.addOperand(MCOperand::createImm(-1)); 2213 else 2214 Inst.addOperand(MCOperand::createImm(Value << 2)); 2215 return MCDisassembler::Success; 2216 } 2217 2218 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2219 unsigned Value, 2220 uint64_t Address, 2221 const void *Decoder) { 2222 if (Value == 0x7F) 2223 Inst.addOperand(MCOperand::createImm(-1)); 2224 else 2225 Inst.addOperand(MCOperand::createImm(Value)); 2226 return MCDisassembler::Success; 2227 } 2228 2229 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2230 unsigned Value, 2231 uint64_t Address, 2232 const void *Decoder) { 2233 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2234 return MCDisassembler::Success; 2235 } 2236 2237 template <unsigned Bits, int Offset, int Scale> 2238 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2239 uint64_t Address, 2240 const void *Decoder) { 2241 Value &= ((1 << Bits) - 1); 2242 Value *= Scale; 2243 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2244 return MCDisassembler::Success; 2245 } 2246 2247 template <unsigned Bits, int Offset, int ScaleBy> 2248 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2249 uint64_t Address, 2250 const void *Decoder) { 2251 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2252 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2253 return MCDisassembler::Success; 2254 } 2255 2256 static DecodeStatus DecodeInsSize(MCInst &Inst, 2257 unsigned Insn, 2258 uint64_t Address, 2259 const void *Decoder) { 2260 // First we need to grab the pos(lsb) from MCInst. 2261 int Pos = Inst.getOperand(2).getImm(); 2262 int Size = (int) Insn - Pos + 1; 2263 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2264 return MCDisassembler::Success; 2265 } 2266 2267 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2268 uint64_t Address, const void *Decoder) { 2269 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2270 return MCDisassembler::Success; 2271 } 2272 2273 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2274 uint64_t Address, const void *Decoder) { 2275 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2276 return MCDisassembler::Success; 2277 } 2278 2279 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2280 uint64_t Address, const void *Decoder) { 2281 int32_t DecodedValue; 2282 switch (Insn) { 2283 case 0: DecodedValue = 256; break; 2284 case 1: DecodedValue = 257; break; 2285 case 510: DecodedValue = -258; break; 2286 case 511: DecodedValue = -257; break; 2287 default: DecodedValue = SignExtend32<9>(Insn); break; 2288 } 2289 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2290 return MCDisassembler::Success; 2291 } 2292 2293 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2294 uint64_t Address, const void *Decoder) { 2295 // Insn must be >= 0, since it is unsigned that condition is always true. 2296 assert(Insn < 16); 2297 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2298 255, 32768, 65535}; 2299 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2300 return MCDisassembler::Success; 2301 } 2302 2303 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2304 unsigned Insn, 2305 uint64_t Address, 2306 const void *Decoder) { 2307 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2308 Mips::S6, Mips::S7, Mips::FP}; 2309 unsigned RegNum; 2310 2311 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2312 2313 // Empty register lists are not allowed. 2314 if (RegLst == 0) 2315 return MCDisassembler::Fail; 2316 2317 RegNum = RegLst & 0xf; 2318 2319 // RegLst values 10-15, and 26-31 are reserved. 2320 if (RegNum > 9) 2321 return MCDisassembler::Fail; 2322 2323 for (unsigned i = 0; i < RegNum; i++) 2324 Inst.addOperand(MCOperand::createReg(Regs[i])); 2325 2326 if (RegLst & 0x10) 2327 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2328 2329 return MCDisassembler::Success; 2330 } 2331 2332 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2333 uint64_t Address, 2334 const void *Decoder) { 2335 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2336 unsigned RegLst; 2337 switch(Inst.getOpcode()) { 2338 default: 2339 RegLst = fieldFromInstruction(Insn, 4, 2); 2340 break; 2341 case Mips::LWM16_MMR6: 2342 case Mips::SWM16_MMR6: 2343 RegLst = fieldFromInstruction(Insn, 8, 2); 2344 break; 2345 } 2346 unsigned RegNum = RegLst & 0x3; 2347 2348 for (unsigned i = 0; i <= RegNum; i++) 2349 Inst.addOperand(MCOperand::createReg(Regs[i])); 2350 2351 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2352 2353 return MCDisassembler::Success; 2354 } 2355 2356 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2357 uint64_t Address, const void *Decoder) { 2358 2359 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2360 2361 switch (RegPair) { 2362 default: 2363 return MCDisassembler::Fail; 2364 case 0: 2365 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2366 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2367 break; 2368 case 1: 2369 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2370 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2371 break; 2372 case 2: 2373 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2374 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2375 break; 2376 case 3: 2377 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2378 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2379 break; 2380 case 4: 2381 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2382 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2383 break; 2384 case 5: 2385 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2386 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2387 break; 2388 case 6: 2389 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2390 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2391 break; 2392 case 7: 2393 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2394 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2395 break; 2396 } 2397 2398 return MCDisassembler::Success; 2399 } 2400 2401 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2402 uint64_t Address, const void *Decoder) { 2403 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2404 return MCDisassembler::Success; 2405 } 2406 2407 template <typename InsnType> 2408 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2409 uint64_t Address, 2410 const void *Decoder) { 2411 // We have: 2412 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2413 // Invalid if rt == 0 2414 // BGTZALC_MMR6 if rs == 0 && rt != 0 2415 // BLTZALC_MMR6 if rs != 0 && rs == rt 2416 // BLTUC_MMR6 if rs != 0 && rs != rt 2417 2418 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2419 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2420 InsnType Imm = 0; 2421 bool HasRs = false; 2422 bool HasRt = false; 2423 2424 if (Rt == 0) 2425 return MCDisassembler::Fail; 2426 else if (Rs == 0) { 2427 MI.setOpcode(Mips::BGTZALC_MMR6); 2428 HasRt = true; 2429 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2430 } 2431 else if (Rs == Rt) { 2432 MI.setOpcode(Mips::BLTZALC_MMR6); 2433 HasRs = true; 2434 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2435 } 2436 else { 2437 MI.setOpcode(Mips::BLTUC_MMR6); 2438 HasRs = true; 2439 HasRt = true; 2440 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2441 } 2442 2443 if (HasRs) 2444 MI.addOperand( 2445 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2446 2447 if (HasRt) 2448 MI.addOperand( 2449 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2450 2451 MI.addOperand(MCOperand::createImm(Imm)); 2452 2453 return MCDisassembler::Success; 2454 } 2455 2456 template <typename InsnType> 2457 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2458 uint64_t Address, 2459 const void *Decoder) { 2460 // We have: 2461 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2462 // Invalid if rt == 0 2463 // BLEZALC_MMR6 if rs == 0 && rt != 0 2464 // BGEZALC_MMR6 if rs == rt && rt != 0 2465 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2466 2467 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2468 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2469 InsnType Imm = 0; 2470 bool HasRs = false; 2471 2472 if (Rt == 0) 2473 return MCDisassembler::Fail; 2474 else if (Rs == 0) { 2475 MI.setOpcode(Mips::BLEZALC_MMR6); 2476 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2477 } 2478 else if (Rs == Rt) { 2479 MI.setOpcode(Mips::BGEZALC_MMR6); 2480 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2481 } 2482 else { 2483 HasRs = true; 2484 MI.setOpcode(Mips::BGEUC_MMR6); 2485 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2486 } 2487 2488 if (HasRs) 2489 MI.addOperand( 2490 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2491 MI.addOperand( 2492 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2493 2494 MI.addOperand(MCOperand::createImm(Imm)); 2495 2496 return MCDisassembler::Success; 2497 } 2498