1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 49 50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 51 52 bool hasCOP3() const { 53 // Only present in MIPS-I and MIPS-II 54 return !hasMips32() && !hasMips3(); 55 } 56 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 }; 62 63 } // end anonymous namespace 64 65 // Forward declare these because the autogenerated code will reference them. 66 // Definitions are further down. 67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 68 unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 78 unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 132 unsigned Insn, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 142 unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 147 unsigned RegNo, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 192 unsigned Offset, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 202 unsigned Offset, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 212 // shifted left by 1 bit. 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 235 unsigned Insn, 236 uint64_t Address, 237 const void *Decoder); 238 239 static DecodeStatus DecodeMem(MCInst &Inst, 240 unsigned Insn, 241 uint64_t Address, 242 const void *Decoder); 243 244 static DecodeStatus DecodeMemEVA(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 249 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 250 unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 254 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 255 unsigned Insn, 256 uint64_t Address, 257 const void *Decoder); 258 259 static DecodeStatus DecodeCacheOp(MCInst &Inst, 260 unsigned Insn, 261 uint64_t Address, 262 const void *Decoder); 263 264 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 265 unsigned Insn, 266 uint64_t Address, 267 const void *Decoder); 268 269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 270 unsigned Insn, 271 uint64_t Address, 272 const void *Decoder); 273 274 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeSyncI(MCInst &Inst, 285 unsigned Insn, 286 uint64_t Address, 287 const void *Decoder); 288 289 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 292 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 313 unsigned Insn, 314 uint64_t Address, 315 const void *Decoder); 316 317 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 318 unsigned Insn, 319 uint64_t Address, 320 const void *Decoder); 321 322 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 323 unsigned Insn, 324 uint64_t Address, 325 const void *Decoder); 326 327 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 336 uint64_t Address, 337 const void *Decoder); 338 339 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 349 unsigned Value, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 354 unsigned Value, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 359 unsigned Value, 360 uint64_t Address, 361 const void *Decoder); 362 363 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 364 unsigned Value, 365 uint64_t Address, 366 const void *Decoder); 367 368 static DecodeStatus DecodeSimm4(MCInst &Inst, 369 unsigned Value, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeSimm16(MCInst &Inst, 374 unsigned Insn, 375 uint64_t Address, 376 const void *Decoder); 377 378 // Decode the immediate field of an LSA instruction which 379 // is off by one. 380 static DecodeStatus DecodeLSAImm(MCInst &Inst, 381 unsigned Insn, 382 uint64_t Address, 383 const void *Decoder); 384 385 static DecodeStatus DecodeInsSize(MCInst &Inst, 386 unsigned Insn, 387 uint64_t Address, 388 const void *Decoder); 389 390 static DecodeStatus DecodeExtSize(MCInst &Inst, 391 unsigned Insn, 392 uint64_t Address, 393 const void *Decoder); 394 395 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 398 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 399 uint64_t Address, const void *Decoder); 400 401 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 402 uint64_t Address, const void *Decoder); 403 404 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 405 uint64_t Address, const void *Decoder); 406 407 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 408 uint64_t Address, const void *Decoder); 409 410 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 411 uint64_t Address, const void *Decoder); 412 413 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 414 /// handle. 415 template <typename InsnType> 416 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 417 const void *Decoder); 418 419 template <typename InsnType> 420 static DecodeStatus 421 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 422 const void *Decoder); 423 424 template <typename InsnType> 425 static DecodeStatus 426 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 427 const void *Decoder); 428 429 template <typename InsnType> 430 static DecodeStatus 431 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 432 const void *Decoder); 433 434 template <typename InsnType> 435 static DecodeStatus 436 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 437 const void *Decoder); 438 439 template <typename InsnType> 440 static DecodeStatus 441 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 442 const void *Decoder); 443 444 template <typename InsnType> 445 static DecodeStatus 446 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 447 const void *Decoder); 448 449 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 450 uint64_t Address, 451 const void *Decoder); 452 453 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 454 uint64_t Address, 455 const void *Decoder); 456 457 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 458 uint64_t Address, 459 const void *Decoder); 460 461 namespace llvm { 462 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 463 TheMips64elTarget; 464 } 465 466 static MCDisassembler *createMipsDisassembler( 467 const Target &T, 468 const MCSubtargetInfo &STI, 469 MCContext &Ctx) { 470 return new MipsDisassembler(STI, Ctx, true); 471 } 472 473 static MCDisassembler *createMipselDisassembler( 474 const Target &T, 475 const MCSubtargetInfo &STI, 476 MCContext &Ctx) { 477 return new MipsDisassembler(STI, Ctx, false); 478 } 479 480 extern "C" void LLVMInitializeMipsDisassembler() { 481 // Register the disassembler. 482 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 483 createMipsDisassembler); 484 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 485 createMipselDisassembler); 486 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 487 createMipsDisassembler); 488 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 489 createMipselDisassembler); 490 } 491 492 #include "MipsGenDisassemblerTables.inc" 493 494 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 495 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 496 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 497 return *(RegInfo->getRegClass(RC).begin() + RegNo); 498 } 499 500 template <typename InsnType> 501 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 502 const void *Decoder) { 503 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 504 // The size of the n field depends on the element size 505 // The register class also depends on this. 506 InsnType tmp = fieldFromInstruction(insn, 17, 5); 507 unsigned NSize = 0; 508 DecodeFN RegDecoder = nullptr; 509 if ((tmp & 0x18) == 0x00) { // INSVE_B 510 NSize = 4; 511 RegDecoder = DecodeMSA128BRegisterClass; 512 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 513 NSize = 3; 514 RegDecoder = DecodeMSA128HRegisterClass; 515 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 516 NSize = 2; 517 RegDecoder = DecodeMSA128WRegisterClass; 518 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 519 NSize = 1; 520 RegDecoder = DecodeMSA128DRegisterClass; 521 } else 522 llvm_unreachable("Invalid encoding"); 523 524 assert(NSize != 0 && RegDecoder != nullptr); 525 526 // $wd 527 tmp = fieldFromInstruction(insn, 6, 5); 528 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 529 return MCDisassembler::Fail; 530 // $wd_in 531 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 532 return MCDisassembler::Fail; 533 // $n 534 tmp = fieldFromInstruction(insn, 16, NSize); 535 MI.addOperand(MCOperand::createImm(tmp)); 536 // $ws 537 tmp = fieldFromInstruction(insn, 11, 5); 538 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 539 return MCDisassembler::Fail; 540 // $n2 541 MI.addOperand(MCOperand::createImm(0)); 542 543 return MCDisassembler::Success; 544 } 545 546 template <typename InsnType> 547 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 548 uint64_t Address, 549 const void *Decoder) { 550 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 551 // (otherwise we would have matched the ADDI instruction from the earlier 552 // ISA's instead). 553 // 554 // We have: 555 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 556 // BOVC if rs >= rt 557 // BEQZALC if rs == 0 && rt != 0 558 // BEQC if rs < rt && rs != 0 559 560 InsnType Rs = fieldFromInstruction(insn, 21, 5); 561 InsnType Rt = fieldFromInstruction(insn, 16, 5); 562 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 563 bool HasRs = false; 564 565 if (Rs >= Rt) { 566 MI.setOpcode(Mips::BOVC); 567 HasRs = true; 568 } else if (Rs != 0 && Rs < Rt) { 569 MI.setOpcode(Mips::BEQC); 570 HasRs = true; 571 } else 572 MI.setOpcode(Mips::BEQZALC); 573 574 if (HasRs) 575 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 576 Rs))); 577 578 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 579 Rt))); 580 MI.addOperand(MCOperand::createImm(Imm)); 581 582 return MCDisassembler::Success; 583 } 584 585 template <typename InsnType> 586 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 587 uint64_t Address, 588 const void *Decoder) { 589 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 590 // (otherwise we would have matched the ADDI instruction from the earlier 591 // ISA's instead). 592 // 593 // We have: 594 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 595 // BNVC if rs >= rt 596 // BNEZALC if rs == 0 && rt != 0 597 // BNEC if rs < rt && rs != 0 598 599 InsnType Rs = fieldFromInstruction(insn, 21, 5); 600 InsnType Rt = fieldFromInstruction(insn, 16, 5); 601 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 602 bool HasRs = false; 603 604 if (Rs >= Rt) { 605 MI.setOpcode(Mips::BNVC); 606 HasRs = true; 607 } else if (Rs != 0 && Rs < Rt) { 608 MI.setOpcode(Mips::BNEC); 609 HasRs = true; 610 } else 611 MI.setOpcode(Mips::BNEZALC); 612 613 if (HasRs) 614 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 615 Rs))); 616 617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 618 Rt))); 619 MI.addOperand(MCOperand::createImm(Imm)); 620 621 return MCDisassembler::Success; 622 } 623 624 template <typename InsnType> 625 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 626 uint64_t Address, 627 const void *Decoder) { 628 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 629 // (otherwise we would have matched the BLEZL instruction from the earlier 630 // ISA's instead). 631 // 632 // We have: 633 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 634 // Invalid if rs == 0 635 // BLEZC if rs == 0 && rt != 0 636 // BGEZC if rs == rt && rt != 0 637 // BGEC if rs != rt && rs != 0 && rt != 0 638 639 InsnType Rs = fieldFromInstruction(insn, 21, 5); 640 InsnType Rt = fieldFromInstruction(insn, 16, 5); 641 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 642 bool HasRs = false; 643 644 if (Rt == 0) 645 return MCDisassembler::Fail; 646 else if (Rs == 0) 647 MI.setOpcode(Mips::BLEZC); 648 else if (Rs == Rt) 649 MI.setOpcode(Mips::BGEZC); 650 else { 651 HasRs = true; 652 MI.setOpcode(Mips::BGEC); 653 } 654 655 if (HasRs) 656 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 657 Rs))); 658 659 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 660 Rt))); 661 662 MI.addOperand(MCOperand::createImm(Imm)); 663 664 return MCDisassembler::Success; 665 } 666 667 template <typename InsnType> 668 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 669 uint64_t Address, 670 const void *Decoder) { 671 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 672 // (otherwise we would have matched the BGTZL instruction from the earlier 673 // ISA's instead). 674 // 675 // We have: 676 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 677 // Invalid if rs == 0 678 // BGTZC if rs == 0 && rt != 0 679 // BLTZC if rs == rt && rt != 0 680 // BLTC if rs != rt && rs != 0 && rt != 0 681 682 bool HasRs = false; 683 684 InsnType Rs = fieldFromInstruction(insn, 21, 5); 685 InsnType Rt = fieldFromInstruction(insn, 16, 5); 686 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 687 688 if (Rt == 0) 689 return MCDisassembler::Fail; 690 else if (Rs == 0) 691 MI.setOpcode(Mips::BGTZC); 692 else if (Rs == Rt) 693 MI.setOpcode(Mips::BLTZC); 694 else { 695 MI.setOpcode(Mips::BLTC); 696 HasRs = true; 697 } 698 699 if (HasRs) 700 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 701 Rs))); 702 703 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 704 Rt))); 705 706 MI.addOperand(MCOperand::createImm(Imm)); 707 708 return MCDisassembler::Success; 709 } 710 711 template <typename InsnType> 712 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 713 uint64_t Address, 714 const void *Decoder) { 715 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 716 // (otherwise we would have matched the BGTZ instruction from the earlier 717 // ISA's instead). 718 // 719 // We have: 720 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 721 // BGTZ if rt == 0 722 // BGTZALC if rs == 0 && rt != 0 723 // BLTZALC if rs != 0 && rs == rt 724 // BLTUC if rs != 0 && rs != rt 725 726 InsnType Rs = fieldFromInstruction(insn, 21, 5); 727 InsnType Rt = fieldFromInstruction(insn, 16, 5); 728 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 729 bool HasRs = false; 730 bool HasRt = false; 731 732 if (Rt == 0) { 733 MI.setOpcode(Mips::BGTZ); 734 HasRs = true; 735 } else if (Rs == 0) { 736 MI.setOpcode(Mips::BGTZALC); 737 HasRt = true; 738 } else if (Rs == Rt) { 739 MI.setOpcode(Mips::BLTZALC); 740 HasRs = true; 741 } else { 742 MI.setOpcode(Mips::BLTUC); 743 HasRs = true; 744 HasRt = true; 745 } 746 747 if (HasRs) 748 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 749 Rs))); 750 751 if (HasRt) 752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 753 Rt))); 754 755 MI.addOperand(MCOperand::createImm(Imm)); 756 757 return MCDisassembler::Success; 758 } 759 760 template <typename InsnType> 761 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 762 uint64_t Address, 763 const void *Decoder) { 764 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 765 // (otherwise we would have matched the BLEZL instruction from the earlier 766 // ISA's instead). 767 // 768 // We have: 769 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 770 // Invalid if rs == 0 771 // BLEZALC if rs == 0 && rt != 0 772 // BGEZALC if rs == rt && rt != 0 773 // BGEUC if rs != rt && rs != 0 && rt != 0 774 775 InsnType Rs = fieldFromInstruction(insn, 21, 5); 776 InsnType Rt = fieldFromInstruction(insn, 16, 5); 777 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 778 bool HasRs = false; 779 780 if (Rt == 0) 781 return MCDisassembler::Fail; 782 else if (Rs == 0) 783 MI.setOpcode(Mips::BLEZALC); 784 else if (Rs == Rt) 785 MI.setOpcode(Mips::BGEZALC); 786 else { 787 HasRs = true; 788 MI.setOpcode(Mips::BGEUC); 789 } 790 791 if (HasRs) 792 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 793 Rs))); 794 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 795 Rt))); 796 797 MI.addOperand(MCOperand::createImm(Imm)); 798 799 return MCDisassembler::Success; 800 } 801 802 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 803 /// according to the given endianess. 804 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 805 uint64_t &Size, uint32_t &Insn, 806 bool IsBigEndian) { 807 // We want to read exactly 2 Bytes of data. 808 if (Bytes.size() < 2) { 809 Size = 0; 810 return MCDisassembler::Fail; 811 } 812 813 if (IsBigEndian) { 814 Insn = (Bytes[0] << 8) | Bytes[1]; 815 } else { 816 Insn = (Bytes[1] << 8) | Bytes[0]; 817 } 818 819 return MCDisassembler::Success; 820 } 821 822 /// Read four bytes from the ArrayRef and return 32 bit word sorted 823 /// according to the given endianess 824 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 825 uint64_t &Size, uint32_t &Insn, 826 bool IsBigEndian, bool IsMicroMips) { 827 // We want to read exactly 4 Bytes of data. 828 if (Bytes.size() < 4) { 829 Size = 0; 830 return MCDisassembler::Fail; 831 } 832 833 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 834 // always precede the low 16 bits in the instruction stream (that is, they 835 // are placed at lower addresses in the instruction stream). 836 // 837 // microMIPS byte ordering: 838 // Big-endian: 0 | 1 | 2 | 3 839 // Little-endian: 1 | 0 | 3 | 2 840 841 if (IsBigEndian) { 842 // Encoded as a big-endian 32-bit word in the stream. 843 Insn = 844 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 845 } else { 846 if (IsMicroMips) { 847 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 848 (Bytes[1] << 24); 849 } else { 850 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 851 (Bytes[3] << 24); 852 } 853 } 854 855 return MCDisassembler::Success; 856 } 857 858 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 859 ArrayRef<uint8_t> Bytes, 860 uint64_t Address, 861 raw_ostream &VStream, 862 raw_ostream &CStream) const { 863 uint32_t Insn; 864 DecodeStatus Result; 865 866 if (IsMicroMips) { 867 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 868 869 if (hasMips32r6()) { 870 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 871 // Calling the auto-generated decoder function for microMIPS32R6 872 // (and microMIPS64R6) 16-bit instructions. 873 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 874 Address, this, STI); 875 if (Result != MCDisassembler::Fail) { 876 Size = 2; 877 return Result; 878 } 879 } 880 881 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 882 // Calling the auto-generated decoder function for microMIPS 16-bit 883 // instructions. 884 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 885 this, STI); 886 if (Result != MCDisassembler::Fail) { 887 Size = 2; 888 return Result; 889 } 890 891 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 892 if (Result == MCDisassembler::Fail) 893 return MCDisassembler::Fail; 894 895 if (hasMips32r6()) { 896 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 897 // Calling the auto-generated decoder function. 898 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 899 this, STI); 900 if (Result != MCDisassembler::Fail) { 901 Size = 4; 902 return Result; 903 } 904 } 905 906 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 907 // Calling the auto-generated decoder function. 908 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 909 this, STI); 910 if (Result != MCDisassembler::Fail) { 911 Size = 4; 912 return Result; 913 } 914 return MCDisassembler::Fail; 915 } 916 917 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 918 if (Result == MCDisassembler::Fail) 919 return MCDisassembler::Fail; 920 921 if (hasCOP3()) { 922 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 923 Result = 924 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 925 if (Result != MCDisassembler::Fail) { 926 Size = 4; 927 return Result; 928 } 929 } 930 931 if (hasMips32r6() && isGP64()) { 932 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 933 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 934 Address, this, STI); 935 if (Result != MCDisassembler::Fail) { 936 Size = 4; 937 return Result; 938 } 939 } 940 941 if (hasMips32r6()) { 942 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 943 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 944 Address, this, STI); 945 if (Result != MCDisassembler::Fail) { 946 Size = 4; 947 return Result; 948 } 949 } 950 951 if (hasCnMips()) { 952 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 953 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 954 Address, this, STI); 955 if (Result != MCDisassembler::Fail) { 956 Size = 4; 957 return Result; 958 } 959 } 960 961 if (isGP64()) { 962 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 963 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 964 Address, this, STI); 965 if (Result != MCDisassembler::Fail) { 966 Size = 4; 967 return Result; 968 } 969 } 970 971 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 972 // Calling the auto-generated decoder function. 973 Result = 974 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 975 if (Result != MCDisassembler::Fail) { 976 Size = 4; 977 return Result; 978 } 979 980 return MCDisassembler::Fail; 981 } 982 983 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 984 unsigned RegNo, 985 uint64_t Address, 986 const void *Decoder) { 987 988 return MCDisassembler::Fail; 989 990 } 991 992 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 993 unsigned RegNo, 994 uint64_t Address, 995 const void *Decoder) { 996 997 if (RegNo > 31) 998 return MCDisassembler::Fail; 999 1000 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1001 Inst.addOperand(MCOperand::createReg(Reg)); 1002 return MCDisassembler::Success; 1003 } 1004 1005 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1006 unsigned RegNo, 1007 uint64_t Address, 1008 const void *Decoder) { 1009 if (RegNo > 7) 1010 return MCDisassembler::Fail; 1011 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1012 Inst.addOperand(MCOperand::createReg(Reg)); 1013 return MCDisassembler::Success; 1014 } 1015 1016 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1017 unsigned RegNo, 1018 uint64_t Address, 1019 const void *Decoder) { 1020 if (RegNo > 7) 1021 return MCDisassembler::Fail; 1022 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1023 Inst.addOperand(MCOperand::createReg(Reg)); 1024 return MCDisassembler::Success; 1025 } 1026 1027 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1028 unsigned RegNo, 1029 uint64_t Address, 1030 const void *Decoder) { 1031 if (RegNo > 7) 1032 return MCDisassembler::Fail; 1033 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1034 Inst.addOperand(MCOperand::createReg(Reg)); 1035 return MCDisassembler::Success; 1036 } 1037 1038 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1039 unsigned RegNo, 1040 uint64_t Address, 1041 const void *Decoder) { 1042 if (RegNo > 31) 1043 return MCDisassembler::Fail; 1044 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1045 Inst.addOperand(MCOperand::createReg(Reg)); 1046 return MCDisassembler::Success; 1047 } 1048 1049 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1050 unsigned RegNo, 1051 uint64_t Address, 1052 const void *Decoder) { 1053 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1054 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1055 1056 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1057 } 1058 1059 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1060 unsigned RegNo, 1061 uint64_t Address, 1062 const void *Decoder) { 1063 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1064 } 1065 1066 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1067 unsigned RegNo, 1068 uint64_t Address, 1069 const void *Decoder) { 1070 if (RegNo > 31) 1071 return MCDisassembler::Fail; 1072 1073 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1074 Inst.addOperand(MCOperand::createReg(Reg)); 1075 return MCDisassembler::Success; 1076 } 1077 1078 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1079 unsigned RegNo, 1080 uint64_t Address, 1081 const void *Decoder) { 1082 if (RegNo > 31) 1083 return MCDisassembler::Fail; 1084 1085 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1086 Inst.addOperand(MCOperand::createReg(Reg)); 1087 return MCDisassembler::Success; 1088 } 1089 1090 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1091 unsigned RegNo, 1092 uint64_t Address, 1093 const void *Decoder) { 1094 if (RegNo > 31) 1095 return MCDisassembler::Fail; 1096 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1097 Inst.addOperand(MCOperand::createReg(Reg)); 1098 return MCDisassembler::Success; 1099 } 1100 1101 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1102 unsigned RegNo, 1103 uint64_t Address, 1104 const void *Decoder) { 1105 if (RegNo > 7) 1106 return MCDisassembler::Fail; 1107 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1108 Inst.addOperand(MCOperand::createReg(Reg)); 1109 return MCDisassembler::Success; 1110 } 1111 1112 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1113 uint64_t Address, 1114 const void *Decoder) { 1115 if (RegNo > 31) 1116 return MCDisassembler::Fail; 1117 1118 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1119 Inst.addOperand(MCOperand::createReg(Reg)); 1120 return MCDisassembler::Success; 1121 } 1122 1123 static DecodeStatus DecodeMem(MCInst &Inst, 1124 unsigned Insn, 1125 uint64_t Address, 1126 const void *Decoder) { 1127 int Offset = SignExtend32<16>(Insn & 0xffff); 1128 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1129 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1130 1131 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1132 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1133 1134 if (Inst.getOpcode() == Mips::SC || 1135 Inst.getOpcode() == Mips::SCD) 1136 Inst.addOperand(MCOperand::createReg(Reg)); 1137 1138 Inst.addOperand(MCOperand::createReg(Reg)); 1139 Inst.addOperand(MCOperand::createReg(Base)); 1140 Inst.addOperand(MCOperand::createImm(Offset)); 1141 1142 return MCDisassembler::Success; 1143 } 1144 1145 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1146 unsigned Insn, 1147 uint64_t Address, 1148 const void *Decoder) { 1149 int Offset = SignExtend32<9>(Insn >> 7); 1150 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1151 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1152 1153 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1154 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1155 1156 if (Inst.getOpcode() == Mips::SCE) 1157 Inst.addOperand(MCOperand::createReg(Reg)); 1158 1159 Inst.addOperand(MCOperand::createReg(Reg)); 1160 Inst.addOperand(MCOperand::createReg(Base)); 1161 Inst.addOperand(MCOperand::createImm(Offset)); 1162 1163 return MCDisassembler::Success; 1164 } 1165 1166 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1167 unsigned Insn, 1168 uint64_t Address, 1169 const void *Decoder) { 1170 int Offset = SignExtend32<9>(Insn & 0x1ff); 1171 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1172 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1173 1174 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1175 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1176 1177 Inst.addOperand(MCOperand::createReg(Reg)); 1178 Inst.addOperand(MCOperand::createReg(Base)); 1179 Inst.addOperand(MCOperand::createImm(Offset)); 1180 1181 return MCDisassembler::Success; 1182 } 1183 1184 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1185 unsigned Insn, 1186 uint64_t Address, 1187 const void *Decoder) { 1188 int Offset = SignExtend32<16>(Insn & 0xffff); 1189 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1190 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1191 1192 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1193 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1194 1195 Inst.addOperand(MCOperand::createReg(Reg)); 1196 Inst.addOperand(MCOperand::createReg(Base)); 1197 Inst.addOperand(MCOperand::createImm(Offset)); 1198 1199 return MCDisassembler::Success; 1200 } 1201 1202 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1203 unsigned Insn, 1204 uint64_t Address, 1205 const void *Decoder) { 1206 int Offset = SignExtend32<16>(Insn & 0xffff); 1207 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1208 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1209 1210 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1211 1212 Inst.addOperand(MCOperand::createReg(Base)); 1213 Inst.addOperand(MCOperand::createImm(Offset)); 1214 Inst.addOperand(MCOperand::createImm(Hint)); 1215 1216 return MCDisassembler::Success; 1217 } 1218 1219 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1220 unsigned Insn, 1221 uint64_t Address, 1222 const void *Decoder) { 1223 int Offset = SignExtend32<12>(Insn & 0xfff); 1224 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1225 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1226 1227 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1228 1229 Inst.addOperand(MCOperand::createReg(Base)); 1230 Inst.addOperand(MCOperand::createImm(Offset)); 1231 Inst.addOperand(MCOperand::createImm(Hint)); 1232 1233 return MCDisassembler::Success; 1234 } 1235 1236 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1237 unsigned Insn, 1238 uint64_t Address, 1239 const void *Decoder) { 1240 int Offset = SignExtend32<9>(Insn & 0x1ff); 1241 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1242 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1243 1244 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1245 1246 Inst.addOperand(MCOperand::createReg(Base)); 1247 Inst.addOperand(MCOperand::createImm(Offset)); 1248 Inst.addOperand(MCOperand::createImm(Hint)); 1249 1250 return MCDisassembler::Success; 1251 } 1252 1253 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1254 unsigned Insn, 1255 uint64_t Address, 1256 const void *Decoder) { 1257 int Offset = SignExtend32<9>(Insn >> 7); 1258 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1259 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1260 1261 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1262 1263 Inst.addOperand(MCOperand::createReg(Base)); 1264 Inst.addOperand(MCOperand::createImm(Offset)); 1265 Inst.addOperand(MCOperand::createImm(Hint)); 1266 1267 return MCDisassembler::Success; 1268 } 1269 1270 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1271 unsigned Insn, 1272 uint64_t Address, 1273 const void *Decoder) { 1274 int Offset = SignExtend32<9>(Insn & 0x1ff); 1275 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1276 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1277 1278 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1279 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1280 1281 Inst.addOperand(MCOperand::createReg(Reg)); 1282 Inst.addOperand(MCOperand::createReg(Base)); 1283 Inst.addOperand(MCOperand::createImm(Offset)); 1284 1285 return MCDisassembler::Success; 1286 } 1287 1288 static DecodeStatus DecodeSyncI(MCInst &Inst, 1289 unsigned Insn, 1290 uint64_t Address, 1291 const void *Decoder) { 1292 int Offset = SignExtend32<16>(Insn & 0xffff); 1293 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1294 1295 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1296 1297 Inst.addOperand(MCOperand::createReg(Base)); 1298 Inst.addOperand(MCOperand::createImm(Offset)); 1299 1300 return MCDisassembler::Success; 1301 } 1302 1303 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1304 uint64_t Address, const void *Decoder) { 1305 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1306 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1307 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1308 1309 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1310 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1311 1312 Inst.addOperand(MCOperand::createReg(Reg)); 1313 Inst.addOperand(MCOperand::createReg(Base)); 1314 1315 // The immediate field of an LD/ST instruction is scaled which means it must 1316 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1317 // data format. 1318 // .b - 1 byte 1319 // .h - 2 bytes 1320 // .w - 4 bytes 1321 // .d - 8 bytes 1322 switch(Inst.getOpcode()) 1323 { 1324 default: 1325 assert (0 && "Unexpected instruction"); 1326 return MCDisassembler::Fail; 1327 break; 1328 case Mips::LD_B: 1329 case Mips::ST_B: 1330 Inst.addOperand(MCOperand::createImm(Offset)); 1331 break; 1332 case Mips::LD_H: 1333 case Mips::ST_H: 1334 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1335 break; 1336 case Mips::LD_W: 1337 case Mips::ST_W: 1338 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1339 break; 1340 case Mips::LD_D: 1341 case Mips::ST_D: 1342 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1343 break; 1344 } 1345 1346 return MCDisassembler::Success; 1347 } 1348 1349 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1350 unsigned Insn, 1351 uint64_t Address, 1352 const void *Decoder) { 1353 unsigned Offset = Insn & 0xf; 1354 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1355 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1356 1357 switch (Inst.getOpcode()) { 1358 case Mips::LBU16_MM: 1359 case Mips::LHU16_MM: 1360 case Mips::LW16_MM: 1361 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1362 == MCDisassembler::Fail) 1363 return MCDisassembler::Fail; 1364 break; 1365 case Mips::SB16_MM: 1366 case Mips::SH16_MM: 1367 case Mips::SW16_MM: 1368 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1369 == MCDisassembler::Fail) 1370 return MCDisassembler::Fail; 1371 break; 1372 } 1373 1374 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1375 == MCDisassembler::Fail) 1376 return MCDisassembler::Fail; 1377 1378 switch (Inst.getOpcode()) { 1379 case Mips::LBU16_MM: 1380 if (Offset == 0xf) 1381 Inst.addOperand(MCOperand::createImm(-1)); 1382 else 1383 Inst.addOperand(MCOperand::createImm(Offset)); 1384 break; 1385 case Mips::SB16_MM: 1386 Inst.addOperand(MCOperand::createImm(Offset)); 1387 break; 1388 case Mips::LHU16_MM: 1389 case Mips::SH16_MM: 1390 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1391 break; 1392 case Mips::LW16_MM: 1393 case Mips::SW16_MM: 1394 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1395 break; 1396 } 1397 1398 return MCDisassembler::Success; 1399 } 1400 1401 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1402 unsigned Insn, 1403 uint64_t Address, 1404 const void *Decoder) { 1405 unsigned Offset = Insn & 0x1F; 1406 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1407 1408 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1409 1410 Inst.addOperand(MCOperand::createReg(Reg)); 1411 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1412 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1413 1414 return MCDisassembler::Success; 1415 } 1416 1417 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1418 unsigned Insn, 1419 uint64_t Address, 1420 const void *Decoder) { 1421 unsigned Offset = Insn & 0x7F; 1422 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1423 1424 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1425 1426 Inst.addOperand(MCOperand::createReg(Reg)); 1427 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1428 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1429 1430 return MCDisassembler::Success; 1431 } 1432 1433 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1434 unsigned Insn, 1435 uint64_t Address, 1436 const void *Decoder) { 1437 int Offset = SignExtend32<4>(Insn & 0xf); 1438 1439 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1440 == MCDisassembler::Fail) 1441 return MCDisassembler::Fail; 1442 1443 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1444 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1445 1446 return MCDisassembler::Success; 1447 } 1448 1449 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1450 unsigned Insn, 1451 uint64_t Address, 1452 const void *Decoder) { 1453 int Offset = SignExtend32<9>(Insn & 0x1ff); 1454 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1455 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1456 1457 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1458 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1459 1460 if (Inst.getOpcode() == Mips::SCE_MM) 1461 Inst.addOperand(MCOperand::createReg(Reg)); 1462 1463 Inst.addOperand(MCOperand::createReg(Reg)); 1464 Inst.addOperand(MCOperand::createReg(Base)); 1465 Inst.addOperand(MCOperand::createImm(Offset)); 1466 1467 return MCDisassembler::Success; 1468 } 1469 1470 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1471 unsigned Insn, 1472 uint64_t Address, 1473 const void *Decoder) { 1474 int Offset = SignExtend32<12>(Insn & 0x0fff); 1475 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1476 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1477 1478 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1479 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1480 1481 switch (Inst.getOpcode()) { 1482 case Mips::SWM32_MM: 1483 case Mips::LWM32_MM: 1484 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1485 == MCDisassembler::Fail) 1486 return MCDisassembler::Fail; 1487 Inst.addOperand(MCOperand::createReg(Base)); 1488 Inst.addOperand(MCOperand::createImm(Offset)); 1489 break; 1490 case Mips::SC_MM: 1491 Inst.addOperand(MCOperand::createReg(Reg)); 1492 // fallthrough 1493 default: 1494 Inst.addOperand(MCOperand::createReg(Reg)); 1495 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1496 Inst.addOperand(MCOperand::createReg(Reg+1)); 1497 1498 Inst.addOperand(MCOperand::createReg(Base)); 1499 Inst.addOperand(MCOperand::createImm(Offset)); 1500 } 1501 1502 return MCDisassembler::Success; 1503 } 1504 1505 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1506 unsigned Insn, 1507 uint64_t Address, 1508 const void *Decoder) { 1509 int Offset = SignExtend32<16>(Insn & 0xffff); 1510 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1511 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1512 1513 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1514 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1515 1516 Inst.addOperand(MCOperand::createReg(Reg)); 1517 Inst.addOperand(MCOperand::createReg(Base)); 1518 Inst.addOperand(MCOperand::createImm(Offset)); 1519 1520 return MCDisassembler::Success; 1521 } 1522 1523 static DecodeStatus DecodeFMem(MCInst &Inst, 1524 unsigned Insn, 1525 uint64_t Address, 1526 const void *Decoder) { 1527 int Offset = SignExtend32<16>(Insn & 0xffff); 1528 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1529 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1530 1531 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1532 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1533 1534 Inst.addOperand(MCOperand::createReg(Reg)); 1535 Inst.addOperand(MCOperand::createReg(Base)); 1536 Inst.addOperand(MCOperand::createImm(Offset)); 1537 1538 return MCDisassembler::Success; 1539 } 1540 1541 static DecodeStatus DecodeFMem2(MCInst &Inst, 1542 unsigned Insn, 1543 uint64_t Address, 1544 const void *Decoder) { 1545 int Offset = SignExtend32<16>(Insn & 0xffff); 1546 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1547 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1548 1549 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1550 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1551 1552 Inst.addOperand(MCOperand::createReg(Reg)); 1553 Inst.addOperand(MCOperand::createReg(Base)); 1554 Inst.addOperand(MCOperand::createImm(Offset)); 1555 1556 return MCDisassembler::Success; 1557 } 1558 1559 static DecodeStatus DecodeFMem3(MCInst &Inst, 1560 unsigned Insn, 1561 uint64_t Address, 1562 const void *Decoder) { 1563 int Offset = SignExtend32<16>(Insn & 0xffff); 1564 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1565 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1566 1567 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1568 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1569 1570 Inst.addOperand(MCOperand::createReg(Reg)); 1571 Inst.addOperand(MCOperand::createReg(Base)); 1572 Inst.addOperand(MCOperand::createImm(Offset)); 1573 1574 return MCDisassembler::Success; 1575 } 1576 1577 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1578 unsigned Insn, 1579 uint64_t Address, 1580 const void *Decoder) { 1581 int Offset = SignExtend32<11>(Insn & 0x07ff); 1582 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1583 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1584 1585 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1586 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1587 1588 Inst.addOperand(MCOperand::createReg(Reg)); 1589 Inst.addOperand(MCOperand::createReg(Base)); 1590 Inst.addOperand(MCOperand::createImm(Offset)); 1591 1592 return MCDisassembler::Success; 1593 } 1594 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1595 unsigned Insn, 1596 uint64_t Address, 1597 const void *Decoder) { 1598 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1599 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1600 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1601 1602 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1603 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1604 1605 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1606 Inst.addOperand(MCOperand::createReg(Rt)); 1607 } 1608 1609 Inst.addOperand(MCOperand::createReg(Rt)); 1610 Inst.addOperand(MCOperand::createReg(Base)); 1611 Inst.addOperand(MCOperand::createImm(Offset)); 1612 1613 return MCDisassembler::Success; 1614 } 1615 1616 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1617 unsigned RegNo, 1618 uint64_t Address, 1619 const void *Decoder) { 1620 // Currently only hardware register 29 is supported. 1621 if (RegNo != 29) 1622 return MCDisassembler::Fail; 1623 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1624 return MCDisassembler::Success; 1625 } 1626 1627 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1628 unsigned RegNo, 1629 uint64_t Address, 1630 const void *Decoder) { 1631 if (RegNo > 30 || RegNo %2) 1632 return MCDisassembler::Fail; 1633 1634 ; 1635 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1636 Inst.addOperand(MCOperand::createReg(Reg)); 1637 return MCDisassembler::Success; 1638 } 1639 1640 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1641 unsigned RegNo, 1642 uint64_t Address, 1643 const void *Decoder) { 1644 if (RegNo >= 4) 1645 return MCDisassembler::Fail; 1646 1647 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1648 Inst.addOperand(MCOperand::createReg(Reg)); 1649 return MCDisassembler::Success; 1650 } 1651 1652 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1653 unsigned RegNo, 1654 uint64_t Address, 1655 const void *Decoder) { 1656 if (RegNo >= 4) 1657 return MCDisassembler::Fail; 1658 1659 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1660 Inst.addOperand(MCOperand::createReg(Reg)); 1661 return MCDisassembler::Success; 1662 } 1663 1664 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1665 unsigned RegNo, 1666 uint64_t Address, 1667 const void *Decoder) { 1668 if (RegNo >= 4) 1669 return MCDisassembler::Fail; 1670 1671 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1672 Inst.addOperand(MCOperand::createReg(Reg)); 1673 return MCDisassembler::Success; 1674 } 1675 1676 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1677 unsigned RegNo, 1678 uint64_t Address, 1679 const void *Decoder) { 1680 if (RegNo > 31) 1681 return MCDisassembler::Fail; 1682 1683 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1684 Inst.addOperand(MCOperand::createReg(Reg)); 1685 return MCDisassembler::Success; 1686 } 1687 1688 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1689 unsigned RegNo, 1690 uint64_t Address, 1691 const void *Decoder) { 1692 if (RegNo > 31) 1693 return MCDisassembler::Fail; 1694 1695 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1696 Inst.addOperand(MCOperand::createReg(Reg)); 1697 return MCDisassembler::Success; 1698 } 1699 1700 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1701 unsigned RegNo, 1702 uint64_t Address, 1703 const void *Decoder) { 1704 if (RegNo > 31) 1705 return MCDisassembler::Fail; 1706 1707 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1708 Inst.addOperand(MCOperand::createReg(Reg)); 1709 return MCDisassembler::Success; 1710 } 1711 1712 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1713 unsigned RegNo, 1714 uint64_t Address, 1715 const void *Decoder) { 1716 if (RegNo > 31) 1717 return MCDisassembler::Fail; 1718 1719 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1720 Inst.addOperand(MCOperand::createReg(Reg)); 1721 return MCDisassembler::Success; 1722 } 1723 1724 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1725 unsigned RegNo, 1726 uint64_t Address, 1727 const void *Decoder) { 1728 if (RegNo > 7) 1729 return MCDisassembler::Fail; 1730 1731 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1732 Inst.addOperand(MCOperand::createReg(Reg)); 1733 return MCDisassembler::Success; 1734 } 1735 1736 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1737 unsigned RegNo, 1738 uint64_t Address, 1739 const void *Decoder) { 1740 if (RegNo > 31) 1741 return MCDisassembler::Fail; 1742 1743 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1744 Inst.addOperand(MCOperand::createReg(Reg)); 1745 return MCDisassembler::Success; 1746 } 1747 1748 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1749 unsigned RegNo, 1750 uint64_t Address, 1751 const void *Decoder) { 1752 if (RegNo > 31) 1753 return MCDisassembler::Fail; 1754 1755 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1756 Inst.addOperand(MCOperand::createReg(Reg)); 1757 return MCDisassembler::Success; 1758 } 1759 1760 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1761 unsigned Offset, 1762 uint64_t Address, 1763 const void *Decoder) { 1764 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1765 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1766 return MCDisassembler::Success; 1767 } 1768 1769 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1770 unsigned Insn, 1771 uint64_t Address, 1772 const void *Decoder) { 1773 1774 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1775 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1776 return MCDisassembler::Success; 1777 } 1778 1779 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1780 unsigned Offset, 1781 uint64_t Address, 1782 const void *Decoder) { 1783 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1784 1785 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1786 return MCDisassembler::Success; 1787 } 1788 1789 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1790 unsigned Offset, 1791 uint64_t Address, 1792 const void *Decoder) { 1793 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1794 1795 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1796 return MCDisassembler::Success; 1797 } 1798 1799 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1800 unsigned Offset, 1801 uint64_t Address, 1802 const void *Decoder) { 1803 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1804 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1805 return MCDisassembler::Success; 1806 } 1807 1808 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1809 unsigned Offset, 1810 uint64_t Address, 1811 const void *Decoder) { 1812 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1813 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1814 return MCDisassembler::Success; 1815 } 1816 1817 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1818 unsigned Offset, 1819 uint64_t Address, 1820 const void *Decoder) { 1821 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1822 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1823 return MCDisassembler::Success; 1824 } 1825 1826 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1827 unsigned Insn, 1828 uint64_t Address, 1829 const void *Decoder) { 1830 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1831 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1832 return MCDisassembler::Success; 1833 } 1834 1835 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1836 unsigned Value, 1837 uint64_t Address, 1838 const void *Decoder) { 1839 if (Value == 0) 1840 Inst.addOperand(MCOperand::createImm(1)); 1841 else if (Value == 0x7) 1842 Inst.addOperand(MCOperand::createImm(-1)); 1843 else 1844 Inst.addOperand(MCOperand::createImm(Value << 2)); 1845 return MCDisassembler::Success; 1846 } 1847 1848 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1849 unsigned Value, 1850 uint64_t Address, 1851 const void *Decoder) { 1852 Inst.addOperand(MCOperand::createImm(Value << 2)); 1853 return MCDisassembler::Success; 1854 } 1855 1856 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1857 unsigned Value, 1858 uint64_t Address, 1859 const void *Decoder) { 1860 if (Value == 0x7F) 1861 Inst.addOperand(MCOperand::createImm(-1)); 1862 else 1863 Inst.addOperand(MCOperand::createImm(Value)); 1864 return MCDisassembler::Success; 1865 } 1866 1867 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1868 unsigned Value, 1869 uint64_t Address, 1870 const void *Decoder) { 1871 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1872 return MCDisassembler::Success; 1873 } 1874 1875 static DecodeStatus DecodeSimm4(MCInst &Inst, 1876 unsigned Value, 1877 uint64_t Address, 1878 const void *Decoder) { 1879 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); 1880 return MCDisassembler::Success; 1881 } 1882 1883 static DecodeStatus DecodeSimm16(MCInst &Inst, 1884 unsigned Insn, 1885 uint64_t Address, 1886 const void *Decoder) { 1887 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); 1888 return MCDisassembler::Success; 1889 } 1890 1891 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1892 unsigned Insn, 1893 uint64_t Address, 1894 const void *Decoder) { 1895 // We add one to the immediate field as it was encoded as 'imm - 1'. 1896 Inst.addOperand(MCOperand::createImm(Insn + 1)); 1897 return MCDisassembler::Success; 1898 } 1899 1900 static DecodeStatus DecodeInsSize(MCInst &Inst, 1901 unsigned Insn, 1902 uint64_t Address, 1903 const void *Decoder) { 1904 // First we need to grab the pos(lsb) from MCInst. 1905 int Pos = Inst.getOperand(2).getImm(); 1906 int Size = (int) Insn - Pos + 1; 1907 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1908 return MCDisassembler::Success; 1909 } 1910 1911 static DecodeStatus DecodeExtSize(MCInst &Inst, 1912 unsigned Insn, 1913 uint64_t Address, 1914 const void *Decoder) { 1915 int Size = (int) Insn + 1; 1916 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1917 return MCDisassembler::Success; 1918 } 1919 1920 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1921 uint64_t Address, const void *Decoder) { 1922 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1923 return MCDisassembler::Success; 1924 } 1925 1926 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1927 uint64_t Address, const void *Decoder) { 1928 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1929 return MCDisassembler::Success; 1930 } 1931 1932 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1933 uint64_t Address, const void *Decoder) { 1934 int32_t DecodedValue; 1935 switch (Insn) { 1936 case 0: DecodedValue = 256; break; 1937 case 1: DecodedValue = 257; break; 1938 case 510: DecodedValue = -258; break; 1939 case 511: DecodedValue = -257; break; 1940 default: DecodedValue = SignExtend32<9>(Insn); break; 1941 } 1942 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1943 return MCDisassembler::Success; 1944 } 1945 1946 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1947 uint64_t Address, const void *Decoder) { 1948 // Insn must be >= 0, since it is unsigned that condition is always true. 1949 assert(Insn < 16); 1950 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1951 255, 32768, 65535}; 1952 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 1953 return MCDisassembler::Success; 1954 } 1955 1956 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1957 uint64_t Address, const void *Decoder) { 1958 Inst.addOperand(MCOperand::createImm(Insn << 2)); 1959 return MCDisassembler::Success; 1960 } 1961 1962 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1963 unsigned Insn, 1964 uint64_t Address, 1965 const void *Decoder) { 1966 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1967 Mips::S6, Mips::S7, Mips::FP}; 1968 unsigned RegNum; 1969 1970 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1971 1972 // Empty register lists are not allowed. 1973 if (RegLst == 0) 1974 return MCDisassembler::Fail; 1975 1976 RegNum = RegLst & 0xf; 1977 1978 // RegLst values 10-15, and 26-31 are reserved. 1979 if (RegNum > 9) 1980 return MCDisassembler::Fail; 1981 1982 for (unsigned i = 0; i < RegNum; i++) 1983 Inst.addOperand(MCOperand::createReg(Regs[i])); 1984 1985 if (RegLst & 0x10) 1986 Inst.addOperand(MCOperand::createReg(Mips::RA)); 1987 1988 return MCDisassembler::Success; 1989 } 1990 1991 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 1992 uint64_t Address, 1993 const void *Decoder) { 1994 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 1995 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 1996 unsigned RegNum = RegLst & 0x3; 1997 1998 for (unsigned i = 0; i <= RegNum; i++) 1999 Inst.addOperand(MCOperand::createReg(Regs[i])); 2000 2001 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2002 2003 return MCDisassembler::Success; 2004 } 2005 2006 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2007 uint64_t Address, const void *Decoder) { 2008 2009 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2010 2011 switch (RegPair) { 2012 default: 2013 return MCDisassembler::Fail; 2014 case 0: 2015 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2016 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2017 break; 2018 case 1: 2019 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2020 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2021 break; 2022 case 2: 2023 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2024 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2025 break; 2026 case 3: 2027 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2028 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2029 break; 2030 case 4: 2031 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2032 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2033 break; 2034 case 5: 2035 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2036 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2037 break; 2038 case 6: 2039 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2040 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2041 break; 2042 case 7: 2043 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2044 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2045 break; 2046 } 2047 2048 return MCDisassembler::Success; 2049 } 2050 2051 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2052 uint64_t Address, const void *Decoder) { 2053 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2054 return MCDisassembler::Success; 2055 } 2056