1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 49 50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 51 52 bool hasCOP3() const { 53 // Only present in MIPS-I and MIPS-II 54 return !hasMips32() && !hasMips3(); 55 } 56 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 }; 62 63 } // end anonymous namespace 64 65 // Forward declare these because the autogenerated code will reference them. 66 // Definitions are further down. 67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 68 unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 78 unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 132 unsigned Insn, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 142 unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 147 unsigned RegNo, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 192 unsigned Offset, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 202 unsigned Offset, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 212 // shifted left by 1 bit. 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 235 unsigned Insn, 236 uint64_t Address, 237 const void *Decoder); 238 239 static DecodeStatus DecodeMem(MCInst &Inst, 240 unsigned Insn, 241 uint64_t Address, 242 const void *Decoder); 243 244 static DecodeStatus DecodeCacheOp(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 249 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 250 unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 254 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 255 unsigned Insn, 256 uint64_t Address, 257 const void *Decoder); 258 259 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 260 unsigned Insn, 261 uint64_t Address, 262 const void *Decoder); 263 264 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 265 unsigned Insn, 266 uint64_t Address, 267 const void *Decoder); 268 269 static DecodeStatus DecodeSyncI(MCInst &Inst, 270 unsigned Insn, 271 uint64_t Address, 272 const void *Decoder); 273 274 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 277 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 313 uint64_t Address, 314 const void *Decoder); 315 316 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 321 uint64_t Address, 322 const void *Decoder); 323 324 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 334 unsigned Value, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 339 unsigned Value, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 344 unsigned Value, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 349 unsigned Value, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeSimm4(MCInst &Inst, 354 unsigned Value, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeSimm16(MCInst &Inst, 359 unsigned Insn, 360 uint64_t Address, 361 const void *Decoder); 362 363 // Decode the immediate field of an LSA instruction which 364 // is off by one. 365 static DecodeStatus DecodeLSAImm(MCInst &Inst, 366 unsigned Insn, 367 uint64_t Address, 368 const void *Decoder); 369 370 static DecodeStatus DecodeInsSize(MCInst &Inst, 371 unsigned Insn, 372 uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeExtSize(MCInst &Inst, 376 unsigned Insn, 377 uint64_t Address, 378 const void *Decoder); 379 380 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 381 uint64_t Address, const void *Decoder); 382 383 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 386 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 389 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 392 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 393 uint64_t Address, const void *Decoder); 394 395 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 398 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 399 /// handle. 400 template <typename InsnType> 401 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 402 const void *Decoder); 403 404 template <typename InsnType> 405 static DecodeStatus 406 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 407 const void *Decoder); 408 409 template <typename InsnType> 410 static DecodeStatus 411 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 412 const void *Decoder); 413 414 template <typename InsnType> 415 static DecodeStatus 416 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 417 const void *Decoder); 418 419 template <typename InsnType> 420 static DecodeStatus 421 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 422 const void *Decoder); 423 424 template <typename InsnType> 425 static DecodeStatus 426 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 427 const void *Decoder); 428 429 template <typename InsnType> 430 static DecodeStatus 431 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 432 const void *Decoder); 433 434 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 435 uint64_t Address, 436 const void *Decoder); 437 438 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 439 uint64_t Address, 440 const void *Decoder); 441 442 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 443 uint64_t Address, 444 const void *Decoder); 445 446 namespace llvm { 447 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 448 TheMips64elTarget; 449 } 450 451 static MCDisassembler *createMipsDisassembler( 452 const Target &T, 453 const MCSubtargetInfo &STI, 454 MCContext &Ctx) { 455 return new MipsDisassembler(STI, Ctx, true); 456 } 457 458 static MCDisassembler *createMipselDisassembler( 459 const Target &T, 460 const MCSubtargetInfo &STI, 461 MCContext &Ctx) { 462 return new MipsDisassembler(STI, Ctx, false); 463 } 464 465 extern "C" void LLVMInitializeMipsDisassembler() { 466 // Register the disassembler. 467 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 468 createMipsDisassembler); 469 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 470 createMipselDisassembler); 471 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 472 createMipsDisassembler); 473 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 474 createMipselDisassembler); 475 } 476 477 #include "MipsGenDisassemblerTables.inc" 478 479 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 480 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 481 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 482 return *(RegInfo->getRegClass(RC).begin() + RegNo); 483 } 484 485 template <typename InsnType> 486 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 487 const void *Decoder) { 488 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 489 // The size of the n field depends on the element size 490 // The register class also depends on this. 491 InsnType tmp = fieldFromInstruction(insn, 17, 5); 492 unsigned NSize = 0; 493 DecodeFN RegDecoder = nullptr; 494 if ((tmp & 0x18) == 0x00) { // INSVE_B 495 NSize = 4; 496 RegDecoder = DecodeMSA128BRegisterClass; 497 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 498 NSize = 3; 499 RegDecoder = DecodeMSA128HRegisterClass; 500 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 501 NSize = 2; 502 RegDecoder = DecodeMSA128WRegisterClass; 503 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 504 NSize = 1; 505 RegDecoder = DecodeMSA128DRegisterClass; 506 } else 507 llvm_unreachable("Invalid encoding"); 508 509 assert(NSize != 0 && RegDecoder != nullptr); 510 511 // $wd 512 tmp = fieldFromInstruction(insn, 6, 5); 513 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 514 return MCDisassembler::Fail; 515 // $wd_in 516 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 517 return MCDisassembler::Fail; 518 // $n 519 tmp = fieldFromInstruction(insn, 16, NSize); 520 MI.addOperand(MCOperand::createImm(tmp)); 521 // $ws 522 tmp = fieldFromInstruction(insn, 11, 5); 523 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 524 return MCDisassembler::Fail; 525 // $n2 526 MI.addOperand(MCOperand::createImm(0)); 527 528 return MCDisassembler::Success; 529 } 530 531 template <typename InsnType> 532 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 533 uint64_t Address, 534 const void *Decoder) { 535 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 536 // (otherwise we would have matched the ADDI instruction from the earlier 537 // ISA's instead). 538 // 539 // We have: 540 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 541 // BOVC if rs >= rt 542 // BEQZALC if rs == 0 && rt != 0 543 // BEQC if rs < rt && rs != 0 544 545 InsnType Rs = fieldFromInstruction(insn, 21, 5); 546 InsnType Rt = fieldFromInstruction(insn, 16, 5); 547 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 548 bool HasRs = false; 549 550 if (Rs >= Rt) { 551 MI.setOpcode(Mips::BOVC); 552 HasRs = true; 553 } else if (Rs != 0 && Rs < Rt) { 554 MI.setOpcode(Mips::BEQC); 555 HasRs = true; 556 } else 557 MI.setOpcode(Mips::BEQZALC); 558 559 if (HasRs) 560 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 561 Rs))); 562 563 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 564 Rt))); 565 MI.addOperand(MCOperand::createImm(Imm)); 566 567 return MCDisassembler::Success; 568 } 569 570 template <typename InsnType> 571 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 572 uint64_t Address, 573 const void *Decoder) { 574 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 575 // (otherwise we would have matched the ADDI instruction from the earlier 576 // ISA's instead). 577 // 578 // We have: 579 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 580 // BNVC if rs >= rt 581 // BNEZALC if rs == 0 && rt != 0 582 // BNEC if rs < rt && rs != 0 583 584 InsnType Rs = fieldFromInstruction(insn, 21, 5); 585 InsnType Rt = fieldFromInstruction(insn, 16, 5); 586 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 587 bool HasRs = false; 588 589 if (Rs >= Rt) { 590 MI.setOpcode(Mips::BNVC); 591 HasRs = true; 592 } else if (Rs != 0 && Rs < Rt) { 593 MI.setOpcode(Mips::BNEC); 594 HasRs = true; 595 } else 596 MI.setOpcode(Mips::BNEZALC); 597 598 if (HasRs) 599 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 600 Rs))); 601 602 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 603 Rt))); 604 MI.addOperand(MCOperand::createImm(Imm)); 605 606 return MCDisassembler::Success; 607 } 608 609 template <typename InsnType> 610 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 611 uint64_t Address, 612 const void *Decoder) { 613 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 614 // (otherwise we would have matched the BLEZL instruction from the earlier 615 // ISA's instead). 616 // 617 // We have: 618 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 619 // Invalid if rs == 0 620 // BLEZC if rs == 0 && rt != 0 621 // BGEZC if rs == rt && rt != 0 622 // BGEC if rs != rt && rs != 0 && rt != 0 623 624 InsnType Rs = fieldFromInstruction(insn, 21, 5); 625 InsnType Rt = fieldFromInstruction(insn, 16, 5); 626 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 627 bool HasRs = false; 628 629 if (Rt == 0) 630 return MCDisassembler::Fail; 631 else if (Rs == 0) 632 MI.setOpcode(Mips::BLEZC); 633 else if (Rs == Rt) 634 MI.setOpcode(Mips::BGEZC); 635 else { 636 HasRs = true; 637 MI.setOpcode(Mips::BGEC); 638 } 639 640 if (HasRs) 641 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 642 Rs))); 643 644 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 645 Rt))); 646 647 MI.addOperand(MCOperand::createImm(Imm)); 648 649 return MCDisassembler::Success; 650 } 651 652 template <typename InsnType> 653 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 654 uint64_t Address, 655 const void *Decoder) { 656 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 657 // (otherwise we would have matched the BGTZL instruction from the earlier 658 // ISA's instead). 659 // 660 // We have: 661 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 662 // Invalid if rs == 0 663 // BGTZC if rs == 0 && rt != 0 664 // BLTZC if rs == rt && rt != 0 665 // BLTC if rs != rt && rs != 0 && rt != 0 666 667 bool HasRs = false; 668 669 InsnType Rs = fieldFromInstruction(insn, 21, 5); 670 InsnType Rt = fieldFromInstruction(insn, 16, 5); 671 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 672 673 if (Rt == 0) 674 return MCDisassembler::Fail; 675 else if (Rs == 0) 676 MI.setOpcode(Mips::BGTZC); 677 else if (Rs == Rt) 678 MI.setOpcode(Mips::BLTZC); 679 else { 680 MI.setOpcode(Mips::BLTC); 681 HasRs = true; 682 } 683 684 if (HasRs) 685 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 686 Rs))); 687 688 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 689 Rt))); 690 691 MI.addOperand(MCOperand::createImm(Imm)); 692 693 return MCDisassembler::Success; 694 } 695 696 template <typename InsnType> 697 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 698 uint64_t Address, 699 const void *Decoder) { 700 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 701 // (otherwise we would have matched the BGTZ instruction from the earlier 702 // ISA's instead). 703 // 704 // We have: 705 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 706 // BGTZ if rt == 0 707 // BGTZALC if rs == 0 && rt != 0 708 // BLTZALC if rs != 0 && rs == rt 709 // BLTUC if rs != 0 && rs != rt 710 711 InsnType Rs = fieldFromInstruction(insn, 21, 5); 712 InsnType Rt = fieldFromInstruction(insn, 16, 5); 713 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 714 bool HasRs = false; 715 bool HasRt = false; 716 717 if (Rt == 0) { 718 MI.setOpcode(Mips::BGTZ); 719 HasRs = true; 720 } else if (Rs == 0) { 721 MI.setOpcode(Mips::BGTZALC); 722 HasRt = true; 723 } else if (Rs == Rt) { 724 MI.setOpcode(Mips::BLTZALC); 725 HasRs = true; 726 } else { 727 MI.setOpcode(Mips::BLTUC); 728 HasRs = true; 729 HasRt = true; 730 } 731 732 if (HasRs) 733 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 734 Rs))); 735 736 if (HasRt) 737 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 738 Rt))); 739 740 MI.addOperand(MCOperand::createImm(Imm)); 741 742 return MCDisassembler::Success; 743 } 744 745 template <typename InsnType> 746 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 747 uint64_t Address, 748 const void *Decoder) { 749 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 750 // (otherwise we would have matched the BLEZL instruction from the earlier 751 // ISA's instead). 752 // 753 // We have: 754 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 755 // Invalid if rs == 0 756 // BLEZALC if rs == 0 && rt != 0 757 // BGEZALC if rs == rt && rt != 0 758 // BGEUC if rs != rt && rs != 0 && rt != 0 759 760 InsnType Rs = fieldFromInstruction(insn, 21, 5); 761 InsnType Rt = fieldFromInstruction(insn, 16, 5); 762 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 763 bool HasRs = false; 764 765 if (Rt == 0) 766 return MCDisassembler::Fail; 767 else if (Rs == 0) 768 MI.setOpcode(Mips::BLEZALC); 769 else if (Rs == Rt) 770 MI.setOpcode(Mips::BGEZALC); 771 else { 772 HasRs = true; 773 MI.setOpcode(Mips::BGEUC); 774 } 775 776 if (HasRs) 777 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 778 Rs))); 779 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 780 Rt))); 781 782 MI.addOperand(MCOperand::createImm(Imm)); 783 784 return MCDisassembler::Success; 785 } 786 787 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 788 /// according to the given endianess. 789 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 790 uint64_t &Size, uint32_t &Insn, 791 bool IsBigEndian) { 792 // We want to read exactly 2 Bytes of data. 793 if (Bytes.size() < 2) { 794 Size = 0; 795 return MCDisassembler::Fail; 796 } 797 798 if (IsBigEndian) { 799 Insn = (Bytes[0] << 8) | Bytes[1]; 800 } else { 801 Insn = (Bytes[1] << 8) | Bytes[0]; 802 } 803 804 return MCDisassembler::Success; 805 } 806 807 /// Read four bytes from the ArrayRef and return 32 bit word sorted 808 /// according to the given endianess 809 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 810 uint64_t &Size, uint32_t &Insn, 811 bool IsBigEndian, bool IsMicroMips) { 812 // We want to read exactly 4 Bytes of data. 813 if (Bytes.size() < 4) { 814 Size = 0; 815 return MCDisassembler::Fail; 816 } 817 818 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 819 // always precede the low 16 bits in the instruction stream (that is, they 820 // are placed at lower addresses in the instruction stream). 821 // 822 // microMIPS byte ordering: 823 // Big-endian: 0 | 1 | 2 | 3 824 // Little-endian: 1 | 0 | 3 | 2 825 826 if (IsBigEndian) { 827 // Encoded as a big-endian 32-bit word in the stream. 828 Insn = 829 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 830 } else { 831 if (IsMicroMips) { 832 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 833 (Bytes[1] << 24); 834 } else { 835 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 836 (Bytes[3] << 24); 837 } 838 } 839 840 return MCDisassembler::Success; 841 } 842 843 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 844 ArrayRef<uint8_t> Bytes, 845 uint64_t Address, 846 raw_ostream &VStream, 847 raw_ostream &CStream) const { 848 uint32_t Insn; 849 DecodeStatus Result; 850 851 if (IsMicroMips) { 852 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 853 854 if (hasMips32r6()) { 855 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 856 // Calling the auto-generated decoder function for microMIPS32R6 857 // (and microMIPS64R6) 16-bit instructions. 858 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 859 Address, this, STI); 860 if (Result != MCDisassembler::Fail) { 861 Size = 2; 862 return Result; 863 } 864 } 865 866 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 867 // Calling the auto-generated decoder function for microMIPS 16-bit 868 // instructions. 869 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 870 this, STI); 871 if (Result != MCDisassembler::Fail) { 872 Size = 2; 873 return Result; 874 } 875 876 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 877 if (Result == MCDisassembler::Fail) 878 return MCDisassembler::Fail; 879 880 if (hasMips32r6()) { 881 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 882 // Calling the auto-generated decoder function. 883 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 884 this, STI); 885 if (Result != MCDisassembler::Fail) { 886 Size = 4; 887 return Result; 888 } 889 } 890 891 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 892 // Calling the auto-generated decoder function. 893 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 894 this, STI); 895 if (Result != MCDisassembler::Fail) { 896 Size = 4; 897 return Result; 898 } 899 return MCDisassembler::Fail; 900 } 901 902 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 903 if (Result == MCDisassembler::Fail) 904 return MCDisassembler::Fail; 905 906 if (hasCOP3()) { 907 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 908 Result = 909 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 910 if (Result != MCDisassembler::Fail) { 911 Size = 4; 912 return Result; 913 } 914 } 915 916 if (hasMips32r6() && isGP64()) { 917 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 918 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 919 Address, this, STI); 920 if (Result != MCDisassembler::Fail) { 921 Size = 4; 922 return Result; 923 } 924 } 925 926 if (hasMips32r6()) { 927 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 928 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 929 Address, this, STI); 930 if (Result != MCDisassembler::Fail) { 931 Size = 4; 932 return Result; 933 } 934 } 935 936 if (hasCnMips()) { 937 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 938 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 939 Address, this, STI); 940 if (Result != MCDisassembler::Fail) { 941 Size = 4; 942 return Result; 943 } 944 } 945 946 if (isGP64()) { 947 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 948 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 949 Address, this, STI); 950 if (Result != MCDisassembler::Fail) { 951 Size = 4; 952 return Result; 953 } 954 } 955 956 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 957 // Calling the auto-generated decoder function. 958 Result = 959 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 960 if (Result != MCDisassembler::Fail) { 961 Size = 4; 962 return Result; 963 } 964 965 return MCDisassembler::Fail; 966 } 967 968 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 969 unsigned RegNo, 970 uint64_t Address, 971 const void *Decoder) { 972 973 return MCDisassembler::Fail; 974 975 } 976 977 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 978 unsigned RegNo, 979 uint64_t Address, 980 const void *Decoder) { 981 982 if (RegNo > 31) 983 return MCDisassembler::Fail; 984 985 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 986 Inst.addOperand(MCOperand::createReg(Reg)); 987 return MCDisassembler::Success; 988 } 989 990 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 991 unsigned RegNo, 992 uint64_t Address, 993 const void *Decoder) { 994 if (RegNo > 7) 995 return MCDisassembler::Fail; 996 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 997 Inst.addOperand(MCOperand::createReg(Reg)); 998 return MCDisassembler::Success; 999 } 1000 1001 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1002 unsigned RegNo, 1003 uint64_t Address, 1004 const void *Decoder) { 1005 if (RegNo > 7) 1006 return MCDisassembler::Fail; 1007 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1008 Inst.addOperand(MCOperand::createReg(Reg)); 1009 return MCDisassembler::Success; 1010 } 1011 1012 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1013 unsigned RegNo, 1014 uint64_t Address, 1015 const void *Decoder) { 1016 if (RegNo > 7) 1017 return MCDisassembler::Fail; 1018 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1019 Inst.addOperand(MCOperand::createReg(Reg)); 1020 return MCDisassembler::Success; 1021 } 1022 1023 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1024 unsigned RegNo, 1025 uint64_t Address, 1026 const void *Decoder) { 1027 if (RegNo > 31) 1028 return MCDisassembler::Fail; 1029 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1030 Inst.addOperand(MCOperand::createReg(Reg)); 1031 return MCDisassembler::Success; 1032 } 1033 1034 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1035 unsigned RegNo, 1036 uint64_t Address, 1037 const void *Decoder) { 1038 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1039 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1040 1041 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1042 } 1043 1044 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1045 unsigned RegNo, 1046 uint64_t Address, 1047 const void *Decoder) { 1048 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1049 } 1050 1051 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1052 unsigned RegNo, 1053 uint64_t Address, 1054 const void *Decoder) { 1055 if (RegNo > 31) 1056 return MCDisassembler::Fail; 1057 1058 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1059 Inst.addOperand(MCOperand::createReg(Reg)); 1060 return MCDisassembler::Success; 1061 } 1062 1063 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1064 unsigned RegNo, 1065 uint64_t Address, 1066 const void *Decoder) { 1067 if (RegNo > 31) 1068 return MCDisassembler::Fail; 1069 1070 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1071 Inst.addOperand(MCOperand::createReg(Reg)); 1072 return MCDisassembler::Success; 1073 } 1074 1075 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1076 unsigned RegNo, 1077 uint64_t Address, 1078 const void *Decoder) { 1079 if (RegNo > 31) 1080 return MCDisassembler::Fail; 1081 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1082 Inst.addOperand(MCOperand::createReg(Reg)); 1083 return MCDisassembler::Success; 1084 } 1085 1086 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1087 unsigned RegNo, 1088 uint64_t Address, 1089 const void *Decoder) { 1090 if (RegNo > 7) 1091 return MCDisassembler::Fail; 1092 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1093 Inst.addOperand(MCOperand::createReg(Reg)); 1094 return MCDisassembler::Success; 1095 } 1096 1097 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1098 uint64_t Address, 1099 const void *Decoder) { 1100 if (RegNo > 31) 1101 return MCDisassembler::Fail; 1102 1103 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1104 Inst.addOperand(MCOperand::createReg(Reg)); 1105 return MCDisassembler::Success; 1106 } 1107 1108 static DecodeStatus DecodeMem(MCInst &Inst, 1109 unsigned Insn, 1110 uint64_t Address, 1111 const void *Decoder) { 1112 int Offset = SignExtend32<16>(Insn & 0xffff); 1113 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1114 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1115 1116 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1117 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1118 1119 if(Inst.getOpcode() == Mips::SC || 1120 Inst.getOpcode() == Mips::SCD){ 1121 Inst.addOperand(MCOperand::createReg(Reg)); 1122 } 1123 1124 Inst.addOperand(MCOperand::createReg(Reg)); 1125 Inst.addOperand(MCOperand::createReg(Base)); 1126 Inst.addOperand(MCOperand::createImm(Offset)); 1127 1128 return MCDisassembler::Success; 1129 } 1130 1131 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1132 unsigned Insn, 1133 uint64_t Address, 1134 const void *Decoder) { 1135 int Offset = SignExtend32<16>(Insn & 0xffff); 1136 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1137 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1138 1139 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1140 1141 Inst.addOperand(MCOperand::createReg(Base)); 1142 Inst.addOperand(MCOperand::createImm(Offset)); 1143 Inst.addOperand(MCOperand::createImm(Hint)); 1144 1145 return MCDisassembler::Success; 1146 } 1147 1148 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1149 unsigned Insn, 1150 uint64_t Address, 1151 const void *Decoder) { 1152 int Offset = SignExtend32<12>(Insn & 0xfff); 1153 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1154 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1155 1156 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1157 1158 Inst.addOperand(MCOperand::createReg(Base)); 1159 Inst.addOperand(MCOperand::createImm(Offset)); 1160 Inst.addOperand(MCOperand::createImm(Hint)); 1161 1162 return MCDisassembler::Success; 1163 } 1164 1165 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1166 unsigned Insn, 1167 uint64_t Address, 1168 const void *Decoder) { 1169 int Offset = SignExtend32<9>(Insn & 0x1ff); 1170 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1171 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1172 1173 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1174 1175 Inst.addOperand(MCOperand::createReg(Base)); 1176 Inst.addOperand(MCOperand::createImm(Offset)); 1177 Inst.addOperand(MCOperand::createImm(Hint)); 1178 1179 return MCDisassembler::Success; 1180 } 1181 1182 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 1183 unsigned Insn, 1184 uint64_t Address, 1185 const void *Decoder) { 1186 int Offset = fieldFromInstruction(Insn, 7, 9); 1187 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1188 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1189 1190 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1191 1192 Inst.addOperand(MCOperand::createReg(Base)); 1193 Inst.addOperand(MCOperand::createImm(Offset)); 1194 Inst.addOperand(MCOperand::createImm(Hint)); 1195 1196 return MCDisassembler::Success; 1197 } 1198 1199 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1200 unsigned Insn, 1201 uint64_t Address, 1202 const void *Decoder) { 1203 int Offset = SignExtend32<9>(Insn & 0x1ff); 1204 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1205 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1206 1207 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1208 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1209 1210 Inst.addOperand(MCOperand::createReg(Reg)); 1211 Inst.addOperand(MCOperand::createReg(Base)); 1212 Inst.addOperand(MCOperand::createImm(Offset)); 1213 1214 return MCDisassembler::Success; 1215 } 1216 1217 static DecodeStatus DecodeSyncI(MCInst &Inst, 1218 unsigned Insn, 1219 uint64_t Address, 1220 const void *Decoder) { 1221 int Offset = SignExtend32<16>(Insn & 0xffff); 1222 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1223 1224 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1225 1226 Inst.addOperand(MCOperand::createReg(Base)); 1227 Inst.addOperand(MCOperand::createImm(Offset)); 1228 1229 return MCDisassembler::Success; 1230 } 1231 1232 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1233 uint64_t Address, const void *Decoder) { 1234 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1235 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1236 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1237 1238 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1239 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1240 1241 Inst.addOperand(MCOperand::createReg(Reg)); 1242 Inst.addOperand(MCOperand::createReg(Base)); 1243 1244 // The immediate field of an LD/ST instruction is scaled which means it must 1245 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1246 // data format. 1247 // .b - 1 byte 1248 // .h - 2 bytes 1249 // .w - 4 bytes 1250 // .d - 8 bytes 1251 switch(Inst.getOpcode()) 1252 { 1253 default: 1254 assert (0 && "Unexpected instruction"); 1255 return MCDisassembler::Fail; 1256 break; 1257 case Mips::LD_B: 1258 case Mips::ST_B: 1259 Inst.addOperand(MCOperand::createImm(Offset)); 1260 break; 1261 case Mips::LD_H: 1262 case Mips::ST_H: 1263 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1264 break; 1265 case Mips::LD_W: 1266 case Mips::ST_W: 1267 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1268 break; 1269 case Mips::LD_D: 1270 case Mips::ST_D: 1271 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1272 break; 1273 } 1274 1275 return MCDisassembler::Success; 1276 } 1277 1278 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1279 unsigned Insn, 1280 uint64_t Address, 1281 const void *Decoder) { 1282 unsigned Offset = Insn & 0xf; 1283 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1284 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1285 1286 switch (Inst.getOpcode()) { 1287 case Mips::LBU16_MM: 1288 case Mips::LHU16_MM: 1289 case Mips::LW16_MM: 1290 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1291 == MCDisassembler::Fail) 1292 return MCDisassembler::Fail; 1293 break; 1294 case Mips::SB16_MM: 1295 case Mips::SH16_MM: 1296 case Mips::SW16_MM: 1297 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1298 == MCDisassembler::Fail) 1299 return MCDisassembler::Fail; 1300 break; 1301 } 1302 1303 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1304 == MCDisassembler::Fail) 1305 return MCDisassembler::Fail; 1306 1307 switch (Inst.getOpcode()) { 1308 case Mips::LBU16_MM: 1309 if (Offset == 0xf) 1310 Inst.addOperand(MCOperand::createImm(-1)); 1311 else 1312 Inst.addOperand(MCOperand::createImm(Offset)); 1313 break; 1314 case Mips::SB16_MM: 1315 Inst.addOperand(MCOperand::createImm(Offset)); 1316 break; 1317 case Mips::LHU16_MM: 1318 case Mips::SH16_MM: 1319 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1320 break; 1321 case Mips::LW16_MM: 1322 case Mips::SW16_MM: 1323 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1324 break; 1325 } 1326 1327 return MCDisassembler::Success; 1328 } 1329 1330 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1331 unsigned Insn, 1332 uint64_t Address, 1333 const void *Decoder) { 1334 unsigned Offset = Insn & 0x1F; 1335 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1336 1337 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1338 1339 Inst.addOperand(MCOperand::createReg(Reg)); 1340 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1341 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1342 1343 return MCDisassembler::Success; 1344 } 1345 1346 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1347 unsigned Insn, 1348 uint64_t Address, 1349 const void *Decoder) { 1350 unsigned Offset = Insn & 0x7F; 1351 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1352 1353 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1354 1355 Inst.addOperand(MCOperand::createReg(Reg)); 1356 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1357 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1358 1359 return MCDisassembler::Success; 1360 } 1361 1362 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1363 unsigned Insn, 1364 uint64_t Address, 1365 const void *Decoder) { 1366 int Offset = SignExtend32<4>(Insn & 0xf); 1367 1368 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1369 == MCDisassembler::Fail) 1370 return MCDisassembler::Fail; 1371 1372 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1373 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1374 1375 return MCDisassembler::Success; 1376 } 1377 1378 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1379 unsigned Insn, 1380 uint64_t Address, 1381 const void *Decoder) { 1382 int Offset = SignExtend32<9>(Insn & 0x1ff); 1383 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1384 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1385 1386 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1387 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1388 1389 Inst.addOperand(MCOperand::createReg(Reg)); 1390 Inst.addOperand(MCOperand::createReg(Base)); 1391 Inst.addOperand(MCOperand::createImm(Offset)); 1392 1393 return MCDisassembler::Success; 1394 } 1395 1396 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1397 unsigned Insn, 1398 uint64_t Address, 1399 const void *Decoder) { 1400 int Offset = SignExtend32<12>(Insn & 0x0fff); 1401 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1402 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1403 1404 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1405 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1406 1407 switch (Inst.getOpcode()) { 1408 case Mips::SWM32_MM: 1409 case Mips::LWM32_MM: 1410 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1411 == MCDisassembler::Fail) 1412 return MCDisassembler::Fail; 1413 Inst.addOperand(MCOperand::createReg(Base)); 1414 Inst.addOperand(MCOperand::createImm(Offset)); 1415 break; 1416 case Mips::SC_MM: 1417 Inst.addOperand(MCOperand::createReg(Reg)); 1418 // fallthrough 1419 default: 1420 Inst.addOperand(MCOperand::createReg(Reg)); 1421 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1422 Inst.addOperand(MCOperand::createReg(Reg+1)); 1423 1424 Inst.addOperand(MCOperand::createReg(Base)); 1425 Inst.addOperand(MCOperand::createImm(Offset)); 1426 } 1427 1428 return MCDisassembler::Success; 1429 } 1430 1431 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1432 unsigned Insn, 1433 uint64_t Address, 1434 const void *Decoder) { 1435 int Offset = SignExtend32<16>(Insn & 0xffff); 1436 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1437 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1438 1439 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1440 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1441 1442 Inst.addOperand(MCOperand::createReg(Reg)); 1443 Inst.addOperand(MCOperand::createReg(Base)); 1444 Inst.addOperand(MCOperand::createImm(Offset)); 1445 1446 return MCDisassembler::Success; 1447 } 1448 1449 static DecodeStatus DecodeFMem(MCInst &Inst, 1450 unsigned Insn, 1451 uint64_t Address, 1452 const void *Decoder) { 1453 int Offset = SignExtend32<16>(Insn & 0xffff); 1454 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1455 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1456 1457 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1458 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1459 1460 Inst.addOperand(MCOperand::createReg(Reg)); 1461 Inst.addOperand(MCOperand::createReg(Base)); 1462 Inst.addOperand(MCOperand::createImm(Offset)); 1463 1464 return MCDisassembler::Success; 1465 } 1466 1467 static DecodeStatus DecodeFMem2(MCInst &Inst, 1468 unsigned Insn, 1469 uint64_t Address, 1470 const void *Decoder) { 1471 int Offset = SignExtend32<16>(Insn & 0xffff); 1472 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1473 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1474 1475 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1476 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1477 1478 Inst.addOperand(MCOperand::createReg(Reg)); 1479 Inst.addOperand(MCOperand::createReg(Base)); 1480 Inst.addOperand(MCOperand::createImm(Offset)); 1481 1482 return MCDisassembler::Success; 1483 } 1484 1485 static DecodeStatus DecodeFMem3(MCInst &Inst, 1486 unsigned Insn, 1487 uint64_t Address, 1488 const void *Decoder) { 1489 int Offset = SignExtend32<16>(Insn & 0xffff); 1490 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1491 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1492 1493 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1494 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1495 1496 Inst.addOperand(MCOperand::createReg(Reg)); 1497 Inst.addOperand(MCOperand::createReg(Base)); 1498 Inst.addOperand(MCOperand::createImm(Offset)); 1499 1500 return MCDisassembler::Success; 1501 } 1502 1503 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1504 unsigned Insn, 1505 uint64_t Address, 1506 const void *Decoder) { 1507 int Offset = SignExtend32<11>(Insn & 0x07ff); 1508 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1509 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1510 1511 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1512 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1513 1514 Inst.addOperand(MCOperand::createReg(Reg)); 1515 Inst.addOperand(MCOperand::createReg(Base)); 1516 Inst.addOperand(MCOperand::createImm(Offset)); 1517 1518 return MCDisassembler::Success; 1519 } 1520 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1521 unsigned Insn, 1522 uint64_t Address, 1523 const void *Decoder) { 1524 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1525 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1526 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1527 1528 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1529 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1530 1531 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1532 Inst.addOperand(MCOperand::createReg(Rt)); 1533 } 1534 1535 Inst.addOperand(MCOperand::createReg(Rt)); 1536 Inst.addOperand(MCOperand::createReg(Base)); 1537 Inst.addOperand(MCOperand::createImm(Offset)); 1538 1539 return MCDisassembler::Success; 1540 } 1541 1542 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1543 unsigned RegNo, 1544 uint64_t Address, 1545 const void *Decoder) { 1546 // Currently only hardware register 29 is supported. 1547 if (RegNo != 29) 1548 return MCDisassembler::Fail; 1549 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1550 return MCDisassembler::Success; 1551 } 1552 1553 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1554 unsigned RegNo, 1555 uint64_t Address, 1556 const void *Decoder) { 1557 if (RegNo > 30 || RegNo %2) 1558 return MCDisassembler::Fail; 1559 1560 ; 1561 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1562 Inst.addOperand(MCOperand::createReg(Reg)); 1563 return MCDisassembler::Success; 1564 } 1565 1566 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1567 unsigned RegNo, 1568 uint64_t Address, 1569 const void *Decoder) { 1570 if (RegNo >= 4) 1571 return MCDisassembler::Fail; 1572 1573 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1574 Inst.addOperand(MCOperand::createReg(Reg)); 1575 return MCDisassembler::Success; 1576 } 1577 1578 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1579 unsigned RegNo, 1580 uint64_t Address, 1581 const void *Decoder) { 1582 if (RegNo >= 4) 1583 return MCDisassembler::Fail; 1584 1585 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1586 Inst.addOperand(MCOperand::createReg(Reg)); 1587 return MCDisassembler::Success; 1588 } 1589 1590 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1591 unsigned RegNo, 1592 uint64_t Address, 1593 const void *Decoder) { 1594 if (RegNo >= 4) 1595 return MCDisassembler::Fail; 1596 1597 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1598 Inst.addOperand(MCOperand::createReg(Reg)); 1599 return MCDisassembler::Success; 1600 } 1601 1602 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1603 unsigned RegNo, 1604 uint64_t Address, 1605 const void *Decoder) { 1606 if (RegNo > 31) 1607 return MCDisassembler::Fail; 1608 1609 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1610 Inst.addOperand(MCOperand::createReg(Reg)); 1611 return MCDisassembler::Success; 1612 } 1613 1614 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1615 unsigned RegNo, 1616 uint64_t Address, 1617 const void *Decoder) { 1618 if (RegNo > 31) 1619 return MCDisassembler::Fail; 1620 1621 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1622 Inst.addOperand(MCOperand::createReg(Reg)); 1623 return MCDisassembler::Success; 1624 } 1625 1626 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1627 unsigned RegNo, 1628 uint64_t Address, 1629 const void *Decoder) { 1630 if (RegNo > 31) 1631 return MCDisassembler::Fail; 1632 1633 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1634 Inst.addOperand(MCOperand::createReg(Reg)); 1635 return MCDisassembler::Success; 1636 } 1637 1638 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1639 unsigned RegNo, 1640 uint64_t Address, 1641 const void *Decoder) { 1642 if (RegNo > 31) 1643 return MCDisassembler::Fail; 1644 1645 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1646 Inst.addOperand(MCOperand::createReg(Reg)); 1647 return MCDisassembler::Success; 1648 } 1649 1650 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1651 unsigned RegNo, 1652 uint64_t Address, 1653 const void *Decoder) { 1654 if (RegNo > 7) 1655 return MCDisassembler::Fail; 1656 1657 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1658 Inst.addOperand(MCOperand::createReg(Reg)); 1659 return MCDisassembler::Success; 1660 } 1661 1662 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1663 unsigned RegNo, 1664 uint64_t Address, 1665 const void *Decoder) { 1666 if (RegNo > 31) 1667 return MCDisassembler::Fail; 1668 1669 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1670 Inst.addOperand(MCOperand::createReg(Reg)); 1671 return MCDisassembler::Success; 1672 } 1673 1674 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1675 unsigned RegNo, 1676 uint64_t Address, 1677 const void *Decoder) { 1678 if (RegNo > 31) 1679 return MCDisassembler::Fail; 1680 1681 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1682 Inst.addOperand(MCOperand::createReg(Reg)); 1683 return MCDisassembler::Success; 1684 } 1685 1686 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1687 unsigned Offset, 1688 uint64_t Address, 1689 const void *Decoder) { 1690 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1691 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1692 return MCDisassembler::Success; 1693 } 1694 1695 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1696 unsigned Insn, 1697 uint64_t Address, 1698 const void *Decoder) { 1699 1700 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1701 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1702 return MCDisassembler::Success; 1703 } 1704 1705 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1706 unsigned Offset, 1707 uint64_t Address, 1708 const void *Decoder) { 1709 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1710 1711 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1712 return MCDisassembler::Success; 1713 } 1714 1715 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1716 unsigned Offset, 1717 uint64_t Address, 1718 const void *Decoder) { 1719 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1720 1721 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1722 return MCDisassembler::Success; 1723 } 1724 1725 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1726 unsigned Offset, 1727 uint64_t Address, 1728 const void *Decoder) { 1729 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1730 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1731 return MCDisassembler::Success; 1732 } 1733 1734 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1735 unsigned Offset, 1736 uint64_t Address, 1737 const void *Decoder) { 1738 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1739 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1740 return MCDisassembler::Success; 1741 } 1742 1743 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1744 unsigned Offset, 1745 uint64_t Address, 1746 const void *Decoder) { 1747 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1748 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1749 return MCDisassembler::Success; 1750 } 1751 1752 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1753 unsigned Insn, 1754 uint64_t Address, 1755 const void *Decoder) { 1756 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1757 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1758 return MCDisassembler::Success; 1759 } 1760 1761 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1762 unsigned Value, 1763 uint64_t Address, 1764 const void *Decoder) { 1765 if (Value == 0) 1766 Inst.addOperand(MCOperand::createImm(1)); 1767 else if (Value == 0x7) 1768 Inst.addOperand(MCOperand::createImm(-1)); 1769 else 1770 Inst.addOperand(MCOperand::createImm(Value << 2)); 1771 return MCDisassembler::Success; 1772 } 1773 1774 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1775 unsigned Value, 1776 uint64_t Address, 1777 const void *Decoder) { 1778 Inst.addOperand(MCOperand::createImm(Value << 2)); 1779 return MCDisassembler::Success; 1780 } 1781 1782 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1783 unsigned Value, 1784 uint64_t Address, 1785 const void *Decoder) { 1786 if (Value == 0x7F) 1787 Inst.addOperand(MCOperand::createImm(-1)); 1788 else 1789 Inst.addOperand(MCOperand::createImm(Value)); 1790 return MCDisassembler::Success; 1791 } 1792 1793 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1794 unsigned Value, 1795 uint64_t Address, 1796 const void *Decoder) { 1797 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1798 return MCDisassembler::Success; 1799 } 1800 1801 static DecodeStatus DecodeSimm4(MCInst &Inst, 1802 unsigned Value, 1803 uint64_t Address, 1804 const void *Decoder) { 1805 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); 1806 return MCDisassembler::Success; 1807 } 1808 1809 static DecodeStatus DecodeSimm16(MCInst &Inst, 1810 unsigned Insn, 1811 uint64_t Address, 1812 const void *Decoder) { 1813 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); 1814 return MCDisassembler::Success; 1815 } 1816 1817 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1818 unsigned Insn, 1819 uint64_t Address, 1820 const void *Decoder) { 1821 // We add one to the immediate field as it was encoded as 'imm - 1'. 1822 Inst.addOperand(MCOperand::createImm(Insn + 1)); 1823 return MCDisassembler::Success; 1824 } 1825 1826 static DecodeStatus DecodeInsSize(MCInst &Inst, 1827 unsigned Insn, 1828 uint64_t Address, 1829 const void *Decoder) { 1830 // First we need to grab the pos(lsb) from MCInst. 1831 int Pos = Inst.getOperand(2).getImm(); 1832 int Size = (int) Insn - Pos + 1; 1833 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1834 return MCDisassembler::Success; 1835 } 1836 1837 static DecodeStatus DecodeExtSize(MCInst &Inst, 1838 unsigned Insn, 1839 uint64_t Address, 1840 const void *Decoder) { 1841 int Size = (int) Insn + 1; 1842 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1843 return MCDisassembler::Success; 1844 } 1845 1846 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1847 uint64_t Address, const void *Decoder) { 1848 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1849 return MCDisassembler::Success; 1850 } 1851 1852 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1853 uint64_t Address, const void *Decoder) { 1854 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1855 return MCDisassembler::Success; 1856 } 1857 1858 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1859 uint64_t Address, const void *Decoder) { 1860 int32_t DecodedValue; 1861 switch (Insn) { 1862 case 0: DecodedValue = 256; break; 1863 case 1: DecodedValue = 257; break; 1864 case 510: DecodedValue = -258; break; 1865 case 511: DecodedValue = -257; break; 1866 default: DecodedValue = SignExtend32<9>(Insn); break; 1867 } 1868 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1869 return MCDisassembler::Success; 1870 } 1871 1872 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1873 uint64_t Address, const void *Decoder) { 1874 // Insn must be >= 0, since it is unsigned that condition is always true. 1875 assert(Insn < 16); 1876 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1877 255, 32768, 65535}; 1878 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 1879 return MCDisassembler::Success; 1880 } 1881 1882 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1883 uint64_t Address, const void *Decoder) { 1884 Inst.addOperand(MCOperand::createImm(Insn << 2)); 1885 return MCDisassembler::Success; 1886 } 1887 1888 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1889 unsigned Insn, 1890 uint64_t Address, 1891 const void *Decoder) { 1892 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1893 Mips::S6, Mips::FP}; 1894 unsigned RegNum; 1895 1896 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1897 // Empty register lists are not allowed. 1898 if (RegLst == 0) 1899 return MCDisassembler::Fail; 1900 1901 RegNum = RegLst & 0xf; 1902 for (unsigned i = 0; i < RegNum; i++) 1903 Inst.addOperand(MCOperand::createReg(Regs[i])); 1904 1905 if (RegLst & 0x10) 1906 Inst.addOperand(MCOperand::createReg(Mips::RA)); 1907 1908 return MCDisassembler::Success; 1909 } 1910 1911 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 1912 uint64_t Address, 1913 const void *Decoder) { 1914 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 1915 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 1916 unsigned RegNum = RegLst & 0x3; 1917 1918 for (unsigned i = 0; i <= RegNum; i++) 1919 Inst.addOperand(MCOperand::createReg(Regs[i])); 1920 1921 Inst.addOperand(MCOperand::createReg(Mips::RA)); 1922 1923 return MCDisassembler::Success; 1924 } 1925 1926 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 1927 uint64_t Address, const void *Decoder) { 1928 1929 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 1930 1931 switch (RegPair) { 1932 default: 1933 return MCDisassembler::Fail; 1934 case 0: 1935 Inst.addOperand(MCOperand::createReg(Mips::A1)); 1936 Inst.addOperand(MCOperand::createReg(Mips::A2)); 1937 break; 1938 case 1: 1939 Inst.addOperand(MCOperand::createReg(Mips::A1)); 1940 Inst.addOperand(MCOperand::createReg(Mips::A3)); 1941 break; 1942 case 2: 1943 Inst.addOperand(MCOperand::createReg(Mips::A2)); 1944 Inst.addOperand(MCOperand::createReg(Mips::A3)); 1945 break; 1946 case 3: 1947 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1948 Inst.addOperand(MCOperand::createReg(Mips::S5)); 1949 break; 1950 case 4: 1951 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1952 Inst.addOperand(MCOperand::createReg(Mips::S6)); 1953 break; 1954 case 5: 1955 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1956 Inst.addOperand(MCOperand::createReg(Mips::A1)); 1957 break; 1958 case 6: 1959 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1960 Inst.addOperand(MCOperand::createReg(Mips::A2)); 1961 break; 1962 case 7: 1963 Inst.addOperand(MCOperand::createReg(Mips::A0)); 1964 Inst.addOperand(MCOperand::createReg(Mips::A3)); 1965 break; 1966 } 1967 1968 return MCDisassembler::Success; 1969 } 1970 1971 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 1972 uint64_t Address, const void *Decoder) { 1973 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 1974 return MCDisassembler::Success; 1975 } 1976