1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/TargetRegistry.h" 25 26 using namespace llvm; 27 28 #define DEBUG_TYPE "mips-disassembler" 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 34 /// MipsDisassemblerBase - a disasembler class for Mips. 35 class MipsDisassemblerBase : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, 40 bool bigEndian) : 41 MCDisassembler(STI, Ctx), 42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {} 43 44 virtual ~MipsDisassemblerBase() {} 45 46 bool isN64() const { return IsN64; } 47 48 private: 49 bool IsN64; 50 protected: 51 bool isBigEndian; 52 }; 53 54 /// MipsDisassembler - a disasembler class for Mips32. 55 class MipsDisassembler : public MipsDisassemblerBase { 56 bool IsMicroMips; 57 public: 58 /// Constructor - Initializes the disassembler. 59 /// 60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 61 bool bigEndian) : 62 MipsDisassemblerBase(STI, Ctx, bigEndian) { 63 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 64 } 65 66 /// getInstruction - See MCDisassembler. 67 DecodeStatus getInstruction(MCInst &instr, 68 uint64_t &size, 69 const MemoryObject ®ion, 70 uint64_t address, 71 raw_ostream &vStream, 72 raw_ostream &cStream) const override; 73 }; 74 75 76 /// Mips64Disassembler - a disasembler class for Mips64. 77 class Mips64Disassembler : public MipsDisassemblerBase { 78 public: 79 /// Constructor - Initializes the disassembler. 80 /// 81 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 82 bool bigEndian) : 83 MipsDisassemblerBase(STI, Ctx, bigEndian) {} 84 85 /// getInstruction - See MCDisassembler. 86 DecodeStatus getInstruction(MCInst &instr, 87 uint64_t &size, 88 const MemoryObject ®ion, 89 uint64_t address, 90 raw_ostream &vStream, 91 raw_ostream &cStream) const override; 92 }; 93 94 } // end anonymous namespace 95 96 // Forward declare these because the autogenerated code will reference them. 97 // Definitions are further down. 98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 99 unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 114 unsigned Insn, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 129 unsigned RegNo, 130 uint64_t Address, 131 const void *Decoder); 132 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, 134 unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder); 137 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 139 unsigned RegNo, 140 uint64_t Address, 141 const void *Decoder); 142 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 144 unsigned RegNo, 145 uint64_t Address, 146 const void *Decoder); 147 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 149 unsigned Insn, 150 uint64_t Address, 151 const void *Decoder); 152 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 154 unsigned RegNo, 155 uint64_t Address, 156 const void *Decoder); 157 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 159 unsigned RegNo, 160 uint64_t Address, 161 const void *Decoder); 162 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder); 167 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 169 unsigned RegNo, 170 uint64_t Address, 171 const void *Decoder); 172 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 174 unsigned RegNo, 175 uint64_t Address, 176 const void *Decoder); 177 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 179 unsigned RegNo, 180 uint64_t Address, 181 const void *Decoder); 182 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 184 unsigned RegNo, 185 uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 189 unsigned RegNo, 190 uint64_t Address, 191 const void *Decoder); 192 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 194 unsigned RegNo, 195 uint64_t Address, 196 const void *Decoder); 197 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 199 unsigned Offset, 200 uint64_t Address, 201 const void *Decoder); 202 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 208 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 209 unsigned Offset, 210 uint64_t Address, 211 const void *Decoder); 212 213 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 228 unsigned Insn, 229 uint64_t Address, 230 const void *Decoder); 231 232 static DecodeStatus DecodeMem(MCInst &Inst, 233 unsigned Insn, 234 uint64_t Address, 235 const void *Decoder); 236 237 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 240 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 241 unsigned Insn, 242 uint64_t Address, 243 const void *Decoder); 244 245 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 246 unsigned Insn, 247 uint64_t Address, 248 const void *Decoder); 249 250 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 254 static DecodeStatus DecodeSimm16(MCInst &Inst, 255 unsigned Insn, 256 uint64_t Address, 257 const void *Decoder); 258 259 // Decode the immediate field of an LSA instruction which 260 // is off by one. 261 static DecodeStatus DecodeLSAImm(MCInst &Inst, 262 unsigned Insn, 263 uint64_t Address, 264 const void *Decoder); 265 266 static DecodeStatus DecodeInsSize(MCInst &Inst, 267 unsigned Insn, 268 uint64_t Address, 269 const void *Decoder); 270 271 static DecodeStatus DecodeExtSize(MCInst &Inst, 272 unsigned Insn, 273 uint64_t Address, 274 const void *Decoder); 275 276 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 279 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 280 /// handle. 281 template <typename InsnType> 282 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 283 const void *Decoder); 284 namespace llvm { 285 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 286 TheMips64elTarget; 287 } 288 289 static MCDisassembler *createMipsDisassembler( 290 const Target &T, 291 const MCSubtargetInfo &STI, 292 MCContext &Ctx) { 293 return new MipsDisassembler(STI, Ctx, true); 294 } 295 296 static MCDisassembler *createMipselDisassembler( 297 const Target &T, 298 const MCSubtargetInfo &STI, 299 MCContext &Ctx) { 300 return new MipsDisassembler(STI, Ctx, false); 301 } 302 303 static MCDisassembler *createMips64Disassembler( 304 const Target &T, 305 const MCSubtargetInfo &STI, 306 MCContext &Ctx) { 307 return new Mips64Disassembler(STI, Ctx, true); 308 } 309 310 static MCDisassembler *createMips64elDisassembler( 311 const Target &T, 312 const MCSubtargetInfo &STI, 313 MCContext &Ctx) { 314 return new Mips64Disassembler(STI, Ctx, false); 315 } 316 317 extern "C" void LLVMInitializeMipsDisassembler() { 318 // Register the disassembler. 319 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 320 createMipsDisassembler); 321 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 322 createMipselDisassembler); 323 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 324 createMips64Disassembler); 325 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 326 createMips64elDisassembler); 327 } 328 329 #include "MipsGenDisassemblerTables.inc" 330 331 template <typename InsnType> 332 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 333 const void *Decoder) { 334 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 335 // The size of the n field depends on the element size 336 // The register class also depends on this. 337 InsnType tmp = fieldFromInstruction(insn, 17, 5); 338 unsigned NSize = 0; 339 DecodeFN RegDecoder = nullptr; 340 if ((tmp & 0x18) == 0x00) { // INSVE_B 341 NSize = 4; 342 RegDecoder = DecodeMSA128BRegisterClass; 343 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 344 NSize = 3; 345 RegDecoder = DecodeMSA128HRegisterClass; 346 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 347 NSize = 2; 348 RegDecoder = DecodeMSA128WRegisterClass; 349 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 350 NSize = 1; 351 RegDecoder = DecodeMSA128DRegisterClass; 352 } else 353 llvm_unreachable("Invalid encoding"); 354 355 assert(NSize != 0 && RegDecoder != nullptr); 356 357 // $wd 358 tmp = fieldFromInstruction(insn, 6, 5); 359 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 360 return MCDisassembler::Fail; 361 // $wd_in 362 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 363 return MCDisassembler::Fail; 364 // $n 365 tmp = fieldFromInstruction(insn, 16, NSize); 366 MI.addOperand(MCOperand::CreateImm(tmp)); 367 // $ws 368 tmp = fieldFromInstruction(insn, 11, 5); 369 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 370 return MCDisassembler::Fail; 371 // $n2 372 MI.addOperand(MCOperand::CreateImm(0)); 373 374 return MCDisassembler::Success; 375 } 376 377 /// readInstruction - read four bytes from the MemoryObject 378 /// and return 32 bit word sorted according to the given endianess 379 static DecodeStatus readInstruction32(const MemoryObject ®ion, 380 uint64_t address, 381 uint64_t &size, 382 uint32_t &insn, 383 bool isBigEndian, 384 bool IsMicroMips) { 385 uint8_t Bytes[4]; 386 387 // We want to read exactly 4 Bytes of data. 388 if (region.readBytes(address, 4, Bytes) == -1) { 389 size = 0; 390 return MCDisassembler::Fail; 391 } 392 393 if (isBigEndian) { 394 // Encoded as a big-endian 32-bit word in the stream. 395 insn = (Bytes[3] << 0) | 396 (Bytes[2] << 8) | 397 (Bytes[1] << 16) | 398 (Bytes[0] << 24); 399 } 400 else { 401 // Encoded as a small-endian 32-bit word in the stream. 402 // Little-endian byte ordering: 403 // mips32r2: 4 | 3 | 2 | 1 404 // microMIPS: 2 | 1 | 4 | 3 405 if (IsMicroMips) { 406 insn = (Bytes[2] << 0) | 407 (Bytes[3] << 8) | 408 (Bytes[0] << 16) | 409 (Bytes[1] << 24); 410 } else { 411 insn = (Bytes[0] << 0) | 412 (Bytes[1] << 8) | 413 (Bytes[2] << 16) | 414 (Bytes[3] << 24); 415 } 416 } 417 418 return MCDisassembler::Success; 419 } 420 421 DecodeStatus 422 MipsDisassembler::getInstruction(MCInst &instr, 423 uint64_t &Size, 424 const MemoryObject &Region, 425 uint64_t Address, 426 raw_ostream &vStream, 427 raw_ostream &cStream) const { 428 uint32_t Insn; 429 430 DecodeStatus Result = readInstruction32(Region, Address, Size, 431 Insn, isBigEndian, IsMicroMips); 432 if (Result == MCDisassembler::Fail) 433 return MCDisassembler::Fail; 434 435 if (IsMicroMips) { 436 // Calling the auto-generated decoder function. 437 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, 438 this, STI); 439 if (Result != MCDisassembler::Fail) { 440 Size = 4; 441 return Result; 442 } 443 return MCDisassembler::Fail; 444 } 445 446 // Calling the auto-generated decoder function. 447 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, 448 this, STI); 449 if (Result != MCDisassembler::Fail) { 450 Size = 4; 451 return Result; 452 } 453 454 return MCDisassembler::Fail; 455 } 456 457 DecodeStatus 458 Mips64Disassembler::getInstruction(MCInst &instr, 459 uint64_t &Size, 460 const MemoryObject &Region, 461 uint64_t Address, 462 raw_ostream &vStream, 463 raw_ostream &cStream) const { 464 uint32_t Insn; 465 466 DecodeStatus Result = readInstruction32(Region, Address, Size, 467 Insn, isBigEndian, false); 468 if (Result == MCDisassembler::Fail) 469 return MCDisassembler::Fail; 470 471 // Calling the auto-generated decoder function. 472 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, 473 this, STI); 474 if (Result != MCDisassembler::Fail) { 475 Size = 4; 476 return Result; 477 } 478 // If we fail to decode in Mips64 decoder space we can try in Mips32 479 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, 480 this, STI); 481 if (Result != MCDisassembler::Fail) { 482 Size = 4; 483 return Result; 484 } 485 486 return MCDisassembler::Fail; 487 } 488 489 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 490 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); 491 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 492 return *(RegInfo->getRegClass(RC).begin() + RegNo); 493 } 494 495 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 496 unsigned RegNo, 497 uint64_t Address, 498 const void *Decoder) { 499 500 return MCDisassembler::Fail; 501 502 } 503 504 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 505 unsigned RegNo, 506 uint64_t Address, 507 const void *Decoder) { 508 509 if (RegNo > 31) 510 return MCDisassembler::Fail; 511 512 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 513 Inst.addOperand(MCOperand::CreateReg(Reg)); 514 return MCDisassembler::Success; 515 } 516 517 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 518 unsigned RegNo, 519 uint64_t Address, 520 const void *Decoder) { 521 if (RegNo > 31) 522 return MCDisassembler::Fail; 523 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 524 Inst.addOperand(MCOperand::CreateReg(Reg)); 525 return MCDisassembler::Success; 526 } 527 528 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 529 unsigned RegNo, 530 uint64_t Address, 531 const void *Decoder) { 532 if (static_cast<const MipsDisassembler *>(Decoder)->isN64()) 533 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 534 535 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 536 } 537 538 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 539 unsigned RegNo, 540 uint64_t Address, 541 const void *Decoder) { 542 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 543 } 544 545 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 546 unsigned RegNo, 547 uint64_t Address, 548 const void *Decoder) { 549 if (RegNo > 31) 550 return MCDisassembler::Fail; 551 552 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 553 Inst.addOperand(MCOperand::CreateReg(Reg)); 554 return MCDisassembler::Success; 555 } 556 557 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 558 unsigned RegNo, 559 uint64_t Address, 560 const void *Decoder) { 561 if (RegNo > 31) 562 return MCDisassembler::Fail; 563 564 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 565 Inst.addOperand(MCOperand::CreateReg(Reg)); 566 return MCDisassembler::Success; 567 } 568 569 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, 570 unsigned RegNo, 571 uint64_t Address, 572 const void *Decoder) { 573 if (RegNo > 31) 574 return MCDisassembler::Fail; 575 576 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo); 577 Inst.addOperand(MCOperand::CreateReg(Reg)); 578 return MCDisassembler::Success; 579 } 580 581 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 582 unsigned RegNo, 583 uint64_t Address, 584 const void *Decoder) { 585 if (RegNo > 31) 586 return MCDisassembler::Fail; 587 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 588 Inst.addOperand(MCOperand::CreateReg(Reg)); 589 return MCDisassembler::Success; 590 } 591 592 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 593 unsigned RegNo, 594 uint64_t Address, 595 const void *Decoder) { 596 if (RegNo > 7) 597 return MCDisassembler::Fail; 598 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 599 Inst.addOperand(MCOperand::CreateReg(Reg)); 600 return MCDisassembler::Success; 601 } 602 603 static DecodeStatus DecodeMem(MCInst &Inst, 604 unsigned Insn, 605 uint64_t Address, 606 const void *Decoder) { 607 int Offset = SignExtend32<16>(Insn & 0xffff); 608 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 609 unsigned Base = fieldFromInstruction(Insn, 21, 5); 610 611 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 612 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 613 614 if(Inst.getOpcode() == Mips::SC){ 615 Inst.addOperand(MCOperand::CreateReg(Reg)); 616 } 617 618 Inst.addOperand(MCOperand::CreateReg(Reg)); 619 Inst.addOperand(MCOperand::CreateReg(Base)); 620 Inst.addOperand(MCOperand::CreateImm(Offset)); 621 622 return MCDisassembler::Success; 623 } 624 625 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 626 uint64_t Address, const void *Decoder) { 627 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 628 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 629 unsigned Base = fieldFromInstruction(Insn, 11, 5); 630 631 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 632 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 633 634 Inst.addOperand(MCOperand::CreateReg(Reg)); 635 Inst.addOperand(MCOperand::CreateReg(Base)); 636 637 // The immediate field of an LD/ST instruction is scaled which means it must 638 // be multiplied (when decoding) by the size (in bytes) of the instructions' 639 // data format. 640 // .b - 1 byte 641 // .h - 2 bytes 642 // .w - 4 bytes 643 // .d - 8 bytes 644 switch(Inst.getOpcode()) 645 { 646 default: 647 assert (0 && "Unexpected instruction"); 648 return MCDisassembler::Fail; 649 break; 650 case Mips::LD_B: 651 case Mips::ST_B: 652 Inst.addOperand(MCOperand::CreateImm(Offset)); 653 break; 654 case Mips::LD_H: 655 case Mips::ST_H: 656 Inst.addOperand(MCOperand::CreateImm(Offset << 1)); 657 break; 658 case Mips::LD_W: 659 case Mips::ST_W: 660 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 661 break; 662 case Mips::LD_D: 663 case Mips::ST_D: 664 Inst.addOperand(MCOperand::CreateImm(Offset << 3)); 665 break; 666 } 667 668 return MCDisassembler::Success; 669 } 670 671 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 672 unsigned Insn, 673 uint64_t Address, 674 const void *Decoder) { 675 int Offset = SignExtend32<12>(Insn & 0x0fff); 676 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 677 unsigned Base = fieldFromInstruction(Insn, 16, 5); 678 679 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 680 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 681 682 if (Inst.getOpcode() == Mips::SC_MM) 683 Inst.addOperand(MCOperand::CreateReg(Reg)); 684 685 Inst.addOperand(MCOperand::CreateReg(Reg)); 686 Inst.addOperand(MCOperand::CreateReg(Base)); 687 Inst.addOperand(MCOperand::CreateImm(Offset)); 688 689 return MCDisassembler::Success; 690 } 691 692 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 693 unsigned Insn, 694 uint64_t Address, 695 const void *Decoder) { 696 int Offset = SignExtend32<16>(Insn & 0xffff); 697 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 698 unsigned Base = fieldFromInstruction(Insn, 16, 5); 699 700 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 701 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 702 703 Inst.addOperand(MCOperand::CreateReg(Reg)); 704 Inst.addOperand(MCOperand::CreateReg(Base)); 705 Inst.addOperand(MCOperand::CreateImm(Offset)); 706 707 return MCDisassembler::Success; 708 } 709 710 static DecodeStatus DecodeFMem(MCInst &Inst, 711 unsigned Insn, 712 uint64_t Address, 713 const void *Decoder) { 714 int Offset = SignExtend32<16>(Insn & 0xffff); 715 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 716 unsigned Base = fieldFromInstruction(Insn, 21, 5); 717 718 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 719 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 720 721 Inst.addOperand(MCOperand::CreateReg(Reg)); 722 Inst.addOperand(MCOperand::CreateReg(Base)); 723 Inst.addOperand(MCOperand::CreateImm(Offset)); 724 725 return MCDisassembler::Success; 726 } 727 728 729 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 730 unsigned RegNo, 731 uint64_t Address, 732 const void *Decoder) { 733 // Currently only hardware register 29 is supported. 734 if (RegNo != 29) 735 return MCDisassembler::Fail; 736 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); 737 return MCDisassembler::Success; 738 } 739 740 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 741 unsigned RegNo, 742 uint64_t Address, 743 const void *Decoder) { 744 if (RegNo > 30 || RegNo %2) 745 return MCDisassembler::Fail; 746 747 ; 748 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 749 Inst.addOperand(MCOperand::CreateReg(Reg)); 750 return MCDisassembler::Success; 751 } 752 753 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 754 unsigned RegNo, 755 uint64_t Address, 756 const void *Decoder) { 757 if (RegNo >= 4) 758 return MCDisassembler::Fail; 759 760 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 761 Inst.addOperand(MCOperand::CreateReg(Reg)); 762 return MCDisassembler::Success; 763 } 764 765 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 766 unsigned RegNo, 767 uint64_t Address, 768 const void *Decoder) { 769 if (RegNo >= 4) 770 return MCDisassembler::Fail; 771 772 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 773 Inst.addOperand(MCOperand::CreateReg(Reg)); 774 return MCDisassembler::Success; 775 } 776 777 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 778 unsigned RegNo, 779 uint64_t Address, 780 const void *Decoder) { 781 if (RegNo >= 4) 782 return MCDisassembler::Fail; 783 784 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 785 Inst.addOperand(MCOperand::CreateReg(Reg)); 786 return MCDisassembler::Success; 787 } 788 789 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 790 unsigned RegNo, 791 uint64_t Address, 792 const void *Decoder) { 793 if (RegNo > 31) 794 return MCDisassembler::Fail; 795 796 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 797 Inst.addOperand(MCOperand::CreateReg(Reg)); 798 return MCDisassembler::Success; 799 } 800 801 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 802 unsigned RegNo, 803 uint64_t Address, 804 const void *Decoder) { 805 if (RegNo > 31) 806 return MCDisassembler::Fail; 807 808 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 809 Inst.addOperand(MCOperand::CreateReg(Reg)); 810 return MCDisassembler::Success; 811 } 812 813 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 814 unsigned RegNo, 815 uint64_t Address, 816 const void *Decoder) { 817 if (RegNo > 31) 818 return MCDisassembler::Fail; 819 820 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 821 Inst.addOperand(MCOperand::CreateReg(Reg)); 822 return MCDisassembler::Success; 823 } 824 825 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 826 unsigned RegNo, 827 uint64_t Address, 828 const void *Decoder) { 829 if (RegNo > 31) 830 return MCDisassembler::Fail; 831 832 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 833 Inst.addOperand(MCOperand::CreateReg(Reg)); 834 return MCDisassembler::Success; 835 } 836 837 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 838 unsigned RegNo, 839 uint64_t Address, 840 const void *Decoder) { 841 if (RegNo > 7) 842 return MCDisassembler::Fail; 843 844 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 845 Inst.addOperand(MCOperand::CreateReg(Reg)); 846 return MCDisassembler::Success; 847 } 848 849 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 850 unsigned Offset, 851 uint64_t Address, 852 const void *Decoder) { 853 unsigned BranchOffset = Offset & 0xffff; 854 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4; 855 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 856 return MCDisassembler::Success; 857 } 858 859 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 860 unsigned Insn, 861 uint64_t Address, 862 const void *Decoder) { 863 864 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 865 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 866 return MCDisassembler::Success; 867 } 868 869 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 870 unsigned Offset, 871 uint64_t Address, 872 const void *Decoder) { 873 int32_t BranchOffset = SignExtend32<21>(Offset) << 2; 874 875 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 876 return MCDisassembler::Success; 877 } 878 879 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 880 unsigned Offset, 881 uint64_t Address, 882 const void *Decoder) { 883 int32_t BranchOffset = SignExtend32<26>(Offset) << 2; 884 885 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 886 return MCDisassembler::Success; 887 } 888 889 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 890 unsigned Offset, 891 uint64_t Address, 892 const void *Decoder) { 893 unsigned BranchOffset = Offset & 0xffff; 894 BranchOffset = SignExtend32<18>(BranchOffset << 1); 895 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 896 return MCDisassembler::Success; 897 } 898 899 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 900 unsigned Insn, 901 uint64_t Address, 902 const void *Decoder) { 903 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 904 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 905 return MCDisassembler::Success; 906 } 907 908 static DecodeStatus DecodeSimm16(MCInst &Inst, 909 unsigned Insn, 910 uint64_t Address, 911 const void *Decoder) { 912 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 913 return MCDisassembler::Success; 914 } 915 916 static DecodeStatus DecodeLSAImm(MCInst &Inst, 917 unsigned Insn, 918 uint64_t Address, 919 const void *Decoder) { 920 // We add one to the immediate field as it was encoded as 'imm - 1'. 921 Inst.addOperand(MCOperand::CreateImm(Insn + 1)); 922 return MCDisassembler::Success; 923 } 924 925 static DecodeStatus DecodeInsSize(MCInst &Inst, 926 unsigned Insn, 927 uint64_t Address, 928 const void *Decoder) { 929 // First we need to grab the pos(lsb) from MCInst. 930 int Pos = Inst.getOperand(2).getImm(); 931 int Size = (int) Insn - Pos + 1; 932 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 933 return MCDisassembler::Success; 934 } 935 936 static DecodeStatus DecodeExtSize(MCInst &Inst, 937 unsigned Insn, 938 uint64_t Address, 939 const void *Decoder) { 940 int Size = (int) Insn + 1; 941 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 942 return MCDisassembler::Success; 943 } 944 945 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 946 uint64_t Address, const void *Decoder) { 947 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2)); 948 return MCDisassembler::Success; 949 } 950