1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCTargetDesc.h" 15 #include "Mips.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeMem(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeMemEVA(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 291 const void *Decoder); 292 293 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 294 unsigned Insn, 295 uint64_t Address, 296 const void *Decoder); 297 298 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 299 unsigned Insn, 300 uint64_t Address, 301 const void *Decoder); 302 303 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 304 unsigned Insn, 305 uint64_t Address, 306 const void *Decoder); 307 308 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 309 unsigned Insn, 310 uint64_t Address, 311 const void *Decoder); 312 313 static DecodeStatus DecodeSyncI(MCInst &Inst, 314 unsigned Insn, 315 uint64_t Address, 316 const void *Decoder); 317 318 static DecodeStatus DecodeSynciR6(MCInst &Inst, 319 unsigned Insn, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 324 uint64_t Address, const void *Decoder); 325 326 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 327 unsigned Insn, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 332 unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 337 unsigned Insn, 338 uint64_t Address, 339 const void *Decoder); 340 341 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 342 unsigned Insn, 343 uint64_t Address, 344 const void *Decoder); 345 346 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 347 unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 352 unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 357 unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 370 const void *Decoder); 371 372 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 378 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 383 unsigned Insn, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 398 unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset, int Scale> 403 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder); 406 407 template <unsigned Bits, int Offset> 408 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 409 uint64_t Address, 410 const void *Decoder) { 411 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 412 Decoder); 413 } 414 415 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 416 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeInsSize(MCInst &Inst, 421 unsigned Insn, 422 uint64_t Address, 423 const void *Decoder); 424 425 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 426 uint64_t Address, const void *Decoder); 427 428 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void *Decoder); 430 431 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 432 uint64_t Address, const void *Decoder); 433 434 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void *Decoder); 436 437 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 438 uint64_t Address, const void *Decoder); 439 440 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 441 /// handle. 442 template <typename InsnType> 443 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 444 const void *Decoder); 445 446 template <typename InsnType> 447 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 452 const void *Decoder); 453 454 template <typename InsnType> 455 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus 464 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 465 const void *Decoder); 466 467 template <typename InsnType> 468 static DecodeStatus 469 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 470 const void *Decoder); 471 472 template <typename InsnType> 473 static DecodeStatus 474 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 475 const void *Decoder); 476 477 template <typename InsnType> 478 static DecodeStatus 479 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 480 const void *Decoder); 481 482 template <typename InsnType> 483 static DecodeStatus 484 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 485 const void *Decoder); 486 487 template <typename InsnType> 488 static DecodeStatus 489 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 490 const void *Decoder); 491 492 template <typename InsnType> 493 static DecodeStatus 494 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 495 const void *Decoder); 496 497 template <typename InsnType> 498 static DecodeStatus 499 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 500 const void *Decoder); 501 502 template <typename InsnType> 503 static DecodeStatus 504 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 505 const void *Decoder); 506 507 template <typename InsnType> 508 static DecodeStatus 509 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 510 const void *Decoder); 511 512 template <typename InsnType> 513 static DecodeStatus 514 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 515 const void *Decoder); 516 517 template <typename InsnType> 518 static DecodeStatus 519 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 520 const void *Decoder); 521 522 template <typename InsnType> 523 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 524 const void *Decoder); 525 526 template <typename InsnType> 527 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 528 const void *Decoder); 529 530 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 531 uint64_t Address, 532 const void *Decoder); 533 534 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 535 uint64_t Address, 536 const void *Decoder); 537 538 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 539 uint64_t Address, 540 const void *Decoder); 541 542 namespace llvm { 543 544 Target &getTheMipselTarget(); 545 Target &getTheMipsTarget(); 546 Target &getTheMips64Target(); 547 Target &getTheMips64elTarget(); 548 549 } // end namespace llvm 550 551 static MCDisassembler *createMipsDisassembler( 552 const Target &T, 553 const MCSubtargetInfo &STI, 554 MCContext &Ctx) { 555 return new MipsDisassembler(STI, Ctx, true); 556 } 557 558 static MCDisassembler *createMipselDisassembler( 559 const Target &T, 560 const MCSubtargetInfo &STI, 561 MCContext &Ctx) { 562 return new MipsDisassembler(STI, Ctx, false); 563 } 564 565 extern "C" void LLVMInitializeMipsDisassembler() { 566 // Register the disassembler. 567 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 568 createMipsDisassembler); 569 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 570 createMipselDisassembler); 571 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 572 createMipsDisassembler); 573 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 574 createMipselDisassembler); 575 } 576 577 #include "MipsGenDisassemblerTables.inc" 578 579 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 580 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 581 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 582 return *(RegInfo->getRegClass(RC).begin() + RegNo); 583 } 584 585 template <typename InsnType> 586 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 587 const void *Decoder) { 588 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 589 590 // The size of the n field depends on the element size 591 // The register class also depends on this. 592 InsnType tmp = fieldFromInstruction(insn, 17, 5); 593 unsigned NSize = 0; 594 DecodeFN RegDecoder = nullptr; 595 if ((tmp & 0x18) == 0x00) { // INSVE_B 596 NSize = 4; 597 RegDecoder = DecodeMSA128BRegisterClass; 598 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 599 NSize = 3; 600 RegDecoder = DecodeMSA128HRegisterClass; 601 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 602 NSize = 2; 603 RegDecoder = DecodeMSA128WRegisterClass; 604 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 605 NSize = 1; 606 RegDecoder = DecodeMSA128DRegisterClass; 607 } else 608 llvm_unreachable("Invalid encoding"); 609 610 assert(NSize != 0 && RegDecoder != nullptr); 611 612 // $wd 613 tmp = fieldFromInstruction(insn, 6, 5); 614 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 615 return MCDisassembler::Fail; 616 // $wd_in 617 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 618 return MCDisassembler::Fail; 619 // $n 620 tmp = fieldFromInstruction(insn, 16, NSize); 621 MI.addOperand(MCOperand::createImm(tmp)); 622 // $ws 623 tmp = fieldFromInstruction(insn, 11, 5); 624 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 625 return MCDisassembler::Fail; 626 // $n2 627 MI.addOperand(MCOperand::createImm(0)); 628 629 return MCDisassembler::Success; 630 } 631 632 template <typename InsnType> 633 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 634 const void *Decoder) { 635 InsnType Rs = fieldFromInstruction(insn, 16, 5); 636 InsnType Imm = fieldFromInstruction(insn, 0, 16); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 638 Rs))); 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 640 Rs))); 641 MI.addOperand(MCOperand::createImm(Imm)); 642 643 return MCDisassembler::Success; 644 } 645 646 template <typename InsnType> 647 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 648 const void *Decoder) { 649 InsnType Rs = fieldFromInstruction(insn, 21, 5); 650 InsnType Imm = fieldFromInstruction(insn, 0, 16); 651 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 652 Rs))); 653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 654 Rs))); 655 MI.addOperand(MCOperand::createImm(Imm)); 656 657 return MCDisassembler::Success; 658 } 659 660 template <typename InsnType> 661 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 662 uint64_t Address, 663 const void *Decoder) { 664 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 665 // (otherwise we would have matched the ADDI instruction from the earlier 666 // ISA's instead). 667 // 668 // We have: 669 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 670 // BOVC if rs >= rt 671 // BEQZALC if rs == 0 && rt != 0 672 // BEQC if rs < rt && rs != 0 673 674 InsnType Rs = fieldFromInstruction(insn, 21, 5); 675 InsnType Rt = fieldFromInstruction(insn, 16, 5); 676 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 677 bool HasRs = false; 678 679 if (Rs >= Rt) { 680 MI.setOpcode(Mips::BOVC); 681 HasRs = true; 682 } else if (Rs != 0 && Rs < Rt) { 683 MI.setOpcode(Mips::BEQC); 684 HasRs = true; 685 } else 686 MI.setOpcode(Mips::BEQZALC); 687 688 if (HasRs) 689 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 690 Rs))); 691 692 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 693 Rt))); 694 MI.addOperand(MCOperand::createImm(Imm)); 695 696 return MCDisassembler::Success; 697 } 698 699 template <typename InsnType> 700 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 701 uint64_t Address, 702 const void *Decoder) { 703 InsnType Rt = fieldFromInstruction(insn, 21, 5); 704 InsnType Rs = fieldFromInstruction(insn, 16, 5); 705 int64_t Imm = 0; 706 707 if (Rs >= Rt) { 708 MI.setOpcode(Mips::BOVC_MMR6); 709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 710 Rt))); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rs))); 713 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 714 } else if (Rs != 0 && Rs < Rt) { 715 MI.setOpcode(Mips::BEQC_MMR6); 716 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 717 Rs))); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rt))); 720 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 721 } else { 722 MI.setOpcode(Mips::BEQZALC_MMR6); 723 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 724 Rt))); 725 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 726 } 727 728 MI.addOperand(MCOperand::createImm(Imm)); 729 730 return MCDisassembler::Success; 731 } 732 733 template <typename InsnType> 734 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 735 uint64_t Address, 736 const void *Decoder) { 737 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 738 // (otherwise we would have matched the ADDI instruction from the earlier 739 // ISA's instead). 740 // 741 // We have: 742 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 743 // BNVC if rs >= rt 744 // BNEZALC if rs == 0 && rt != 0 745 // BNEC if rs < rt && rs != 0 746 747 InsnType Rs = fieldFromInstruction(insn, 21, 5); 748 InsnType Rt = fieldFromInstruction(insn, 16, 5); 749 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 750 bool HasRs = false; 751 752 if (Rs >= Rt) { 753 MI.setOpcode(Mips::BNVC); 754 HasRs = true; 755 } else if (Rs != 0 && Rs < Rt) { 756 MI.setOpcode(Mips::BNEC); 757 HasRs = true; 758 } else 759 MI.setOpcode(Mips::BNEZALC); 760 761 if (HasRs) 762 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 763 Rs))); 764 765 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 766 Rt))); 767 MI.addOperand(MCOperand::createImm(Imm)); 768 769 return MCDisassembler::Success; 770 } 771 772 template <typename InsnType> 773 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 774 uint64_t Address, 775 const void *Decoder) { 776 InsnType Rt = fieldFromInstruction(insn, 21, 5); 777 InsnType Rs = fieldFromInstruction(insn, 16, 5); 778 int64_t Imm = 0; 779 780 if (Rs >= Rt) { 781 MI.setOpcode(Mips::BNVC_MMR6); 782 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 783 Rt))); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rs))); 786 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 787 } else if (Rs != 0 && Rs < Rt) { 788 MI.setOpcode(Mips::BNEC_MMR6); 789 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 790 Rs))); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rt))); 793 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 794 } else { 795 MI.setOpcode(Mips::BNEZALC_MMR6); 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rt))); 798 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 799 } 800 801 MI.addOperand(MCOperand::createImm(Imm)); 802 803 return MCDisassembler::Success; 804 } 805 806 template <typename InsnType> 807 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 808 uint64_t Address, 809 const void *Decoder) { 810 // We have: 811 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 812 // Invalid if rt == 0 813 // BGTZC_MMR6 if rs == 0 && rt != 0 814 // BLTZC_MMR6 if rs == rt && rt != 0 815 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 816 817 InsnType Rt = fieldFromInstruction(insn, 21, 5); 818 InsnType Rs = fieldFromInstruction(insn, 16, 5); 819 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 820 bool HasRs = false; 821 822 if (Rt == 0) 823 return MCDisassembler::Fail; 824 else if (Rs == 0) 825 MI.setOpcode(Mips::BGTZC_MMR6); 826 else if (Rs == Rt) 827 MI.setOpcode(Mips::BLTZC_MMR6); 828 else { 829 MI.setOpcode(Mips::BLTC_MMR6); 830 HasRs = true; 831 } 832 833 if (HasRs) 834 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 835 Rs))); 836 837 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 838 Rt))); 839 840 MI.addOperand(MCOperand::createImm(Imm)); 841 842 return MCDisassembler::Success; 843 } 844 845 template <typename InsnType> 846 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 847 uint64_t Address, 848 const void *Decoder) { 849 // We have: 850 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 851 // Invalid if rt == 0 852 // BLEZC_MMR6 if rs == 0 && rt != 0 853 // BGEZC_MMR6 if rs == rt && rt != 0 854 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 855 856 InsnType Rt = fieldFromInstruction(insn, 21, 5); 857 InsnType Rs = fieldFromInstruction(insn, 16, 5); 858 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 859 bool HasRs = false; 860 861 if (Rt == 0) 862 return MCDisassembler::Fail; 863 else if (Rs == 0) 864 MI.setOpcode(Mips::BLEZC_MMR6); 865 else if (Rs == Rt) 866 MI.setOpcode(Mips::BGEZC_MMR6); 867 else { 868 HasRs = true; 869 MI.setOpcode(Mips::BGEC_MMR6); 870 } 871 872 if (HasRs) 873 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 874 Rs))); 875 876 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 877 Rt))); 878 879 MI.addOperand(MCOperand::createImm(Imm)); 880 881 return MCDisassembler::Success; 882 } 883 884 template <typename InsnType> 885 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 886 uint64_t Address, 887 const void *Decoder) { 888 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 889 // (otherwise we would have matched the BLEZL instruction from the earlier 890 // ISA's instead). 891 // 892 // We have: 893 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 894 // Invalid if rs == 0 895 // BLEZC if rs == 0 && rt != 0 896 // BGEZC if rs == rt && rt != 0 897 // BGEC if rs != rt && rs != 0 && rt != 0 898 899 InsnType Rs = fieldFromInstruction(insn, 21, 5); 900 InsnType Rt = fieldFromInstruction(insn, 16, 5); 901 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 902 bool HasRs = false; 903 904 if (Rt == 0) 905 return MCDisassembler::Fail; 906 else if (Rs == 0) 907 MI.setOpcode(Mips::BLEZC); 908 else if (Rs == Rt) 909 MI.setOpcode(Mips::BGEZC); 910 else { 911 HasRs = true; 912 MI.setOpcode(Mips::BGEC); 913 } 914 915 if (HasRs) 916 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 917 Rs))); 918 919 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 920 Rt))); 921 922 MI.addOperand(MCOperand::createImm(Imm)); 923 924 return MCDisassembler::Success; 925 } 926 927 template <typename InsnType> 928 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 929 uint64_t Address, 930 const void *Decoder) { 931 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 932 // (otherwise we would have matched the BGTZL instruction from the earlier 933 // ISA's instead). 934 // 935 // We have: 936 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 937 // Invalid if rs == 0 938 // BGTZC if rs == 0 && rt != 0 939 // BLTZC if rs == rt && rt != 0 940 // BLTC if rs != rt && rs != 0 && rt != 0 941 942 bool HasRs = false; 943 944 InsnType Rs = fieldFromInstruction(insn, 21, 5); 945 InsnType Rt = fieldFromInstruction(insn, 16, 5); 946 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 947 948 if (Rt == 0) 949 return MCDisassembler::Fail; 950 else if (Rs == 0) 951 MI.setOpcode(Mips::BGTZC); 952 else if (Rs == Rt) 953 MI.setOpcode(Mips::BLTZC); 954 else { 955 MI.setOpcode(Mips::BLTC); 956 HasRs = true; 957 } 958 959 if (HasRs) 960 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 961 Rs))); 962 963 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 964 Rt))); 965 966 MI.addOperand(MCOperand::createImm(Imm)); 967 968 return MCDisassembler::Success; 969 } 970 971 template <typename InsnType> 972 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 973 uint64_t Address, 974 const void *Decoder) { 975 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 976 // (otherwise we would have matched the BGTZ instruction from the earlier 977 // ISA's instead). 978 // 979 // We have: 980 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 981 // BGTZ if rt == 0 982 // BGTZALC if rs == 0 && rt != 0 983 // BLTZALC if rs != 0 && rs == rt 984 // BLTUC if rs != 0 && rs != rt 985 986 InsnType Rs = fieldFromInstruction(insn, 21, 5); 987 InsnType Rt = fieldFromInstruction(insn, 16, 5); 988 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 989 bool HasRs = false; 990 bool HasRt = false; 991 992 if (Rt == 0) { 993 MI.setOpcode(Mips::BGTZ); 994 HasRs = true; 995 } else if (Rs == 0) { 996 MI.setOpcode(Mips::BGTZALC); 997 HasRt = true; 998 } else if (Rs == Rt) { 999 MI.setOpcode(Mips::BLTZALC); 1000 HasRs = true; 1001 } else { 1002 MI.setOpcode(Mips::BLTUC); 1003 HasRs = true; 1004 HasRt = true; 1005 } 1006 1007 if (HasRs) 1008 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1009 Rs))); 1010 1011 if (HasRt) 1012 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1013 Rt))); 1014 1015 MI.addOperand(MCOperand::createImm(Imm)); 1016 1017 return MCDisassembler::Success; 1018 } 1019 1020 template <typename InsnType> 1021 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1022 uint64_t Address, 1023 const void *Decoder) { 1024 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1025 // (otherwise we would have matched the BLEZL instruction from the earlier 1026 // ISA's instead). 1027 // 1028 // We have: 1029 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1030 // Invalid if rs == 0 1031 // BLEZALC if rs == 0 && rt != 0 1032 // BGEZALC if rs == rt && rt != 0 1033 // BGEUC if rs != rt && rs != 0 && rt != 0 1034 1035 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1036 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1037 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1038 bool HasRs = false; 1039 1040 if (Rt == 0) 1041 return MCDisassembler::Fail; 1042 else if (Rs == 0) 1043 MI.setOpcode(Mips::BLEZALC); 1044 else if (Rs == Rt) 1045 MI.setOpcode(Mips::BGEZALC); 1046 else { 1047 HasRs = true; 1048 MI.setOpcode(Mips::BGEUC); 1049 } 1050 1051 if (HasRs) 1052 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1053 Rs))); 1054 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1055 Rt))); 1056 1057 MI.addOperand(MCOperand::createImm(Imm)); 1058 1059 return MCDisassembler::Success; 1060 } 1061 1062 // Override the generated disassembler to produce DEXT all the time. This is 1063 // for feature / behaviour parity with binutils. 1064 template <typename InsnType> 1065 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1066 const void *Decoder) { 1067 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1068 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1069 unsigned Size = 0; 1070 unsigned Pos = 0; 1071 1072 switch (MI.getOpcode()) { 1073 case Mips::DEXT: 1074 Pos = Lsb; 1075 Size = Msbd + 1; 1076 break; 1077 case Mips::DEXTM: 1078 Pos = Lsb; 1079 Size = Msbd + 1 + 32; 1080 break; 1081 case Mips::DEXTU: 1082 Pos = Lsb + 32; 1083 Size = Msbd + 1; 1084 break; 1085 default: 1086 llvm_unreachable("Unknown DEXT instruction!"); 1087 } 1088 1089 MI.setOpcode(Mips::DEXT); 1090 1091 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1092 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1093 1094 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1095 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1096 MI.addOperand(MCOperand::createImm(Pos)); 1097 MI.addOperand(MCOperand::createImm(Size)); 1098 1099 return MCDisassembler::Success; 1100 } 1101 1102 // Override the generated disassembler to produce DINS all the time. This is 1103 // for feature / behaviour parity with binutils. 1104 template <typename InsnType> 1105 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1106 const void *Decoder) { 1107 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1108 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1109 unsigned Size = 0; 1110 unsigned Pos = 0; 1111 1112 switch (MI.getOpcode()) { 1113 case Mips::DINS: 1114 Pos = Lsb; 1115 Size = Msbd + 1 - Pos; 1116 break; 1117 case Mips::DINSM: 1118 Pos = Lsb; 1119 Size = Msbd + 33 - Pos; 1120 break; 1121 case Mips::DINSU: 1122 Pos = Lsb + 32; 1123 // mbsd = pos + size - 33 1124 // mbsd - pos + 33 = size 1125 Size = Msbd + 33 - Pos; 1126 break; 1127 default: 1128 llvm_unreachable("Unknown DINS instruction!"); 1129 } 1130 1131 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1132 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1133 1134 MI.setOpcode(Mips::DINS); 1135 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1136 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1137 MI.addOperand(MCOperand::createImm(Pos)); 1138 MI.addOperand(MCOperand::createImm(Size)); 1139 1140 return MCDisassembler::Success; 1141 } 1142 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1143 /// according to the given endianness. 1144 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1145 uint64_t &Size, uint32_t &Insn, 1146 bool IsBigEndian) { 1147 // We want to read exactly 2 Bytes of data. 1148 if (Bytes.size() < 2) { 1149 Size = 0; 1150 return MCDisassembler::Fail; 1151 } 1152 1153 if (IsBigEndian) { 1154 Insn = (Bytes[0] << 8) | Bytes[1]; 1155 } else { 1156 Insn = (Bytes[1] << 8) | Bytes[0]; 1157 } 1158 1159 return MCDisassembler::Success; 1160 } 1161 1162 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1163 /// according to the given endianness. 1164 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1165 uint64_t &Size, uint32_t &Insn, 1166 bool IsBigEndian, bool IsMicroMips) { 1167 // We want to read exactly 4 Bytes of data. 1168 if (Bytes.size() < 4) { 1169 Size = 0; 1170 return MCDisassembler::Fail; 1171 } 1172 1173 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1174 // always precede the low 16 bits in the instruction stream (that is, they 1175 // are placed at lower addresses in the instruction stream). 1176 // 1177 // microMIPS byte ordering: 1178 // Big-endian: 0 | 1 | 2 | 3 1179 // Little-endian: 1 | 0 | 3 | 2 1180 1181 if (IsBigEndian) { 1182 // Encoded as a big-endian 32-bit word in the stream. 1183 Insn = 1184 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1185 } else { 1186 if (IsMicroMips) { 1187 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1188 (Bytes[1] << 24); 1189 } else { 1190 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1191 (Bytes[3] << 24); 1192 } 1193 } 1194 1195 return MCDisassembler::Success; 1196 } 1197 1198 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1199 ArrayRef<uint8_t> Bytes, 1200 uint64_t Address, 1201 raw_ostream &VStream, 1202 raw_ostream &CStream) const { 1203 uint32_t Insn; 1204 DecodeStatus Result; 1205 Size = 0; 1206 1207 if (IsMicroMips) { 1208 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1209 if (Result == MCDisassembler::Fail) 1210 return MCDisassembler::Fail; 1211 1212 if (hasMips32r6()) { 1213 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1214 // Calling the auto-generated decoder function for microMIPS32R6 1215 // 16-bit instructions. 1216 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1217 Address, this, STI); 1218 if (Result != MCDisassembler::Fail) { 1219 Size = 2; 1220 return Result; 1221 } 1222 } 1223 1224 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1225 // Calling the auto-generated decoder function for microMIPS 16-bit 1226 // instructions. 1227 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1228 this, STI); 1229 if (Result != MCDisassembler::Fail) { 1230 Size = 2; 1231 return Result; 1232 } 1233 1234 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1235 if (Result == MCDisassembler::Fail) 1236 return MCDisassembler::Fail; 1237 1238 if (hasMips32r6()) { 1239 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1240 // Calling the auto-generated decoder function. 1241 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1242 this, STI); 1243 if (Result != MCDisassembler::Fail) { 1244 Size = 4; 1245 return Result; 1246 } 1247 } 1248 1249 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1250 // Calling the auto-generated decoder function. 1251 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1252 this, STI); 1253 if (Result != MCDisassembler::Fail) { 1254 Size = 4; 1255 return Result; 1256 } 1257 1258 if (isFP64()) { 1259 DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1260 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1261 Address, this, STI); 1262 if (Result != MCDisassembler::Fail) { 1263 Size = 4; 1264 return Result; 1265 } 1266 } 1267 1268 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1269 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1270 // could form a valid instruction. The two bytes we rejected as an 1271 // instruction could have actually beeen an inline constant pool that is 1272 // unconditionally branched over. 1273 Size = 2; 1274 return MCDisassembler::Fail; 1275 } 1276 1277 // Attempt to read the instruction so that we can attempt to decode it. If 1278 // the buffer is not 4 bytes long, let the higher level logic figure out 1279 // what to do with a size of zero and MCDisassembler::Fail. 1280 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1281 if (Result == MCDisassembler::Fail) 1282 return MCDisassembler::Fail; 1283 1284 // The only instruction size for standard encoded MIPS. 1285 Size = 4; 1286 1287 if (hasCOP3()) { 1288 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1289 Result = 1290 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1291 if (Result != MCDisassembler::Fail) 1292 return Result; 1293 } 1294 1295 if (hasMips32r6() && isGP64()) { 1296 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1297 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1298 Address, this, STI); 1299 if (Result != MCDisassembler::Fail) 1300 return Result; 1301 } 1302 1303 if (hasMips32r6() && isPTR64()) { 1304 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1305 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1306 Address, this, STI); 1307 if (Result != MCDisassembler::Fail) 1308 return Result; 1309 } 1310 1311 if (hasMips32r6()) { 1312 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1313 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1314 Address, this, STI); 1315 if (Result != MCDisassembler::Fail) 1316 return Result; 1317 } 1318 1319 if (hasMips2() && isPTR64()) { 1320 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1321 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1322 Address, this, STI); 1323 if (Result != MCDisassembler::Fail) 1324 return Result; 1325 } 1326 1327 if (hasCnMips()) { 1328 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1329 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1330 Address, this, STI); 1331 if (Result != MCDisassembler::Fail) 1332 return Result; 1333 } 1334 1335 if (isGP64()) { 1336 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1337 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1338 Address, this, STI); 1339 if (Result != MCDisassembler::Fail) 1340 return Result; 1341 } 1342 1343 if (isFP64()) { 1344 DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1345 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1346 Address, this, STI); 1347 if (Result != MCDisassembler::Fail) 1348 return Result; 1349 } 1350 1351 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1352 // Calling the auto-generated decoder function. 1353 Result = 1354 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1355 if (Result != MCDisassembler::Fail) 1356 return Result; 1357 1358 return MCDisassembler::Fail; 1359 } 1360 1361 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1362 unsigned RegNo, 1363 uint64_t Address, 1364 const void *Decoder) { 1365 return MCDisassembler::Fail; 1366 } 1367 1368 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1369 unsigned RegNo, 1370 uint64_t Address, 1371 const void *Decoder) { 1372 if (RegNo > 31) 1373 return MCDisassembler::Fail; 1374 1375 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1376 Inst.addOperand(MCOperand::createReg(Reg)); 1377 return MCDisassembler::Success; 1378 } 1379 1380 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1381 unsigned RegNo, 1382 uint64_t Address, 1383 const void *Decoder) { 1384 if (RegNo > 7) 1385 return MCDisassembler::Fail; 1386 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1387 Inst.addOperand(MCOperand::createReg(Reg)); 1388 return MCDisassembler::Success; 1389 } 1390 1391 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1392 unsigned RegNo, 1393 uint64_t Address, 1394 const void *Decoder) { 1395 if (RegNo > 7) 1396 return MCDisassembler::Fail; 1397 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1398 Inst.addOperand(MCOperand::createReg(Reg)); 1399 return MCDisassembler::Success; 1400 } 1401 1402 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1403 unsigned RegNo, 1404 uint64_t Address, 1405 const void *Decoder) { 1406 if (RegNo > 7) 1407 return MCDisassembler::Fail; 1408 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1409 Inst.addOperand(MCOperand::createReg(Reg)); 1410 return MCDisassembler::Success; 1411 } 1412 1413 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1414 unsigned RegNo, 1415 uint64_t Address, 1416 const void *Decoder) { 1417 if (RegNo > 31) 1418 return MCDisassembler::Fail; 1419 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1420 Inst.addOperand(MCOperand::createReg(Reg)); 1421 return MCDisassembler::Success; 1422 } 1423 1424 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1425 unsigned RegNo, 1426 uint64_t Address, 1427 const void *Decoder) { 1428 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1429 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1430 1431 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1432 } 1433 1434 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1435 unsigned RegNo, 1436 uint64_t Address, 1437 const void *Decoder) { 1438 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1439 } 1440 1441 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1442 unsigned RegNo, 1443 uint64_t Address, 1444 const void *Decoder) { 1445 if (RegNo > 31) 1446 return MCDisassembler::Fail; 1447 1448 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1449 Inst.addOperand(MCOperand::createReg(Reg)); 1450 return MCDisassembler::Success; 1451 } 1452 1453 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1454 unsigned RegNo, 1455 uint64_t Address, 1456 const void *Decoder) { 1457 if (RegNo > 31) 1458 return MCDisassembler::Fail; 1459 1460 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1461 Inst.addOperand(MCOperand::createReg(Reg)); 1462 return MCDisassembler::Success; 1463 } 1464 1465 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1466 unsigned RegNo, 1467 uint64_t Address, 1468 const void *Decoder) { 1469 if (RegNo > 31) 1470 return MCDisassembler::Fail; 1471 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1472 Inst.addOperand(MCOperand::createReg(Reg)); 1473 return MCDisassembler::Success; 1474 } 1475 1476 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1477 unsigned RegNo, 1478 uint64_t Address, 1479 const void *Decoder) { 1480 if (RegNo > 7) 1481 return MCDisassembler::Fail; 1482 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1483 Inst.addOperand(MCOperand::createReg(Reg)); 1484 return MCDisassembler::Success; 1485 } 1486 1487 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1488 uint64_t Address, 1489 const void *Decoder) { 1490 if (RegNo > 31) 1491 return MCDisassembler::Fail; 1492 1493 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1494 Inst.addOperand(MCOperand::createReg(Reg)); 1495 return MCDisassembler::Success; 1496 } 1497 1498 static DecodeStatus DecodeMem(MCInst &Inst, 1499 unsigned Insn, 1500 uint64_t Address, 1501 const void *Decoder) { 1502 int Offset = SignExtend32<16>(Insn & 0xffff); 1503 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1504 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1505 1506 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1507 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1508 1509 if (Inst.getOpcode() == Mips::SC || 1510 Inst.getOpcode() == Mips::SCD) 1511 Inst.addOperand(MCOperand::createReg(Reg)); 1512 1513 Inst.addOperand(MCOperand::createReg(Reg)); 1514 Inst.addOperand(MCOperand::createReg(Base)); 1515 Inst.addOperand(MCOperand::createImm(Offset)); 1516 1517 return MCDisassembler::Success; 1518 } 1519 1520 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1521 unsigned Insn, 1522 uint64_t Address, 1523 const void *Decoder) { 1524 int Offset = SignExtend32<9>(Insn >> 7); 1525 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1526 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1527 1528 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1529 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1530 1531 if (Inst.getOpcode() == Mips::SCE) 1532 Inst.addOperand(MCOperand::createReg(Reg)); 1533 1534 Inst.addOperand(MCOperand::createReg(Reg)); 1535 Inst.addOperand(MCOperand::createReg(Base)); 1536 Inst.addOperand(MCOperand::createImm(Offset)); 1537 1538 return MCDisassembler::Success; 1539 } 1540 1541 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1542 unsigned Insn, 1543 uint64_t Address, 1544 const void *Decoder) { 1545 int Offset = SignExtend32<9>(Insn & 0x1ff); 1546 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1547 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1548 1549 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1550 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1551 1552 Inst.addOperand(MCOperand::createReg(Reg)); 1553 Inst.addOperand(MCOperand::createReg(Base)); 1554 Inst.addOperand(MCOperand::createImm(Offset)); 1555 1556 return MCDisassembler::Success; 1557 } 1558 1559 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1560 unsigned Insn, 1561 uint64_t Address, 1562 const void *Decoder) { 1563 int Offset = SignExtend32<16>(Insn & 0xffff); 1564 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1565 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1566 1567 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1568 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1569 1570 Inst.addOperand(MCOperand::createReg(Reg)); 1571 Inst.addOperand(MCOperand::createReg(Base)); 1572 Inst.addOperand(MCOperand::createImm(Offset)); 1573 1574 return MCDisassembler::Success; 1575 } 1576 1577 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1578 unsigned Insn, 1579 uint64_t Address, 1580 const void *Decoder) { 1581 int Offset = SignExtend32<16>(Insn & 0xffff); 1582 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1583 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1584 1585 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1586 1587 Inst.addOperand(MCOperand::createReg(Base)); 1588 Inst.addOperand(MCOperand::createImm(Offset)); 1589 Inst.addOperand(MCOperand::createImm(Hint)); 1590 1591 return MCDisassembler::Success; 1592 } 1593 1594 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1595 unsigned Insn, 1596 uint64_t Address, 1597 const void *Decoder) { 1598 int Offset = SignExtend32<12>(Insn & 0xfff); 1599 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1600 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1601 1602 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1603 1604 Inst.addOperand(MCOperand::createReg(Base)); 1605 Inst.addOperand(MCOperand::createImm(Offset)); 1606 Inst.addOperand(MCOperand::createImm(Hint)); 1607 1608 return MCDisassembler::Success; 1609 } 1610 1611 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1612 unsigned Insn, 1613 uint64_t Address, 1614 const void *Decoder) { 1615 int Offset = SignExtend32<9>(Insn & 0x1ff); 1616 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1617 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1618 1619 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1620 1621 Inst.addOperand(MCOperand::createReg(Base)); 1622 Inst.addOperand(MCOperand::createImm(Offset)); 1623 Inst.addOperand(MCOperand::createImm(Hint)); 1624 1625 return MCDisassembler::Success; 1626 } 1627 1628 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1629 unsigned Insn, 1630 uint64_t Address, 1631 const void *Decoder) { 1632 int Offset = SignExtend32<9>(Insn >> 7); 1633 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1634 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1635 1636 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1637 1638 Inst.addOperand(MCOperand::createReg(Base)); 1639 Inst.addOperand(MCOperand::createImm(Offset)); 1640 Inst.addOperand(MCOperand::createImm(Hint)); 1641 1642 return MCDisassembler::Success; 1643 } 1644 1645 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1646 unsigned Insn, 1647 uint64_t Address, 1648 const void *Decoder) { 1649 int Offset = SignExtend32<9>(Insn & 0x1ff); 1650 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1651 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1652 1653 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1654 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1655 1656 Inst.addOperand(MCOperand::createReg(Reg)); 1657 Inst.addOperand(MCOperand::createReg(Base)); 1658 Inst.addOperand(MCOperand::createImm(Offset)); 1659 1660 return MCDisassembler::Success; 1661 } 1662 1663 static DecodeStatus DecodeSyncI(MCInst &Inst, 1664 unsigned Insn, 1665 uint64_t Address, 1666 const void *Decoder) { 1667 int Offset = SignExtend32<16>(Insn & 0xffff); 1668 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1669 1670 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1671 1672 Inst.addOperand(MCOperand::createReg(Base)); 1673 Inst.addOperand(MCOperand::createImm(Offset)); 1674 1675 return MCDisassembler::Success; 1676 } 1677 1678 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1679 unsigned Insn, 1680 uint64_t Address, 1681 const void *Decoder) { 1682 int Immediate = SignExtend32<16>(Insn & 0xffff); 1683 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1684 1685 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1686 1687 Inst.addOperand(MCOperand::createReg(Base)); 1688 Inst.addOperand(MCOperand::createImm(Immediate)); 1689 1690 return MCDisassembler::Success; 1691 } 1692 1693 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1694 uint64_t Address, const void *Decoder) { 1695 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1696 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1697 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1698 1699 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1700 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1701 1702 Inst.addOperand(MCOperand::createReg(Reg)); 1703 Inst.addOperand(MCOperand::createReg(Base)); 1704 1705 // The immediate field of an LD/ST instruction is scaled which means it must 1706 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1707 // data format. 1708 // .b - 1 byte 1709 // .h - 2 bytes 1710 // .w - 4 bytes 1711 // .d - 8 bytes 1712 switch(Inst.getOpcode()) 1713 { 1714 default: 1715 assert(false && "Unexpected instruction"); 1716 return MCDisassembler::Fail; 1717 break; 1718 case Mips::LD_B: 1719 case Mips::ST_B: 1720 Inst.addOperand(MCOperand::createImm(Offset)); 1721 break; 1722 case Mips::LD_H: 1723 case Mips::ST_H: 1724 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1725 break; 1726 case Mips::LD_W: 1727 case Mips::ST_W: 1728 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1729 break; 1730 case Mips::LD_D: 1731 case Mips::ST_D: 1732 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1733 break; 1734 } 1735 1736 return MCDisassembler::Success; 1737 } 1738 1739 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1740 unsigned Insn, 1741 uint64_t Address, 1742 const void *Decoder) { 1743 unsigned Offset = Insn & 0xf; 1744 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1745 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1746 1747 switch (Inst.getOpcode()) { 1748 case Mips::LBU16_MM: 1749 case Mips::LHU16_MM: 1750 case Mips::LW16_MM: 1751 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1752 == MCDisassembler::Fail) 1753 return MCDisassembler::Fail; 1754 break; 1755 case Mips::SB16_MM: 1756 case Mips::SB16_MMR6: 1757 case Mips::SH16_MM: 1758 case Mips::SH16_MMR6: 1759 case Mips::SW16_MM: 1760 case Mips::SW16_MMR6: 1761 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1762 == MCDisassembler::Fail) 1763 return MCDisassembler::Fail; 1764 break; 1765 } 1766 1767 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1768 == MCDisassembler::Fail) 1769 return MCDisassembler::Fail; 1770 1771 switch (Inst.getOpcode()) { 1772 case Mips::LBU16_MM: 1773 if (Offset == 0xf) 1774 Inst.addOperand(MCOperand::createImm(-1)); 1775 else 1776 Inst.addOperand(MCOperand::createImm(Offset)); 1777 break; 1778 case Mips::SB16_MM: 1779 case Mips::SB16_MMR6: 1780 Inst.addOperand(MCOperand::createImm(Offset)); 1781 break; 1782 case Mips::LHU16_MM: 1783 case Mips::SH16_MM: 1784 case Mips::SH16_MMR6: 1785 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1786 break; 1787 case Mips::LW16_MM: 1788 case Mips::SW16_MM: 1789 case Mips::SW16_MMR6: 1790 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1791 break; 1792 } 1793 1794 return MCDisassembler::Success; 1795 } 1796 1797 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1798 unsigned Insn, 1799 uint64_t Address, 1800 const void *Decoder) { 1801 unsigned Offset = Insn & 0x1F; 1802 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1803 1804 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1805 1806 Inst.addOperand(MCOperand::createReg(Reg)); 1807 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1808 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1809 1810 return MCDisassembler::Success; 1811 } 1812 1813 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1814 unsigned Insn, 1815 uint64_t Address, 1816 const void *Decoder) { 1817 unsigned Offset = Insn & 0x7F; 1818 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1819 1820 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1821 1822 Inst.addOperand(MCOperand::createReg(Reg)); 1823 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1824 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1825 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1830 unsigned Insn, 1831 uint64_t Address, 1832 const void *Decoder) { 1833 int Offset; 1834 switch (Inst.getOpcode()) { 1835 case Mips::LWM16_MMR6: 1836 case Mips::SWM16_MMR6: 1837 Offset = fieldFromInstruction(Insn, 4, 4); 1838 break; 1839 default: 1840 Offset = SignExtend32<4>(Insn & 0xf); 1841 break; 1842 } 1843 1844 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1845 == MCDisassembler::Fail) 1846 return MCDisassembler::Fail; 1847 1848 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1849 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1850 1851 return MCDisassembler::Success; 1852 } 1853 1854 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1855 unsigned Insn, 1856 uint64_t Address, 1857 const void *Decoder) { 1858 int Offset = SignExtend32<9>(Insn & 0x1ff); 1859 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1860 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1861 1862 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1863 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1864 1865 if (Inst.getOpcode() == Mips::SCE_MM) 1866 Inst.addOperand(MCOperand::createReg(Reg)); 1867 1868 Inst.addOperand(MCOperand::createReg(Reg)); 1869 Inst.addOperand(MCOperand::createReg(Base)); 1870 Inst.addOperand(MCOperand::createImm(Offset)); 1871 1872 return MCDisassembler::Success; 1873 } 1874 1875 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1876 unsigned Insn, 1877 uint64_t Address, 1878 const void *Decoder) { 1879 int Offset = SignExtend32<12>(Insn & 0x0fff); 1880 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1881 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1882 1883 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1884 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1885 1886 switch (Inst.getOpcode()) { 1887 case Mips::SWM32_MM: 1888 case Mips::LWM32_MM: 1889 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1890 == MCDisassembler::Fail) 1891 return MCDisassembler::Fail; 1892 Inst.addOperand(MCOperand::createReg(Base)); 1893 Inst.addOperand(MCOperand::createImm(Offset)); 1894 break; 1895 case Mips::SC_MM: 1896 Inst.addOperand(MCOperand::createReg(Reg)); 1897 LLVM_FALLTHROUGH; 1898 default: 1899 Inst.addOperand(MCOperand::createReg(Reg)); 1900 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1901 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1902 Inst.addOperand(MCOperand::createReg(Reg+1)); 1903 1904 Inst.addOperand(MCOperand::createReg(Base)); 1905 Inst.addOperand(MCOperand::createImm(Offset)); 1906 } 1907 1908 return MCDisassembler::Success; 1909 } 1910 1911 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1912 unsigned Insn, 1913 uint64_t Address, 1914 const void *Decoder) { 1915 int Offset = SignExtend32<16>(Insn & 0xffff); 1916 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1917 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1918 1919 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1920 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1921 1922 Inst.addOperand(MCOperand::createReg(Reg)); 1923 Inst.addOperand(MCOperand::createReg(Base)); 1924 Inst.addOperand(MCOperand::createImm(Offset)); 1925 1926 return MCDisassembler::Success; 1927 } 1928 1929 static DecodeStatus DecodeFMem(MCInst &Inst, 1930 unsigned Insn, 1931 uint64_t Address, 1932 const void *Decoder) { 1933 int Offset = SignExtend32<16>(Insn & 0xffff); 1934 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1935 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1936 1937 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1938 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1939 1940 Inst.addOperand(MCOperand::createReg(Reg)); 1941 Inst.addOperand(MCOperand::createReg(Base)); 1942 Inst.addOperand(MCOperand::createImm(Offset)); 1943 1944 return MCDisassembler::Success; 1945 } 1946 1947 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1948 uint64_t Address, const void *Decoder) { 1949 // This function is the same as DecodeFMem but with the Reg and Base fields 1950 // swapped according to microMIPS spec. 1951 int Offset = SignExtend32<16>(Insn & 0xffff); 1952 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1953 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1954 1955 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1956 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1957 1958 Inst.addOperand(MCOperand::createReg(Reg)); 1959 Inst.addOperand(MCOperand::createReg(Base)); 1960 Inst.addOperand(MCOperand::createImm(Offset)); 1961 1962 return MCDisassembler::Success; 1963 } 1964 1965 static DecodeStatus DecodeFMem2(MCInst &Inst, 1966 unsigned Insn, 1967 uint64_t Address, 1968 const void *Decoder) { 1969 int Offset = SignExtend32<16>(Insn & 0xffff); 1970 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1971 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1972 1973 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1974 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1975 1976 Inst.addOperand(MCOperand::createReg(Reg)); 1977 Inst.addOperand(MCOperand::createReg(Base)); 1978 Inst.addOperand(MCOperand::createImm(Offset)); 1979 1980 return MCDisassembler::Success; 1981 } 1982 1983 static DecodeStatus DecodeFMem3(MCInst &Inst, 1984 unsigned Insn, 1985 uint64_t Address, 1986 const void *Decoder) { 1987 int Offset = SignExtend32<16>(Insn & 0xffff); 1988 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1989 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1990 1991 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1992 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1993 1994 Inst.addOperand(MCOperand::createReg(Reg)); 1995 Inst.addOperand(MCOperand::createReg(Base)); 1996 Inst.addOperand(MCOperand::createImm(Offset)); 1997 1998 return MCDisassembler::Success; 1999 } 2000 2001 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2002 unsigned Insn, 2003 uint64_t Address, 2004 const void *Decoder) { 2005 int Offset = SignExtend32<11>(Insn & 0x07ff); 2006 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2007 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2008 2009 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2010 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2011 2012 Inst.addOperand(MCOperand::createReg(Reg)); 2013 Inst.addOperand(MCOperand::createReg(Base)); 2014 Inst.addOperand(MCOperand::createImm(Offset)); 2015 2016 return MCDisassembler::Success; 2017 } 2018 2019 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2020 uint64_t Address, const void *Decoder) { 2021 int Offset = SignExtend32<11>(Insn & 0x07ff); 2022 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2023 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2024 2025 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2026 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2027 2028 Inst.addOperand(MCOperand::createReg(Reg)); 2029 Inst.addOperand(MCOperand::createReg(Base)); 2030 Inst.addOperand(MCOperand::createImm(Offset)); 2031 2032 return MCDisassembler::Success; 2033 } 2034 2035 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2036 unsigned Insn, 2037 uint64_t Address, 2038 const void *Decoder) { 2039 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2040 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2041 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2042 2043 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2044 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2045 2046 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2047 Inst.addOperand(MCOperand::createReg(Rt)); 2048 } 2049 2050 Inst.addOperand(MCOperand::createReg(Rt)); 2051 Inst.addOperand(MCOperand::createReg(Base)); 2052 Inst.addOperand(MCOperand::createImm(Offset)); 2053 2054 return MCDisassembler::Success; 2055 } 2056 2057 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2058 unsigned RegNo, 2059 uint64_t Address, 2060 const void *Decoder) { 2061 // Currently only hardware register 29 is supported. 2062 if (RegNo != 29) 2063 return MCDisassembler::Fail; 2064 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2065 return MCDisassembler::Success; 2066 } 2067 2068 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2069 unsigned RegNo, 2070 uint64_t Address, 2071 const void *Decoder) { 2072 if (RegNo > 30 || RegNo %2) 2073 return MCDisassembler::Fail; 2074 2075 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2076 Inst.addOperand(MCOperand::createReg(Reg)); 2077 return MCDisassembler::Success; 2078 } 2079 2080 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2081 unsigned RegNo, 2082 uint64_t Address, 2083 const void *Decoder) { 2084 if (RegNo >= 4) 2085 return MCDisassembler::Fail; 2086 2087 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2088 Inst.addOperand(MCOperand::createReg(Reg)); 2089 return MCDisassembler::Success; 2090 } 2091 2092 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2093 unsigned RegNo, 2094 uint64_t Address, 2095 const void *Decoder) { 2096 if (RegNo >= 4) 2097 return MCDisassembler::Fail; 2098 2099 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2100 Inst.addOperand(MCOperand::createReg(Reg)); 2101 return MCDisassembler::Success; 2102 } 2103 2104 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2105 unsigned RegNo, 2106 uint64_t Address, 2107 const void *Decoder) { 2108 if (RegNo >= 4) 2109 return MCDisassembler::Fail; 2110 2111 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2112 Inst.addOperand(MCOperand::createReg(Reg)); 2113 return MCDisassembler::Success; 2114 } 2115 2116 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2117 unsigned RegNo, 2118 uint64_t Address, 2119 const void *Decoder) { 2120 if (RegNo > 31) 2121 return MCDisassembler::Fail; 2122 2123 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2124 Inst.addOperand(MCOperand::createReg(Reg)); 2125 return MCDisassembler::Success; 2126 } 2127 2128 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2129 unsigned RegNo, 2130 uint64_t Address, 2131 const void *Decoder) { 2132 if (RegNo > 31) 2133 return MCDisassembler::Fail; 2134 2135 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2136 Inst.addOperand(MCOperand::createReg(Reg)); 2137 return MCDisassembler::Success; 2138 } 2139 2140 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2141 unsigned RegNo, 2142 uint64_t Address, 2143 const void *Decoder) { 2144 if (RegNo > 31) 2145 return MCDisassembler::Fail; 2146 2147 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2148 Inst.addOperand(MCOperand::createReg(Reg)); 2149 return MCDisassembler::Success; 2150 } 2151 2152 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2153 unsigned RegNo, 2154 uint64_t Address, 2155 const void *Decoder) { 2156 if (RegNo > 31) 2157 return MCDisassembler::Fail; 2158 2159 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2160 Inst.addOperand(MCOperand::createReg(Reg)); 2161 return MCDisassembler::Success; 2162 } 2163 2164 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2165 unsigned RegNo, 2166 uint64_t Address, 2167 const void *Decoder) { 2168 if (RegNo > 7) 2169 return MCDisassembler::Fail; 2170 2171 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2172 Inst.addOperand(MCOperand::createReg(Reg)); 2173 return MCDisassembler::Success; 2174 } 2175 2176 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2177 unsigned RegNo, 2178 uint64_t Address, 2179 const void *Decoder) { 2180 if (RegNo > 31) 2181 return MCDisassembler::Fail; 2182 2183 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2184 Inst.addOperand(MCOperand::createReg(Reg)); 2185 return MCDisassembler::Success; 2186 } 2187 2188 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2189 unsigned RegNo, 2190 uint64_t Address, 2191 const void *Decoder) { 2192 if (RegNo > 31) 2193 return MCDisassembler::Fail; 2194 2195 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2196 Inst.addOperand(MCOperand::createReg(Reg)); 2197 return MCDisassembler::Success; 2198 } 2199 2200 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2201 unsigned Offset, 2202 uint64_t Address, 2203 const void *Decoder) { 2204 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2205 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2206 return MCDisassembler::Success; 2207 } 2208 2209 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2210 unsigned Offset, 2211 uint64_t Address, 2212 const void *Decoder) { 2213 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2214 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2215 return MCDisassembler::Success; 2216 } 2217 2218 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2219 unsigned Insn, 2220 uint64_t Address, 2221 const void *Decoder) { 2222 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2223 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2224 return MCDisassembler::Success; 2225 } 2226 2227 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2228 unsigned Offset, 2229 uint64_t Address, 2230 const void *Decoder) { 2231 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2232 2233 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2234 return MCDisassembler::Success; 2235 } 2236 2237 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2238 unsigned Offset, 2239 uint64_t Address, 2240 const void *Decoder) { 2241 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2242 2243 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2244 return MCDisassembler::Success; 2245 } 2246 2247 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2248 unsigned Offset, 2249 uint64_t Address, 2250 const void *Decoder) { 2251 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2252 2253 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2254 return MCDisassembler::Success; 2255 } 2256 2257 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2258 unsigned Offset, 2259 uint64_t Address, 2260 const void *Decoder) { 2261 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2262 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2263 return MCDisassembler::Success; 2264 } 2265 2266 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2267 unsigned Offset, 2268 uint64_t Address, 2269 const void *Decoder) { 2270 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2271 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2272 return MCDisassembler::Success; 2273 } 2274 2275 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2276 unsigned Offset, 2277 uint64_t Address, 2278 const void *Decoder) { 2279 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2280 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2281 return MCDisassembler::Success; 2282 } 2283 2284 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2285 unsigned Offset, 2286 uint64_t Address, 2287 const void *Decoder) { 2288 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2289 2290 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2291 return MCDisassembler::Success; 2292 } 2293 2294 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2295 unsigned Insn, 2296 uint64_t Address, 2297 const void *Decoder) { 2298 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2299 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2300 return MCDisassembler::Success; 2301 } 2302 2303 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2304 unsigned Value, 2305 uint64_t Address, 2306 const void *Decoder) { 2307 if (Value == 0) 2308 Inst.addOperand(MCOperand::createImm(1)); 2309 else if (Value == 0x7) 2310 Inst.addOperand(MCOperand::createImm(-1)); 2311 else 2312 Inst.addOperand(MCOperand::createImm(Value << 2)); 2313 return MCDisassembler::Success; 2314 } 2315 2316 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2317 unsigned Value, 2318 uint64_t Address, 2319 const void *Decoder) { 2320 if (Value == 0x7F) 2321 Inst.addOperand(MCOperand::createImm(-1)); 2322 else 2323 Inst.addOperand(MCOperand::createImm(Value)); 2324 return MCDisassembler::Success; 2325 } 2326 2327 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2328 unsigned Value, 2329 uint64_t Address, 2330 const void *Decoder) { 2331 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2332 return MCDisassembler::Success; 2333 } 2334 2335 template <unsigned Bits, int Offset, int Scale> 2336 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2337 uint64_t Address, 2338 const void *Decoder) { 2339 Value &= ((1 << Bits) - 1); 2340 Value *= Scale; 2341 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2342 return MCDisassembler::Success; 2343 } 2344 2345 template <unsigned Bits, int Offset, int ScaleBy> 2346 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2347 uint64_t Address, 2348 const void *Decoder) { 2349 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2350 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2351 return MCDisassembler::Success; 2352 } 2353 2354 static DecodeStatus DecodeInsSize(MCInst &Inst, 2355 unsigned Insn, 2356 uint64_t Address, 2357 const void *Decoder) { 2358 // First we need to grab the pos(lsb) from MCInst. 2359 // This function only handles the 32 bit variants of ins, as dins 2360 // variants are handled differently. 2361 int Pos = Inst.getOperand(2).getImm(); 2362 int Size = (int) Insn - Pos + 1; 2363 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2364 return MCDisassembler::Success; 2365 } 2366 2367 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2368 uint64_t Address, const void *Decoder) { 2369 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2370 return MCDisassembler::Success; 2371 } 2372 2373 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2374 uint64_t Address, const void *Decoder) { 2375 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2376 return MCDisassembler::Success; 2377 } 2378 2379 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2380 uint64_t Address, const void *Decoder) { 2381 int32_t DecodedValue; 2382 switch (Insn) { 2383 case 0: DecodedValue = 256; break; 2384 case 1: DecodedValue = 257; break; 2385 case 510: DecodedValue = -258; break; 2386 case 511: DecodedValue = -257; break; 2387 default: DecodedValue = SignExtend32<9>(Insn); break; 2388 } 2389 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2390 return MCDisassembler::Success; 2391 } 2392 2393 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2394 uint64_t Address, const void *Decoder) { 2395 // Insn must be >= 0, since it is unsigned that condition is always true. 2396 assert(Insn < 16); 2397 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2398 255, 32768, 65535}; 2399 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2400 return MCDisassembler::Success; 2401 } 2402 2403 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2404 unsigned Insn, 2405 uint64_t Address, 2406 const void *Decoder) { 2407 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2408 Mips::S6, Mips::S7, Mips::FP}; 2409 unsigned RegNum; 2410 2411 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2412 2413 // Empty register lists are not allowed. 2414 if (RegLst == 0) 2415 return MCDisassembler::Fail; 2416 2417 RegNum = RegLst & 0xf; 2418 2419 // RegLst values 10-15, and 26-31 are reserved. 2420 if (RegNum > 9) 2421 return MCDisassembler::Fail; 2422 2423 for (unsigned i = 0; i < RegNum; i++) 2424 Inst.addOperand(MCOperand::createReg(Regs[i])); 2425 2426 if (RegLst & 0x10) 2427 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2428 2429 return MCDisassembler::Success; 2430 } 2431 2432 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2433 uint64_t Address, 2434 const void *Decoder) { 2435 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2436 unsigned RegLst; 2437 switch(Inst.getOpcode()) { 2438 default: 2439 RegLst = fieldFromInstruction(Insn, 4, 2); 2440 break; 2441 case Mips::LWM16_MMR6: 2442 case Mips::SWM16_MMR6: 2443 RegLst = fieldFromInstruction(Insn, 8, 2); 2444 break; 2445 } 2446 unsigned RegNum = RegLst & 0x3; 2447 2448 for (unsigned i = 0; i <= RegNum; i++) 2449 Inst.addOperand(MCOperand::createReg(Regs[i])); 2450 2451 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2452 2453 return MCDisassembler::Success; 2454 } 2455 2456 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2457 uint64_t Address, const void *Decoder) { 2458 switch (RegPair) { 2459 default: 2460 return MCDisassembler::Fail; 2461 case 0: 2462 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2463 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2464 break; 2465 case 1: 2466 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2467 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2468 break; 2469 case 2: 2470 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2471 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2472 break; 2473 case 3: 2474 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2475 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2476 break; 2477 case 4: 2478 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2479 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2480 break; 2481 case 5: 2482 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2483 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2484 break; 2485 case 6: 2486 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2487 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2488 break; 2489 case 7: 2490 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2491 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2492 break; 2493 } 2494 2495 return MCDisassembler::Success; 2496 } 2497 2498 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2499 uint64_t Address, const void *Decoder) { 2500 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2501 return MCDisassembler::Success; 2502 } 2503 2504 template <typename InsnType> 2505 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2506 uint64_t Address, 2507 const void *Decoder) { 2508 // We have: 2509 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2510 // Invalid if rt == 0 2511 // BGTZALC_MMR6 if rs == 0 && rt != 0 2512 // BLTZALC_MMR6 if rs != 0 && rs == rt 2513 // BLTUC_MMR6 if rs != 0 && rs != rt 2514 2515 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2516 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2517 InsnType Imm = 0; 2518 bool HasRs = false; 2519 bool HasRt = false; 2520 2521 if (Rt == 0) 2522 return MCDisassembler::Fail; 2523 else if (Rs == 0) { 2524 MI.setOpcode(Mips::BGTZALC_MMR6); 2525 HasRt = true; 2526 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2527 } 2528 else if (Rs == Rt) { 2529 MI.setOpcode(Mips::BLTZALC_MMR6); 2530 HasRs = true; 2531 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2532 } 2533 else { 2534 MI.setOpcode(Mips::BLTUC_MMR6); 2535 HasRs = true; 2536 HasRt = true; 2537 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2538 } 2539 2540 if (HasRs) 2541 MI.addOperand( 2542 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2543 2544 if (HasRt) 2545 MI.addOperand( 2546 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2547 2548 MI.addOperand(MCOperand::createImm(Imm)); 2549 2550 return MCDisassembler::Success; 2551 } 2552 2553 template <typename InsnType> 2554 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2555 uint64_t Address, 2556 const void *Decoder) { 2557 // We have: 2558 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2559 // Invalid if rt == 0 2560 // BLEZALC_MMR6 if rs == 0 && rt != 0 2561 // BGEZALC_MMR6 if rs == rt && rt != 0 2562 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2563 2564 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2565 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2566 InsnType Imm = 0; 2567 bool HasRs = false; 2568 2569 if (Rt == 0) 2570 return MCDisassembler::Fail; 2571 else if (Rs == 0) { 2572 MI.setOpcode(Mips::BLEZALC_MMR6); 2573 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2574 } 2575 else if (Rs == Rt) { 2576 MI.setOpcode(Mips::BGEZALC_MMR6); 2577 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2578 } 2579 else { 2580 HasRs = true; 2581 MI.setOpcode(Mips::BGEUC_MMR6); 2582 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2583 } 2584 2585 if (HasRs) 2586 MI.addOperand( 2587 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2588 MI.addOperand( 2589 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2590 2591 MI.addOperand(MCOperand::createImm(Imm)); 2592 2593 return MCDisassembler::Success; 2594 } 2595