1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 48 49 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 50 51 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 52 53 bool hasCOP3() const { 54 // Only present in MIPS-I and MIPS-II 55 return !hasMips32() && !hasMips3(); 56 } 57 58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 59 ArrayRef<uint8_t> Bytes, uint64_t Address, 60 raw_ostream &VStream, 61 raw_ostream &CStream) const override; 62 }; 63 64 } // end anonymous namespace 65 66 // Forward declare these because the autogenerated code will reference them. 67 // Definitions are further down. 68 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 69 unsigned RegNo, 70 uint64_t Address, 71 const void *Decoder); 72 73 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 74 unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 78 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 79 unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 83 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 99 unsigned Insn, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 114 unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 133 unsigned Insn, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 193 unsigned Offset, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 198 unsigned Insn, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 203 unsigned Offset, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 213 // shifted left by 1 bit. 214 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 215 unsigned Offset, 216 uint64_t Address, 217 const void *Decoder); 218 219 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 220 // shifted left by 1 bit. 221 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 222 unsigned Offset, 223 uint64_t Address, 224 const void *Decoder); 225 226 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 227 // shifted left by 1 bit. 228 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 229 unsigned Offset, 230 uint64_t Address, 231 const void *Decoder); 232 233 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 234 // shifted left by 1 bit. 235 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 236 unsigned Offset, 237 uint64_t Address, 238 const void *Decoder); 239 240 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 241 // shifted left by 1 bit. 242 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 243 unsigned Insn, 244 uint64_t Address, 245 const void *Decoder); 246 247 static DecodeStatus DecodeMem(MCInst &Inst, 248 unsigned Insn, 249 uint64_t Address, 250 const void *Decoder); 251 252 static DecodeStatus DecodeMemEVA(MCInst &Inst, 253 unsigned Insn, 254 uint64_t Address, 255 const void *Decoder); 256 257 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 262 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 263 unsigned Insn, 264 uint64_t Address, 265 const void *Decoder); 266 267 static DecodeStatus DecodeCacheOp(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeSyncI(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeSynciR6(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 305 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 321 unsigned Insn, 322 uint64_t Address, 323 const void *Decoder); 324 325 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 326 unsigned Insn, 327 uint64_t Address, 328 const void *Decoder); 329 330 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 331 unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 336 unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 341 uint64_t Address, 342 const void *Decoder); 343 344 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 349 uint64_t Address, 350 const void *Decoder); 351 352 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 357 unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 362 unsigned Value, 363 uint64_t Address, 364 const void *Decoder); 365 366 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 367 unsigned Value, 368 uint64_t Address, 369 const void *Decoder); 370 371 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 372 unsigned Value, 373 uint64_t Address, 374 const void *Decoder); 375 376 template <unsigned Bits, int Offset, int Scale> 377 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 378 uint64_t Address, 379 const void *Decoder); 380 381 template <unsigned Bits, int Offset> 382 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 383 uint64_t Address, 384 const void *Decoder) { 385 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 386 Decoder); 387 } 388 389 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 390 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 391 uint64_t Address, 392 const void *Decoder); 393 394 static DecodeStatus DecodeInsSize(MCInst &Inst, 395 unsigned Insn, 396 uint64_t Address, 397 const void *Decoder); 398 399 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 400 uint64_t Address, const void *Decoder); 401 402 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 403 uint64_t Address, const void *Decoder); 404 405 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 406 uint64_t Address, const void *Decoder); 407 408 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 409 uint64_t Address, const void *Decoder); 410 411 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 412 uint64_t Address, const void *Decoder); 413 414 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 415 /// handle. 416 template <typename InsnType> 417 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 418 const void *Decoder); 419 420 template <typename InsnType> 421 static DecodeStatus 422 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 423 const void *Decoder); 424 425 template <typename InsnType> 426 static DecodeStatus 427 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 428 const void *Decoder); 429 430 template <typename InsnType> 431 static DecodeStatus 432 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 433 const void *Decoder); 434 435 template <typename InsnType> 436 static DecodeStatus 437 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 438 const void *Decoder); 439 440 template <typename InsnType> 441 static DecodeStatus 442 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus 447 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 451 uint64_t Address, 452 const void *Decoder); 453 454 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 455 uint64_t Address, 456 const void *Decoder); 457 458 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 459 uint64_t Address, 460 const void *Decoder); 461 462 namespace llvm { 463 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 464 TheMips64elTarget; 465 } 466 467 static MCDisassembler *createMipsDisassembler( 468 const Target &T, 469 const MCSubtargetInfo &STI, 470 MCContext &Ctx) { 471 return new MipsDisassembler(STI, Ctx, true); 472 } 473 474 static MCDisassembler *createMipselDisassembler( 475 const Target &T, 476 const MCSubtargetInfo &STI, 477 MCContext &Ctx) { 478 return new MipsDisassembler(STI, Ctx, false); 479 } 480 481 extern "C" void LLVMInitializeMipsDisassembler() { 482 // Register the disassembler. 483 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 484 createMipsDisassembler); 485 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 486 createMipselDisassembler); 487 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 488 createMipsDisassembler); 489 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 490 createMipselDisassembler); 491 } 492 493 #include "MipsGenDisassemblerTables.inc" 494 495 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 496 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 497 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 498 return *(RegInfo->getRegClass(RC).begin() + RegNo); 499 } 500 501 template <typename InsnType> 502 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 503 const void *Decoder) { 504 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 505 // The size of the n field depends on the element size 506 // The register class also depends on this. 507 InsnType tmp = fieldFromInstruction(insn, 17, 5); 508 unsigned NSize = 0; 509 DecodeFN RegDecoder = nullptr; 510 if ((tmp & 0x18) == 0x00) { // INSVE_B 511 NSize = 4; 512 RegDecoder = DecodeMSA128BRegisterClass; 513 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 514 NSize = 3; 515 RegDecoder = DecodeMSA128HRegisterClass; 516 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 517 NSize = 2; 518 RegDecoder = DecodeMSA128WRegisterClass; 519 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 520 NSize = 1; 521 RegDecoder = DecodeMSA128DRegisterClass; 522 } else 523 llvm_unreachable("Invalid encoding"); 524 525 assert(NSize != 0 && RegDecoder != nullptr); 526 527 // $wd 528 tmp = fieldFromInstruction(insn, 6, 5); 529 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 530 return MCDisassembler::Fail; 531 // $wd_in 532 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 533 return MCDisassembler::Fail; 534 // $n 535 tmp = fieldFromInstruction(insn, 16, NSize); 536 MI.addOperand(MCOperand::createImm(tmp)); 537 // $ws 538 tmp = fieldFromInstruction(insn, 11, 5); 539 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 540 return MCDisassembler::Fail; 541 // $n2 542 MI.addOperand(MCOperand::createImm(0)); 543 544 return MCDisassembler::Success; 545 } 546 547 template <typename InsnType> 548 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 549 uint64_t Address, 550 const void *Decoder) { 551 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 552 // (otherwise we would have matched the ADDI instruction from the earlier 553 // ISA's instead). 554 // 555 // We have: 556 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 557 // BOVC if rs >= rt 558 // BEQZALC if rs == 0 && rt != 0 559 // BEQC if rs < rt && rs != 0 560 561 InsnType Rs = fieldFromInstruction(insn, 21, 5); 562 InsnType Rt = fieldFromInstruction(insn, 16, 5); 563 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 564 bool HasRs = false; 565 566 if (Rs >= Rt) { 567 MI.setOpcode(Mips::BOVC); 568 HasRs = true; 569 } else if (Rs != 0 && Rs < Rt) { 570 MI.setOpcode(Mips::BEQC); 571 HasRs = true; 572 } else 573 MI.setOpcode(Mips::BEQZALC); 574 575 if (HasRs) 576 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 577 Rs))); 578 579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 580 Rt))); 581 MI.addOperand(MCOperand::createImm(Imm)); 582 583 return MCDisassembler::Success; 584 } 585 586 template <typename InsnType> 587 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 588 uint64_t Address, 589 const void *Decoder) { 590 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 591 // (otherwise we would have matched the ADDI instruction from the earlier 592 // ISA's instead). 593 // 594 // We have: 595 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 596 // BNVC if rs >= rt 597 // BNEZALC if rs == 0 && rt != 0 598 // BNEC if rs < rt && rs != 0 599 600 InsnType Rs = fieldFromInstruction(insn, 21, 5); 601 InsnType Rt = fieldFromInstruction(insn, 16, 5); 602 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 603 bool HasRs = false; 604 605 if (Rs >= Rt) { 606 MI.setOpcode(Mips::BNVC); 607 HasRs = true; 608 } else if (Rs != 0 && Rs < Rt) { 609 MI.setOpcode(Mips::BNEC); 610 HasRs = true; 611 } else 612 MI.setOpcode(Mips::BNEZALC); 613 614 if (HasRs) 615 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 616 Rs))); 617 618 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 619 Rt))); 620 MI.addOperand(MCOperand::createImm(Imm)); 621 622 return MCDisassembler::Success; 623 } 624 625 template <typename InsnType> 626 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 627 uint64_t Address, 628 const void *Decoder) { 629 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 630 // (otherwise we would have matched the BLEZL instruction from the earlier 631 // ISA's instead). 632 // 633 // We have: 634 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 635 // Invalid if rs == 0 636 // BLEZC if rs == 0 && rt != 0 637 // BGEZC if rs == rt && rt != 0 638 // BGEC if rs != rt && rs != 0 && rt != 0 639 640 InsnType Rs = fieldFromInstruction(insn, 21, 5); 641 InsnType Rt = fieldFromInstruction(insn, 16, 5); 642 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 643 bool HasRs = false; 644 645 if (Rt == 0) 646 return MCDisassembler::Fail; 647 else if (Rs == 0) 648 MI.setOpcode(Mips::BLEZC); 649 else if (Rs == Rt) 650 MI.setOpcode(Mips::BGEZC); 651 else { 652 HasRs = true; 653 MI.setOpcode(Mips::BGEC); 654 } 655 656 if (HasRs) 657 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 658 Rs))); 659 660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 661 Rt))); 662 663 MI.addOperand(MCOperand::createImm(Imm)); 664 665 return MCDisassembler::Success; 666 } 667 668 template <typename InsnType> 669 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 670 uint64_t Address, 671 const void *Decoder) { 672 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 673 // (otherwise we would have matched the BGTZL instruction from the earlier 674 // ISA's instead). 675 // 676 // We have: 677 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 678 // Invalid if rs == 0 679 // BGTZC if rs == 0 && rt != 0 680 // BLTZC if rs == rt && rt != 0 681 // BLTC if rs != rt && rs != 0 && rt != 0 682 683 bool HasRs = false; 684 685 InsnType Rs = fieldFromInstruction(insn, 21, 5); 686 InsnType Rt = fieldFromInstruction(insn, 16, 5); 687 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 688 689 if (Rt == 0) 690 return MCDisassembler::Fail; 691 else if (Rs == 0) 692 MI.setOpcode(Mips::BGTZC); 693 else if (Rs == Rt) 694 MI.setOpcode(Mips::BLTZC); 695 else { 696 MI.setOpcode(Mips::BLTC); 697 HasRs = true; 698 } 699 700 if (HasRs) 701 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 702 Rs))); 703 704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 705 Rt))); 706 707 MI.addOperand(MCOperand::createImm(Imm)); 708 709 return MCDisassembler::Success; 710 } 711 712 template <typename InsnType> 713 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 714 uint64_t Address, 715 const void *Decoder) { 716 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 717 // (otherwise we would have matched the BGTZ instruction from the earlier 718 // ISA's instead). 719 // 720 // We have: 721 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 722 // BGTZ if rt == 0 723 // BGTZALC if rs == 0 && rt != 0 724 // BLTZALC if rs != 0 && rs == rt 725 // BLTUC if rs != 0 && rs != rt 726 727 InsnType Rs = fieldFromInstruction(insn, 21, 5); 728 InsnType Rt = fieldFromInstruction(insn, 16, 5); 729 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 730 bool HasRs = false; 731 bool HasRt = false; 732 733 if (Rt == 0) { 734 MI.setOpcode(Mips::BGTZ); 735 HasRs = true; 736 } else if (Rs == 0) { 737 MI.setOpcode(Mips::BGTZALC); 738 HasRt = true; 739 } else if (Rs == Rt) { 740 MI.setOpcode(Mips::BLTZALC); 741 HasRs = true; 742 } else { 743 MI.setOpcode(Mips::BLTUC); 744 HasRs = true; 745 HasRt = true; 746 } 747 748 if (HasRs) 749 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 750 Rs))); 751 752 if (HasRt) 753 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 754 Rt))); 755 756 MI.addOperand(MCOperand::createImm(Imm)); 757 758 return MCDisassembler::Success; 759 } 760 761 template <typename InsnType> 762 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 763 uint64_t Address, 764 const void *Decoder) { 765 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 766 // (otherwise we would have matched the BLEZL instruction from the earlier 767 // ISA's instead). 768 // 769 // We have: 770 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 771 // Invalid if rs == 0 772 // BLEZALC if rs == 0 && rt != 0 773 // BGEZALC if rs == rt && rt != 0 774 // BGEUC if rs != rt && rs != 0 && rt != 0 775 776 InsnType Rs = fieldFromInstruction(insn, 21, 5); 777 InsnType Rt = fieldFromInstruction(insn, 16, 5); 778 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 779 bool HasRs = false; 780 781 if (Rt == 0) 782 return MCDisassembler::Fail; 783 else if (Rs == 0) 784 MI.setOpcode(Mips::BLEZALC); 785 else if (Rs == Rt) 786 MI.setOpcode(Mips::BGEZALC); 787 else { 788 HasRs = true; 789 MI.setOpcode(Mips::BGEUC); 790 } 791 792 if (HasRs) 793 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 794 Rs))); 795 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 796 Rt))); 797 798 MI.addOperand(MCOperand::createImm(Imm)); 799 800 return MCDisassembler::Success; 801 } 802 803 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 804 /// according to the given endianess. 805 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 806 uint64_t &Size, uint32_t &Insn, 807 bool IsBigEndian) { 808 // We want to read exactly 2 Bytes of data. 809 if (Bytes.size() < 2) { 810 Size = 0; 811 return MCDisassembler::Fail; 812 } 813 814 if (IsBigEndian) { 815 Insn = (Bytes[0] << 8) | Bytes[1]; 816 } else { 817 Insn = (Bytes[1] << 8) | Bytes[0]; 818 } 819 820 return MCDisassembler::Success; 821 } 822 823 /// Read four bytes from the ArrayRef and return 32 bit word sorted 824 /// according to the given endianess 825 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 826 uint64_t &Size, uint32_t &Insn, 827 bool IsBigEndian, bool IsMicroMips) { 828 // We want to read exactly 4 Bytes of data. 829 if (Bytes.size() < 4) { 830 Size = 0; 831 return MCDisassembler::Fail; 832 } 833 834 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 835 // always precede the low 16 bits in the instruction stream (that is, they 836 // are placed at lower addresses in the instruction stream). 837 // 838 // microMIPS byte ordering: 839 // Big-endian: 0 | 1 | 2 | 3 840 // Little-endian: 1 | 0 | 3 | 2 841 842 if (IsBigEndian) { 843 // Encoded as a big-endian 32-bit word in the stream. 844 Insn = 845 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 846 } else { 847 if (IsMicroMips) { 848 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 849 (Bytes[1] << 24); 850 } else { 851 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 852 (Bytes[3] << 24); 853 } 854 } 855 856 return MCDisassembler::Success; 857 } 858 859 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 860 ArrayRef<uint8_t> Bytes, 861 uint64_t Address, 862 raw_ostream &VStream, 863 raw_ostream &CStream) const { 864 uint32_t Insn; 865 DecodeStatus Result; 866 867 if (IsMicroMips) { 868 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 869 if (Result == MCDisassembler::Fail) 870 return MCDisassembler::Fail; 871 872 if (hasMips32r6()) { 873 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 874 // Calling the auto-generated decoder function for microMIPS32R6 875 // (and microMIPS64R6) 16-bit instructions. 876 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 877 Address, this, STI); 878 if (Result != MCDisassembler::Fail) { 879 Size = 2; 880 return Result; 881 } 882 } 883 884 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 885 // Calling the auto-generated decoder function for microMIPS 16-bit 886 // instructions. 887 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 888 this, STI); 889 if (Result != MCDisassembler::Fail) { 890 Size = 2; 891 return Result; 892 } 893 894 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 895 if (Result == MCDisassembler::Fail) 896 return MCDisassembler::Fail; 897 898 if (hasMips32r6()) { 899 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 900 // Calling the auto-generated decoder function. 901 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 902 this, STI); 903 if (Result != MCDisassembler::Fail) { 904 Size = 4; 905 return Result; 906 } 907 } 908 909 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 910 // Calling the auto-generated decoder function. 911 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 912 this, STI); 913 if (Result != MCDisassembler::Fail) { 914 Size = 4; 915 return Result; 916 } 917 918 if (hasMips32r6() && isFP64()) { 919 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 920 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 921 Address, this, STI); 922 if (Result != MCDisassembler::Fail) { 923 Size = 4; 924 return Result; 925 } 926 } 927 928 // This is an invalid instruction. Let the disassembler move forward by the 929 // minimum instruction size. 930 Size = 2; 931 return MCDisassembler::Fail; 932 } 933 934 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 935 if (Result == MCDisassembler::Fail) { 936 Size = 4; 937 return MCDisassembler::Fail; 938 } 939 940 if (hasCOP3()) { 941 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 942 Result = 943 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 944 if (Result != MCDisassembler::Fail) { 945 Size = 4; 946 return Result; 947 } 948 } 949 950 if (hasMips32r6() && isGP64()) { 951 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 952 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 953 Address, this, STI); 954 if (Result != MCDisassembler::Fail) { 955 Size = 4; 956 return Result; 957 } 958 } 959 960 if (hasMips32r6()) { 961 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 962 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 963 Address, this, STI); 964 if (Result != MCDisassembler::Fail) { 965 Size = 4; 966 return Result; 967 } 968 } 969 970 if (hasCnMips()) { 971 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 972 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 973 Address, this, STI); 974 if (Result != MCDisassembler::Fail) { 975 Size = 4; 976 return Result; 977 } 978 } 979 980 if (isGP64()) { 981 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 982 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 983 Address, this, STI); 984 if (Result != MCDisassembler::Fail) { 985 Size = 4; 986 return Result; 987 } 988 } 989 990 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 991 // Calling the auto-generated decoder function. 992 Result = 993 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 994 if (Result != MCDisassembler::Fail) { 995 Size = 4; 996 return Result; 997 } 998 999 Size = 4; 1000 return MCDisassembler::Fail; 1001 } 1002 1003 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1004 unsigned RegNo, 1005 uint64_t Address, 1006 const void *Decoder) { 1007 1008 return MCDisassembler::Fail; 1009 1010 } 1011 1012 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1013 unsigned RegNo, 1014 uint64_t Address, 1015 const void *Decoder) { 1016 1017 if (RegNo > 31) 1018 return MCDisassembler::Fail; 1019 1020 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1021 Inst.addOperand(MCOperand::createReg(Reg)); 1022 return MCDisassembler::Success; 1023 } 1024 1025 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1026 unsigned RegNo, 1027 uint64_t Address, 1028 const void *Decoder) { 1029 if (RegNo > 7) 1030 return MCDisassembler::Fail; 1031 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1032 Inst.addOperand(MCOperand::createReg(Reg)); 1033 return MCDisassembler::Success; 1034 } 1035 1036 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1037 unsigned RegNo, 1038 uint64_t Address, 1039 const void *Decoder) { 1040 if (RegNo > 7) 1041 return MCDisassembler::Fail; 1042 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1043 Inst.addOperand(MCOperand::createReg(Reg)); 1044 return MCDisassembler::Success; 1045 } 1046 1047 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1048 unsigned RegNo, 1049 uint64_t Address, 1050 const void *Decoder) { 1051 if (RegNo > 7) 1052 return MCDisassembler::Fail; 1053 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1054 Inst.addOperand(MCOperand::createReg(Reg)); 1055 return MCDisassembler::Success; 1056 } 1057 1058 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1059 unsigned RegNo, 1060 uint64_t Address, 1061 const void *Decoder) { 1062 if (RegNo > 31) 1063 return MCDisassembler::Fail; 1064 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1065 Inst.addOperand(MCOperand::createReg(Reg)); 1066 return MCDisassembler::Success; 1067 } 1068 1069 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1070 unsigned RegNo, 1071 uint64_t Address, 1072 const void *Decoder) { 1073 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1074 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1075 1076 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1077 } 1078 1079 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1080 unsigned RegNo, 1081 uint64_t Address, 1082 const void *Decoder) { 1083 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1084 } 1085 1086 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1087 unsigned RegNo, 1088 uint64_t Address, 1089 const void *Decoder) { 1090 if (RegNo > 31) 1091 return MCDisassembler::Fail; 1092 1093 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1094 Inst.addOperand(MCOperand::createReg(Reg)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1099 unsigned RegNo, 1100 uint64_t Address, 1101 const void *Decoder) { 1102 if (RegNo > 31) 1103 return MCDisassembler::Fail; 1104 1105 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1106 Inst.addOperand(MCOperand::createReg(Reg)); 1107 return MCDisassembler::Success; 1108 } 1109 1110 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1111 unsigned RegNo, 1112 uint64_t Address, 1113 const void *Decoder) { 1114 if (RegNo > 31) 1115 return MCDisassembler::Fail; 1116 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1117 Inst.addOperand(MCOperand::createReg(Reg)); 1118 return MCDisassembler::Success; 1119 } 1120 1121 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1122 unsigned RegNo, 1123 uint64_t Address, 1124 const void *Decoder) { 1125 if (RegNo > 7) 1126 return MCDisassembler::Fail; 1127 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1128 Inst.addOperand(MCOperand::createReg(Reg)); 1129 return MCDisassembler::Success; 1130 } 1131 1132 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1133 uint64_t Address, 1134 const void *Decoder) { 1135 if (RegNo > 31) 1136 return MCDisassembler::Fail; 1137 1138 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1139 Inst.addOperand(MCOperand::createReg(Reg)); 1140 return MCDisassembler::Success; 1141 } 1142 1143 static DecodeStatus DecodeMem(MCInst &Inst, 1144 unsigned Insn, 1145 uint64_t Address, 1146 const void *Decoder) { 1147 int Offset = SignExtend32<16>(Insn & 0xffff); 1148 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1149 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1150 1151 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1152 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1153 1154 if (Inst.getOpcode() == Mips::SC || 1155 Inst.getOpcode() == Mips::SCD) 1156 Inst.addOperand(MCOperand::createReg(Reg)); 1157 1158 Inst.addOperand(MCOperand::createReg(Reg)); 1159 Inst.addOperand(MCOperand::createReg(Base)); 1160 Inst.addOperand(MCOperand::createImm(Offset)); 1161 1162 return MCDisassembler::Success; 1163 } 1164 1165 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1166 unsigned Insn, 1167 uint64_t Address, 1168 const void *Decoder) { 1169 int Offset = SignExtend32<9>(Insn >> 7); 1170 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1171 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1172 1173 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1174 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1175 1176 if (Inst.getOpcode() == Mips::SCE) 1177 Inst.addOperand(MCOperand::createReg(Reg)); 1178 1179 Inst.addOperand(MCOperand::createReg(Reg)); 1180 Inst.addOperand(MCOperand::createReg(Base)); 1181 Inst.addOperand(MCOperand::createImm(Offset)); 1182 1183 return MCDisassembler::Success; 1184 } 1185 1186 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1187 unsigned Insn, 1188 uint64_t Address, 1189 const void *Decoder) { 1190 int Offset = SignExtend32<9>(Insn & 0x1ff); 1191 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1192 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1193 1194 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1195 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1196 1197 Inst.addOperand(MCOperand::createReg(Reg)); 1198 Inst.addOperand(MCOperand::createReg(Base)); 1199 Inst.addOperand(MCOperand::createImm(Offset)); 1200 1201 return MCDisassembler::Success; 1202 } 1203 1204 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1205 unsigned Insn, 1206 uint64_t Address, 1207 const void *Decoder) { 1208 int Offset = SignExtend32<16>(Insn & 0xffff); 1209 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1210 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1211 1212 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1213 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1214 1215 Inst.addOperand(MCOperand::createReg(Reg)); 1216 Inst.addOperand(MCOperand::createReg(Base)); 1217 Inst.addOperand(MCOperand::createImm(Offset)); 1218 1219 return MCDisassembler::Success; 1220 } 1221 1222 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1223 unsigned Insn, 1224 uint64_t Address, 1225 const void *Decoder) { 1226 int Offset = SignExtend32<16>(Insn & 0xffff); 1227 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1228 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1229 1230 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1231 1232 Inst.addOperand(MCOperand::createReg(Base)); 1233 Inst.addOperand(MCOperand::createImm(Offset)); 1234 Inst.addOperand(MCOperand::createImm(Hint)); 1235 1236 return MCDisassembler::Success; 1237 } 1238 1239 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1240 unsigned Insn, 1241 uint64_t Address, 1242 const void *Decoder) { 1243 int Offset = SignExtend32<12>(Insn & 0xfff); 1244 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1245 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1246 1247 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1248 1249 Inst.addOperand(MCOperand::createReg(Base)); 1250 Inst.addOperand(MCOperand::createImm(Offset)); 1251 Inst.addOperand(MCOperand::createImm(Hint)); 1252 1253 return MCDisassembler::Success; 1254 } 1255 1256 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1257 unsigned Insn, 1258 uint64_t Address, 1259 const void *Decoder) { 1260 int Offset = SignExtend32<9>(Insn & 0x1ff); 1261 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1262 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1263 1264 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1265 1266 Inst.addOperand(MCOperand::createReg(Base)); 1267 Inst.addOperand(MCOperand::createImm(Offset)); 1268 Inst.addOperand(MCOperand::createImm(Hint)); 1269 1270 return MCDisassembler::Success; 1271 } 1272 1273 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1274 unsigned Insn, 1275 uint64_t Address, 1276 const void *Decoder) { 1277 int Offset = SignExtend32<9>(Insn >> 7); 1278 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1279 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1280 1281 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1282 1283 Inst.addOperand(MCOperand::createReg(Base)); 1284 Inst.addOperand(MCOperand::createImm(Offset)); 1285 Inst.addOperand(MCOperand::createImm(Hint)); 1286 1287 return MCDisassembler::Success; 1288 } 1289 1290 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1291 unsigned Insn, 1292 uint64_t Address, 1293 const void *Decoder) { 1294 int Offset = SignExtend32<9>(Insn & 0x1ff); 1295 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1296 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1297 1298 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1299 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1300 1301 Inst.addOperand(MCOperand::createReg(Reg)); 1302 Inst.addOperand(MCOperand::createReg(Base)); 1303 Inst.addOperand(MCOperand::createImm(Offset)); 1304 1305 return MCDisassembler::Success; 1306 } 1307 1308 static DecodeStatus DecodeSyncI(MCInst &Inst, 1309 unsigned Insn, 1310 uint64_t Address, 1311 const void *Decoder) { 1312 int Offset = SignExtend32<16>(Insn & 0xffff); 1313 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1314 1315 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1316 1317 Inst.addOperand(MCOperand::createReg(Base)); 1318 Inst.addOperand(MCOperand::createImm(Offset)); 1319 1320 return MCDisassembler::Success; 1321 } 1322 1323 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1324 unsigned Insn, 1325 uint64_t Address, 1326 const void *Decoder) { 1327 int Immediate = SignExtend32<16>(Insn & 0xffff); 1328 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1329 1330 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1331 1332 Inst.addOperand(MCOperand::createReg(Base)); 1333 Inst.addOperand(MCOperand::createImm(Immediate)); 1334 1335 return MCDisassembler::Success; 1336 } 1337 1338 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1339 uint64_t Address, const void *Decoder) { 1340 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1341 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1342 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1343 1344 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1345 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1346 1347 Inst.addOperand(MCOperand::createReg(Reg)); 1348 Inst.addOperand(MCOperand::createReg(Base)); 1349 1350 // The immediate field of an LD/ST instruction is scaled which means it must 1351 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1352 // data format. 1353 // .b - 1 byte 1354 // .h - 2 bytes 1355 // .w - 4 bytes 1356 // .d - 8 bytes 1357 switch(Inst.getOpcode()) 1358 { 1359 default: 1360 assert (0 && "Unexpected instruction"); 1361 return MCDisassembler::Fail; 1362 break; 1363 case Mips::LD_B: 1364 case Mips::ST_B: 1365 Inst.addOperand(MCOperand::createImm(Offset)); 1366 break; 1367 case Mips::LD_H: 1368 case Mips::ST_H: 1369 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1370 break; 1371 case Mips::LD_W: 1372 case Mips::ST_W: 1373 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1374 break; 1375 case Mips::LD_D: 1376 case Mips::ST_D: 1377 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1378 break; 1379 } 1380 1381 return MCDisassembler::Success; 1382 } 1383 1384 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1385 unsigned Insn, 1386 uint64_t Address, 1387 const void *Decoder) { 1388 unsigned Offset = Insn & 0xf; 1389 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1390 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1391 1392 switch (Inst.getOpcode()) { 1393 case Mips::LBU16_MM: 1394 case Mips::LHU16_MM: 1395 case Mips::LW16_MM: 1396 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1397 == MCDisassembler::Fail) 1398 return MCDisassembler::Fail; 1399 break; 1400 case Mips::SB16_MM: 1401 case Mips::SB16_MMR6: 1402 case Mips::SH16_MM: 1403 case Mips::SH16_MMR6: 1404 case Mips::SW16_MM: 1405 case Mips::SW16_MMR6: 1406 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1407 == MCDisassembler::Fail) 1408 return MCDisassembler::Fail; 1409 break; 1410 } 1411 1412 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1413 == MCDisassembler::Fail) 1414 return MCDisassembler::Fail; 1415 1416 switch (Inst.getOpcode()) { 1417 case Mips::LBU16_MM: 1418 if (Offset == 0xf) 1419 Inst.addOperand(MCOperand::createImm(-1)); 1420 else 1421 Inst.addOperand(MCOperand::createImm(Offset)); 1422 break; 1423 case Mips::SB16_MM: 1424 case Mips::SB16_MMR6: 1425 Inst.addOperand(MCOperand::createImm(Offset)); 1426 break; 1427 case Mips::LHU16_MM: 1428 case Mips::SH16_MM: 1429 case Mips::SH16_MMR6: 1430 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1431 break; 1432 case Mips::LW16_MM: 1433 case Mips::SW16_MM: 1434 case Mips::SW16_MMR6: 1435 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1436 break; 1437 } 1438 1439 return MCDisassembler::Success; 1440 } 1441 1442 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1443 unsigned Insn, 1444 uint64_t Address, 1445 const void *Decoder) { 1446 unsigned Offset = Insn & 0x1F; 1447 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1448 1449 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1450 1451 Inst.addOperand(MCOperand::createReg(Reg)); 1452 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1453 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1454 1455 return MCDisassembler::Success; 1456 } 1457 1458 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1459 unsigned Insn, 1460 uint64_t Address, 1461 const void *Decoder) { 1462 unsigned Offset = Insn & 0x7F; 1463 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1464 1465 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1466 1467 Inst.addOperand(MCOperand::createReg(Reg)); 1468 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1469 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1470 1471 return MCDisassembler::Success; 1472 } 1473 1474 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1475 unsigned Insn, 1476 uint64_t Address, 1477 const void *Decoder) { 1478 int Offset; 1479 switch (Inst.getOpcode()) { 1480 case Mips::LWM16_MMR6: 1481 case Mips::SWM16_MMR6: 1482 Offset = fieldFromInstruction(Insn, 4, 4); 1483 break; 1484 default: 1485 Offset = SignExtend32<4>(Insn & 0xf); 1486 break; 1487 } 1488 1489 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1490 == MCDisassembler::Fail) 1491 return MCDisassembler::Fail; 1492 1493 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1494 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1495 1496 return MCDisassembler::Success; 1497 } 1498 1499 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1500 unsigned Insn, 1501 uint64_t Address, 1502 const void *Decoder) { 1503 int Offset = SignExtend32<9>(Insn & 0x1ff); 1504 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1505 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1506 1507 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1508 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1509 1510 if (Inst.getOpcode() == Mips::SCE_MM) 1511 Inst.addOperand(MCOperand::createReg(Reg)); 1512 1513 Inst.addOperand(MCOperand::createReg(Reg)); 1514 Inst.addOperand(MCOperand::createReg(Base)); 1515 Inst.addOperand(MCOperand::createImm(Offset)); 1516 1517 return MCDisassembler::Success; 1518 } 1519 1520 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1521 unsigned Insn, 1522 uint64_t Address, 1523 const void *Decoder) { 1524 int Offset = SignExtend32<12>(Insn & 0x0fff); 1525 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1526 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1527 1528 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1529 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1530 1531 switch (Inst.getOpcode()) { 1532 case Mips::SWM32_MM: 1533 case Mips::LWM32_MM: 1534 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1535 == MCDisassembler::Fail) 1536 return MCDisassembler::Fail; 1537 Inst.addOperand(MCOperand::createReg(Base)); 1538 Inst.addOperand(MCOperand::createImm(Offset)); 1539 break; 1540 case Mips::SC_MM: 1541 Inst.addOperand(MCOperand::createReg(Reg)); 1542 // fallthrough 1543 default: 1544 Inst.addOperand(MCOperand::createReg(Reg)); 1545 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1546 Inst.addOperand(MCOperand::createReg(Reg+1)); 1547 1548 Inst.addOperand(MCOperand::createReg(Base)); 1549 Inst.addOperand(MCOperand::createImm(Offset)); 1550 } 1551 1552 return MCDisassembler::Success; 1553 } 1554 1555 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1556 unsigned Insn, 1557 uint64_t Address, 1558 const void *Decoder) { 1559 int Offset = SignExtend32<16>(Insn & 0xffff); 1560 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1561 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1562 1563 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1564 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1565 1566 Inst.addOperand(MCOperand::createReg(Reg)); 1567 Inst.addOperand(MCOperand::createReg(Base)); 1568 Inst.addOperand(MCOperand::createImm(Offset)); 1569 1570 return MCDisassembler::Success; 1571 } 1572 1573 static DecodeStatus DecodeFMem(MCInst &Inst, 1574 unsigned Insn, 1575 uint64_t Address, 1576 const void *Decoder) { 1577 int Offset = SignExtend32<16>(Insn & 0xffff); 1578 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1579 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1580 1581 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1582 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1583 1584 Inst.addOperand(MCOperand::createReg(Reg)); 1585 Inst.addOperand(MCOperand::createReg(Base)); 1586 Inst.addOperand(MCOperand::createImm(Offset)); 1587 1588 return MCDisassembler::Success; 1589 } 1590 1591 static DecodeStatus DecodeFMem2(MCInst &Inst, 1592 unsigned Insn, 1593 uint64_t Address, 1594 const void *Decoder) { 1595 int Offset = SignExtend32<16>(Insn & 0xffff); 1596 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1597 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1598 1599 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1600 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1601 1602 Inst.addOperand(MCOperand::createReg(Reg)); 1603 Inst.addOperand(MCOperand::createReg(Base)); 1604 Inst.addOperand(MCOperand::createImm(Offset)); 1605 1606 return MCDisassembler::Success; 1607 } 1608 1609 static DecodeStatus DecodeFMem3(MCInst &Inst, 1610 unsigned Insn, 1611 uint64_t Address, 1612 const void *Decoder) { 1613 int Offset = SignExtend32<16>(Insn & 0xffff); 1614 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1615 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1616 1617 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1618 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1619 1620 Inst.addOperand(MCOperand::createReg(Reg)); 1621 Inst.addOperand(MCOperand::createReg(Base)); 1622 Inst.addOperand(MCOperand::createImm(Offset)); 1623 1624 return MCDisassembler::Success; 1625 } 1626 1627 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1628 unsigned Insn, 1629 uint64_t Address, 1630 const void *Decoder) { 1631 int Offset = SignExtend32<11>(Insn & 0x07ff); 1632 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1633 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1634 1635 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1636 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1637 1638 Inst.addOperand(MCOperand::createReg(Reg)); 1639 Inst.addOperand(MCOperand::createReg(Base)); 1640 Inst.addOperand(MCOperand::createImm(Offset)); 1641 1642 return MCDisassembler::Success; 1643 } 1644 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1645 unsigned Insn, 1646 uint64_t Address, 1647 const void *Decoder) { 1648 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1649 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1650 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1651 1652 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1653 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1654 1655 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1656 Inst.addOperand(MCOperand::createReg(Rt)); 1657 } 1658 1659 Inst.addOperand(MCOperand::createReg(Rt)); 1660 Inst.addOperand(MCOperand::createReg(Base)); 1661 Inst.addOperand(MCOperand::createImm(Offset)); 1662 1663 return MCDisassembler::Success; 1664 } 1665 1666 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1667 unsigned RegNo, 1668 uint64_t Address, 1669 const void *Decoder) { 1670 // Currently only hardware register 29 is supported. 1671 if (RegNo != 29) 1672 return MCDisassembler::Fail; 1673 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1674 return MCDisassembler::Success; 1675 } 1676 1677 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1678 unsigned RegNo, 1679 uint64_t Address, 1680 const void *Decoder) { 1681 if (RegNo > 30 || RegNo %2) 1682 return MCDisassembler::Fail; 1683 1684 ; 1685 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1686 Inst.addOperand(MCOperand::createReg(Reg)); 1687 return MCDisassembler::Success; 1688 } 1689 1690 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1691 unsigned RegNo, 1692 uint64_t Address, 1693 const void *Decoder) { 1694 if (RegNo >= 4) 1695 return MCDisassembler::Fail; 1696 1697 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1698 Inst.addOperand(MCOperand::createReg(Reg)); 1699 return MCDisassembler::Success; 1700 } 1701 1702 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1703 unsigned RegNo, 1704 uint64_t Address, 1705 const void *Decoder) { 1706 if (RegNo >= 4) 1707 return MCDisassembler::Fail; 1708 1709 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1710 Inst.addOperand(MCOperand::createReg(Reg)); 1711 return MCDisassembler::Success; 1712 } 1713 1714 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1715 unsigned RegNo, 1716 uint64_t Address, 1717 const void *Decoder) { 1718 if (RegNo >= 4) 1719 return MCDisassembler::Fail; 1720 1721 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1722 Inst.addOperand(MCOperand::createReg(Reg)); 1723 return MCDisassembler::Success; 1724 } 1725 1726 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1727 unsigned RegNo, 1728 uint64_t Address, 1729 const void *Decoder) { 1730 if (RegNo > 31) 1731 return MCDisassembler::Fail; 1732 1733 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1734 Inst.addOperand(MCOperand::createReg(Reg)); 1735 return MCDisassembler::Success; 1736 } 1737 1738 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1739 unsigned RegNo, 1740 uint64_t Address, 1741 const void *Decoder) { 1742 if (RegNo > 31) 1743 return MCDisassembler::Fail; 1744 1745 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1746 Inst.addOperand(MCOperand::createReg(Reg)); 1747 return MCDisassembler::Success; 1748 } 1749 1750 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1751 unsigned RegNo, 1752 uint64_t Address, 1753 const void *Decoder) { 1754 if (RegNo > 31) 1755 return MCDisassembler::Fail; 1756 1757 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1758 Inst.addOperand(MCOperand::createReg(Reg)); 1759 return MCDisassembler::Success; 1760 } 1761 1762 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1763 unsigned RegNo, 1764 uint64_t Address, 1765 const void *Decoder) { 1766 if (RegNo > 31) 1767 return MCDisassembler::Fail; 1768 1769 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1770 Inst.addOperand(MCOperand::createReg(Reg)); 1771 return MCDisassembler::Success; 1772 } 1773 1774 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1775 unsigned RegNo, 1776 uint64_t Address, 1777 const void *Decoder) { 1778 if (RegNo > 7) 1779 return MCDisassembler::Fail; 1780 1781 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1782 Inst.addOperand(MCOperand::createReg(Reg)); 1783 return MCDisassembler::Success; 1784 } 1785 1786 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1787 unsigned RegNo, 1788 uint64_t Address, 1789 const void *Decoder) { 1790 if (RegNo > 31) 1791 return MCDisassembler::Fail; 1792 1793 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1794 Inst.addOperand(MCOperand::createReg(Reg)); 1795 return MCDisassembler::Success; 1796 } 1797 1798 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1799 unsigned RegNo, 1800 uint64_t Address, 1801 const void *Decoder) { 1802 if (RegNo > 31) 1803 return MCDisassembler::Fail; 1804 1805 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1806 Inst.addOperand(MCOperand::createReg(Reg)); 1807 return MCDisassembler::Success; 1808 } 1809 1810 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1811 unsigned Offset, 1812 uint64_t Address, 1813 const void *Decoder) { 1814 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1815 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1816 return MCDisassembler::Success; 1817 } 1818 1819 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1820 unsigned Insn, 1821 uint64_t Address, 1822 const void *Decoder) { 1823 1824 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1825 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1826 return MCDisassembler::Success; 1827 } 1828 1829 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1830 unsigned Offset, 1831 uint64_t Address, 1832 const void *Decoder) { 1833 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1834 1835 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1836 return MCDisassembler::Success; 1837 } 1838 1839 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1840 unsigned Offset, 1841 uint64_t Address, 1842 const void *Decoder) { 1843 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1844 1845 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1846 return MCDisassembler::Success; 1847 } 1848 1849 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1850 unsigned Offset, 1851 uint64_t Address, 1852 const void *Decoder) { 1853 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1854 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1855 return MCDisassembler::Success; 1856 } 1857 1858 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1859 unsigned Offset, 1860 uint64_t Address, 1861 const void *Decoder) { 1862 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1863 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1864 return MCDisassembler::Success; 1865 } 1866 1867 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1868 unsigned Offset, 1869 uint64_t Address, 1870 const void *Decoder) { 1871 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1872 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1873 return MCDisassembler::Success; 1874 } 1875 1876 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 1877 unsigned Offset, 1878 uint64_t Address, 1879 const void *Decoder) { 1880 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 1881 1882 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1883 return MCDisassembler::Success; 1884 } 1885 1886 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1887 unsigned Insn, 1888 uint64_t Address, 1889 const void *Decoder) { 1890 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1891 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1892 return MCDisassembler::Success; 1893 } 1894 1895 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1896 unsigned Value, 1897 uint64_t Address, 1898 const void *Decoder) { 1899 if (Value == 0) 1900 Inst.addOperand(MCOperand::createImm(1)); 1901 else if (Value == 0x7) 1902 Inst.addOperand(MCOperand::createImm(-1)); 1903 else 1904 Inst.addOperand(MCOperand::createImm(Value << 2)); 1905 return MCDisassembler::Success; 1906 } 1907 1908 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 1909 unsigned Value, 1910 uint64_t Address, 1911 const void *Decoder) { 1912 if (Value == 0x7F) 1913 Inst.addOperand(MCOperand::createImm(-1)); 1914 else 1915 Inst.addOperand(MCOperand::createImm(Value)); 1916 return MCDisassembler::Success; 1917 } 1918 1919 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1920 unsigned Value, 1921 uint64_t Address, 1922 const void *Decoder) { 1923 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1924 return MCDisassembler::Success; 1925 } 1926 1927 template <unsigned Bits, int Offset, int Scale> 1928 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1929 uint64_t Address, 1930 const void *Decoder) { 1931 Value &= ((1 << Bits) - 1); 1932 Value *= Scale; 1933 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1934 return MCDisassembler::Success; 1935 } 1936 1937 template <unsigned Bits, int Offset, int ScaleBy> 1938 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1939 uint64_t Address, 1940 const void *Decoder) { 1941 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 1942 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 1943 return MCDisassembler::Success; 1944 } 1945 1946 static DecodeStatus DecodeInsSize(MCInst &Inst, 1947 unsigned Insn, 1948 uint64_t Address, 1949 const void *Decoder) { 1950 // First we need to grab the pos(lsb) from MCInst. 1951 int Pos = Inst.getOperand(2).getImm(); 1952 int Size = (int) Insn - Pos + 1; 1953 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1954 return MCDisassembler::Success; 1955 } 1956 1957 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1958 uint64_t Address, const void *Decoder) { 1959 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1960 return MCDisassembler::Success; 1961 } 1962 1963 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1964 uint64_t Address, const void *Decoder) { 1965 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1966 return MCDisassembler::Success; 1967 } 1968 1969 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1970 uint64_t Address, const void *Decoder) { 1971 int32_t DecodedValue; 1972 switch (Insn) { 1973 case 0: DecodedValue = 256; break; 1974 case 1: DecodedValue = 257; break; 1975 case 510: DecodedValue = -258; break; 1976 case 511: DecodedValue = -257; break; 1977 default: DecodedValue = SignExtend32<9>(Insn); break; 1978 } 1979 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1980 return MCDisassembler::Success; 1981 } 1982 1983 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1984 uint64_t Address, const void *Decoder) { 1985 // Insn must be >= 0, since it is unsigned that condition is always true. 1986 assert(Insn < 16); 1987 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1988 255, 32768, 65535}; 1989 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 1990 return MCDisassembler::Success; 1991 } 1992 1993 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1994 unsigned Insn, 1995 uint64_t Address, 1996 const void *Decoder) { 1997 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1998 Mips::S6, Mips::S7, Mips::FP}; 1999 unsigned RegNum; 2000 2001 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2002 2003 // Empty register lists are not allowed. 2004 if (RegLst == 0) 2005 return MCDisassembler::Fail; 2006 2007 RegNum = RegLst & 0xf; 2008 2009 // RegLst values 10-15, and 26-31 are reserved. 2010 if (RegNum > 9) 2011 return MCDisassembler::Fail; 2012 2013 for (unsigned i = 0; i < RegNum; i++) 2014 Inst.addOperand(MCOperand::createReg(Regs[i])); 2015 2016 if (RegLst & 0x10) 2017 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2018 2019 return MCDisassembler::Success; 2020 } 2021 2022 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2023 uint64_t Address, 2024 const void *Decoder) { 2025 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2026 unsigned RegLst; 2027 switch(Inst.getOpcode()) { 2028 default: 2029 RegLst = fieldFromInstruction(Insn, 4, 2); 2030 break; 2031 case Mips::LWM16_MMR6: 2032 case Mips::SWM16_MMR6: 2033 RegLst = fieldFromInstruction(Insn, 8, 2); 2034 break; 2035 } 2036 unsigned RegNum = RegLst & 0x3; 2037 2038 for (unsigned i = 0; i <= RegNum; i++) 2039 Inst.addOperand(MCOperand::createReg(Regs[i])); 2040 2041 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2042 2043 return MCDisassembler::Success; 2044 } 2045 2046 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2047 uint64_t Address, const void *Decoder) { 2048 2049 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2050 2051 switch (RegPair) { 2052 default: 2053 return MCDisassembler::Fail; 2054 case 0: 2055 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2056 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2057 break; 2058 case 1: 2059 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2060 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2061 break; 2062 case 2: 2063 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2064 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2065 break; 2066 case 3: 2067 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2068 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2069 break; 2070 case 4: 2071 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2072 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2073 break; 2074 case 5: 2075 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2076 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2077 break; 2078 case 6: 2079 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2080 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2081 break; 2082 case 7: 2083 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2084 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2085 break; 2086 } 2087 2088 return MCDisassembler::Success; 2089 } 2090 2091 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2092 uint64_t Address, const void *Decoder) { 2093 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2094 return MCDisassembler::Success; 2095 } 2096