1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCTargetDesc.h" 15 #include "Mips.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeMem(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeMemEVA(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 291 const void *Decoder); 292 293 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 294 unsigned Insn, 295 uint64_t Address, 296 const void *Decoder); 297 298 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 299 unsigned Insn, 300 uint64_t Address, 301 const void *Decoder); 302 303 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 304 unsigned Insn, 305 uint64_t Address, 306 const void *Decoder); 307 308 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 309 unsigned Insn, 310 uint64_t Address, 311 const void *Decoder); 312 313 static DecodeStatus DecodeSyncI(MCInst &Inst, 314 unsigned Insn, 315 uint64_t Address, 316 const void *Decoder); 317 318 static DecodeStatus DecodeSynciR6(MCInst &Inst, 319 unsigned Insn, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 324 uint64_t Address, const void *Decoder); 325 326 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 327 unsigned Insn, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 332 unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 337 unsigned Insn, 338 uint64_t Address, 339 const void *Decoder); 340 341 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 342 unsigned Insn, 343 uint64_t Address, 344 const void *Decoder); 345 346 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 347 unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 352 unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 357 unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 370 const void *Decoder); 371 372 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 378 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 383 unsigned Insn, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 398 unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset, int Scale> 403 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder); 406 407 template <unsigned Bits, int Offset> 408 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 409 uint64_t Address, 410 const void *Decoder) { 411 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 412 Decoder); 413 } 414 415 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 416 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeInsSize(MCInst &Inst, 421 unsigned Insn, 422 uint64_t Address, 423 const void *Decoder); 424 425 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 426 uint64_t Address, const void *Decoder); 427 428 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void *Decoder); 430 431 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 432 uint64_t Address, const void *Decoder); 433 434 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void *Decoder); 436 437 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 438 uint64_t Address, const void *Decoder); 439 440 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 441 /// handle. 442 template <typename InsnType> 443 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 444 const void *Decoder); 445 446 template <typename InsnType> 447 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 452 const void *Decoder); 453 454 template <typename InsnType> 455 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus 464 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 465 const void *Decoder); 466 467 template <typename InsnType> 468 static DecodeStatus 469 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 470 const void *Decoder); 471 472 template <typename InsnType> 473 static DecodeStatus 474 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 475 const void *Decoder); 476 477 template <typename InsnType> 478 static DecodeStatus 479 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 480 const void *Decoder); 481 482 template <typename InsnType> 483 static DecodeStatus 484 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 485 const void *Decoder); 486 487 template <typename InsnType> 488 static DecodeStatus 489 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 490 const void *Decoder); 491 492 template <typename InsnType> 493 static DecodeStatus 494 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 495 const void *Decoder); 496 497 template <typename InsnType> 498 static DecodeStatus 499 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 500 const void *Decoder); 501 502 template <typename InsnType> 503 static DecodeStatus 504 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 505 const void *Decoder); 506 507 template <typename InsnType> 508 static DecodeStatus 509 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 510 const void *Decoder); 511 512 template <typename InsnType> 513 static DecodeStatus 514 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 515 const void *Decoder); 516 517 template <typename InsnType> 518 static DecodeStatus 519 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 520 const void *Decoder); 521 522 template <typename InsnType> 523 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 524 const void *Decoder); 525 526 template <typename InsnType> 527 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 528 const void *Decoder); 529 530 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 531 uint64_t Address, 532 const void *Decoder); 533 534 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 535 uint64_t Address, 536 const void *Decoder); 537 538 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 539 uint64_t Address, 540 const void *Decoder); 541 542 namespace llvm { 543 544 Target &getTheMipselTarget(); 545 Target &getTheMipsTarget(); 546 Target &getTheMips64Target(); 547 Target &getTheMips64elTarget(); 548 549 } // end namespace llvm 550 551 static MCDisassembler *createMipsDisassembler( 552 const Target &T, 553 const MCSubtargetInfo &STI, 554 MCContext &Ctx) { 555 return new MipsDisassembler(STI, Ctx, true); 556 } 557 558 static MCDisassembler *createMipselDisassembler( 559 const Target &T, 560 const MCSubtargetInfo &STI, 561 MCContext &Ctx) { 562 return new MipsDisassembler(STI, Ctx, false); 563 } 564 565 extern "C" void LLVMInitializeMipsDisassembler() { 566 // Register the disassembler. 567 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 568 createMipsDisassembler); 569 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 570 createMipselDisassembler); 571 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 572 createMipsDisassembler); 573 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 574 createMipselDisassembler); 575 } 576 577 #include "MipsGenDisassemblerTables.inc" 578 579 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 580 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 581 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 582 return *(RegInfo->getRegClass(RC).begin() + RegNo); 583 } 584 585 template <typename InsnType> 586 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 587 const void *Decoder) { 588 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 589 590 // The size of the n field depends on the element size 591 // The register class also depends on this. 592 InsnType tmp = fieldFromInstruction(insn, 17, 5); 593 unsigned NSize = 0; 594 DecodeFN RegDecoder = nullptr; 595 if ((tmp & 0x18) == 0x00) { // INSVE_B 596 NSize = 4; 597 RegDecoder = DecodeMSA128BRegisterClass; 598 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 599 NSize = 3; 600 RegDecoder = DecodeMSA128HRegisterClass; 601 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 602 NSize = 2; 603 RegDecoder = DecodeMSA128WRegisterClass; 604 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 605 NSize = 1; 606 RegDecoder = DecodeMSA128DRegisterClass; 607 } else 608 llvm_unreachable("Invalid encoding"); 609 610 assert(NSize != 0 && RegDecoder != nullptr); 611 612 // $wd 613 tmp = fieldFromInstruction(insn, 6, 5); 614 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 615 return MCDisassembler::Fail; 616 // $wd_in 617 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 618 return MCDisassembler::Fail; 619 // $n 620 tmp = fieldFromInstruction(insn, 16, NSize); 621 MI.addOperand(MCOperand::createImm(tmp)); 622 // $ws 623 tmp = fieldFromInstruction(insn, 11, 5); 624 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 625 return MCDisassembler::Fail; 626 // $n2 627 MI.addOperand(MCOperand::createImm(0)); 628 629 return MCDisassembler::Success; 630 } 631 632 template <typename InsnType> 633 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 634 const void *Decoder) { 635 InsnType Rs = fieldFromInstruction(insn, 16, 5); 636 InsnType Imm = fieldFromInstruction(insn, 0, 16); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 638 Rs))); 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 640 Rs))); 641 MI.addOperand(MCOperand::createImm(Imm)); 642 643 return MCDisassembler::Success; 644 } 645 646 template <typename InsnType> 647 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 648 const void *Decoder) { 649 InsnType Rs = fieldFromInstruction(insn, 21, 5); 650 InsnType Imm = fieldFromInstruction(insn, 0, 16); 651 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 652 Rs))); 653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 654 Rs))); 655 MI.addOperand(MCOperand::createImm(Imm)); 656 657 return MCDisassembler::Success; 658 } 659 660 template <typename InsnType> 661 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 662 uint64_t Address, 663 const void *Decoder) { 664 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 665 // (otherwise we would have matched the ADDI instruction from the earlier 666 // ISA's instead). 667 // 668 // We have: 669 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 670 // BOVC if rs >= rt 671 // BEQZALC if rs == 0 && rt != 0 672 // BEQC if rs < rt && rs != 0 673 674 InsnType Rs = fieldFromInstruction(insn, 21, 5); 675 InsnType Rt = fieldFromInstruction(insn, 16, 5); 676 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 677 bool HasRs = false; 678 679 if (Rs >= Rt) { 680 MI.setOpcode(Mips::BOVC); 681 HasRs = true; 682 } else if (Rs != 0 && Rs < Rt) { 683 MI.setOpcode(Mips::BEQC); 684 HasRs = true; 685 } else 686 MI.setOpcode(Mips::BEQZALC); 687 688 if (HasRs) 689 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 690 Rs))); 691 692 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 693 Rt))); 694 MI.addOperand(MCOperand::createImm(Imm)); 695 696 return MCDisassembler::Success; 697 } 698 699 template <typename InsnType> 700 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 701 uint64_t Address, 702 const void *Decoder) { 703 InsnType Rt = fieldFromInstruction(insn, 21, 5); 704 InsnType Rs = fieldFromInstruction(insn, 16, 5); 705 int64_t Imm = 0; 706 707 if (Rs >= Rt) { 708 MI.setOpcode(Mips::BOVC_MMR6); 709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 710 Rt))); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rs))); 713 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 714 } else if (Rs != 0 && Rs < Rt) { 715 MI.setOpcode(Mips::BEQC_MMR6); 716 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 717 Rs))); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rt))); 720 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 721 } else { 722 MI.setOpcode(Mips::BEQZALC_MMR6); 723 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 724 Rt))); 725 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 726 } 727 728 MI.addOperand(MCOperand::createImm(Imm)); 729 730 return MCDisassembler::Success; 731 } 732 733 template <typename InsnType> 734 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 735 uint64_t Address, 736 const void *Decoder) { 737 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 738 // (otherwise we would have matched the ADDI instruction from the earlier 739 // ISA's instead). 740 // 741 // We have: 742 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 743 // BNVC if rs >= rt 744 // BNEZALC if rs == 0 && rt != 0 745 // BNEC if rs < rt && rs != 0 746 747 InsnType Rs = fieldFromInstruction(insn, 21, 5); 748 InsnType Rt = fieldFromInstruction(insn, 16, 5); 749 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 750 bool HasRs = false; 751 752 if (Rs >= Rt) { 753 MI.setOpcode(Mips::BNVC); 754 HasRs = true; 755 } else if (Rs != 0 && Rs < Rt) { 756 MI.setOpcode(Mips::BNEC); 757 HasRs = true; 758 } else 759 MI.setOpcode(Mips::BNEZALC); 760 761 if (HasRs) 762 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 763 Rs))); 764 765 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 766 Rt))); 767 MI.addOperand(MCOperand::createImm(Imm)); 768 769 return MCDisassembler::Success; 770 } 771 772 template <typename InsnType> 773 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 774 uint64_t Address, 775 const void *Decoder) { 776 InsnType Rt = fieldFromInstruction(insn, 21, 5); 777 InsnType Rs = fieldFromInstruction(insn, 16, 5); 778 int64_t Imm = 0; 779 780 if (Rs >= Rt) { 781 MI.setOpcode(Mips::BNVC_MMR6); 782 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 783 Rt))); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rs))); 786 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 787 } else if (Rs != 0 && Rs < Rt) { 788 MI.setOpcode(Mips::BNEC_MMR6); 789 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 790 Rs))); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rt))); 793 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 794 } else { 795 MI.setOpcode(Mips::BNEZALC_MMR6); 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rt))); 798 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 799 } 800 801 MI.addOperand(MCOperand::createImm(Imm)); 802 803 return MCDisassembler::Success; 804 } 805 806 template <typename InsnType> 807 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 808 uint64_t Address, 809 const void *Decoder) { 810 // We have: 811 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 812 // Invalid if rt == 0 813 // BGTZC_MMR6 if rs == 0 && rt != 0 814 // BLTZC_MMR6 if rs == rt && rt != 0 815 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 816 817 InsnType Rt = fieldFromInstruction(insn, 21, 5); 818 InsnType Rs = fieldFromInstruction(insn, 16, 5); 819 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 820 bool HasRs = false; 821 822 if (Rt == 0) 823 return MCDisassembler::Fail; 824 else if (Rs == 0) 825 MI.setOpcode(Mips::BGTZC_MMR6); 826 else if (Rs == Rt) 827 MI.setOpcode(Mips::BLTZC_MMR6); 828 else { 829 MI.setOpcode(Mips::BLTC_MMR6); 830 HasRs = true; 831 } 832 833 if (HasRs) 834 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 835 Rs))); 836 837 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 838 Rt))); 839 840 MI.addOperand(MCOperand::createImm(Imm)); 841 842 return MCDisassembler::Success; 843 } 844 845 template <typename InsnType> 846 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 847 uint64_t Address, 848 const void *Decoder) { 849 // We have: 850 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 851 // Invalid if rt == 0 852 // BLEZC_MMR6 if rs == 0 && rt != 0 853 // BGEZC_MMR6 if rs == rt && rt != 0 854 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 855 856 InsnType Rt = fieldFromInstruction(insn, 21, 5); 857 InsnType Rs = fieldFromInstruction(insn, 16, 5); 858 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 859 bool HasRs = false; 860 861 if (Rt == 0) 862 return MCDisassembler::Fail; 863 else if (Rs == 0) 864 MI.setOpcode(Mips::BLEZC_MMR6); 865 else if (Rs == Rt) 866 MI.setOpcode(Mips::BGEZC_MMR6); 867 else { 868 HasRs = true; 869 MI.setOpcode(Mips::BGEC_MMR6); 870 } 871 872 if (HasRs) 873 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 874 Rs))); 875 876 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 877 Rt))); 878 879 MI.addOperand(MCOperand::createImm(Imm)); 880 881 return MCDisassembler::Success; 882 } 883 884 template <typename InsnType> 885 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 886 uint64_t Address, 887 const void *Decoder) { 888 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 889 // (otherwise we would have matched the BLEZL instruction from the earlier 890 // ISA's instead). 891 // 892 // We have: 893 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 894 // Invalid if rs == 0 895 // BLEZC if rs == 0 && rt != 0 896 // BGEZC if rs == rt && rt != 0 897 // BGEC if rs != rt && rs != 0 && rt != 0 898 899 InsnType Rs = fieldFromInstruction(insn, 21, 5); 900 InsnType Rt = fieldFromInstruction(insn, 16, 5); 901 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 902 bool HasRs = false; 903 904 if (Rt == 0) 905 return MCDisassembler::Fail; 906 else if (Rs == 0) 907 MI.setOpcode(Mips::BLEZC); 908 else if (Rs == Rt) 909 MI.setOpcode(Mips::BGEZC); 910 else { 911 HasRs = true; 912 MI.setOpcode(Mips::BGEC); 913 } 914 915 if (HasRs) 916 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 917 Rs))); 918 919 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 920 Rt))); 921 922 MI.addOperand(MCOperand::createImm(Imm)); 923 924 return MCDisassembler::Success; 925 } 926 927 template <typename InsnType> 928 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 929 uint64_t Address, 930 const void *Decoder) { 931 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 932 // (otherwise we would have matched the BGTZL instruction from the earlier 933 // ISA's instead). 934 // 935 // We have: 936 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 937 // Invalid if rs == 0 938 // BGTZC if rs == 0 && rt != 0 939 // BLTZC if rs == rt && rt != 0 940 // BLTC if rs != rt && rs != 0 && rt != 0 941 942 bool HasRs = false; 943 944 InsnType Rs = fieldFromInstruction(insn, 21, 5); 945 InsnType Rt = fieldFromInstruction(insn, 16, 5); 946 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 947 948 if (Rt == 0) 949 return MCDisassembler::Fail; 950 else if (Rs == 0) 951 MI.setOpcode(Mips::BGTZC); 952 else if (Rs == Rt) 953 MI.setOpcode(Mips::BLTZC); 954 else { 955 MI.setOpcode(Mips::BLTC); 956 HasRs = true; 957 } 958 959 if (HasRs) 960 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 961 Rs))); 962 963 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 964 Rt))); 965 966 MI.addOperand(MCOperand::createImm(Imm)); 967 968 return MCDisassembler::Success; 969 } 970 971 template <typename InsnType> 972 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 973 uint64_t Address, 974 const void *Decoder) { 975 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 976 // (otherwise we would have matched the BGTZ instruction from the earlier 977 // ISA's instead). 978 // 979 // We have: 980 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 981 // BGTZ if rt == 0 982 // BGTZALC if rs == 0 && rt != 0 983 // BLTZALC if rs != 0 && rs == rt 984 // BLTUC if rs != 0 && rs != rt 985 986 InsnType Rs = fieldFromInstruction(insn, 21, 5); 987 InsnType Rt = fieldFromInstruction(insn, 16, 5); 988 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 989 bool HasRs = false; 990 bool HasRt = false; 991 992 if (Rt == 0) { 993 MI.setOpcode(Mips::BGTZ); 994 HasRs = true; 995 } else if (Rs == 0) { 996 MI.setOpcode(Mips::BGTZALC); 997 HasRt = true; 998 } else if (Rs == Rt) { 999 MI.setOpcode(Mips::BLTZALC); 1000 HasRs = true; 1001 } else { 1002 MI.setOpcode(Mips::BLTUC); 1003 HasRs = true; 1004 HasRt = true; 1005 } 1006 1007 if (HasRs) 1008 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1009 Rs))); 1010 1011 if (HasRt) 1012 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1013 Rt))); 1014 1015 MI.addOperand(MCOperand::createImm(Imm)); 1016 1017 return MCDisassembler::Success; 1018 } 1019 1020 template <typename InsnType> 1021 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1022 uint64_t Address, 1023 const void *Decoder) { 1024 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1025 // (otherwise we would have matched the BLEZL instruction from the earlier 1026 // ISA's instead). 1027 // 1028 // We have: 1029 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1030 // Invalid if rs == 0 1031 // BLEZALC if rs == 0 && rt != 0 1032 // BGEZALC if rs == rt && rt != 0 1033 // BGEUC if rs != rt && rs != 0 && rt != 0 1034 1035 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1036 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1037 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1038 bool HasRs = false; 1039 1040 if (Rt == 0) 1041 return MCDisassembler::Fail; 1042 else if (Rs == 0) 1043 MI.setOpcode(Mips::BLEZALC); 1044 else if (Rs == Rt) 1045 MI.setOpcode(Mips::BGEZALC); 1046 else { 1047 HasRs = true; 1048 MI.setOpcode(Mips::BGEUC); 1049 } 1050 1051 if (HasRs) 1052 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1053 Rs))); 1054 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1055 Rt))); 1056 1057 MI.addOperand(MCOperand::createImm(Imm)); 1058 1059 return MCDisassembler::Success; 1060 } 1061 1062 // Override the generated disassembler to produce DEXT all the time. This is 1063 // for feature / behaviour parity with binutils. 1064 template <typename InsnType> 1065 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1066 const void *Decoder) { 1067 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1068 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1069 unsigned Size = 0; 1070 unsigned Pos = 0; 1071 bool IsMicroMips = false; 1072 1073 switch (MI.getOpcode()) { 1074 case Mips::DEXT_MM64R6: 1075 IsMicroMips = true; 1076 LLVM_FALLTHROUGH; 1077 case Mips::DEXT: 1078 Pos = Lsb; 1079 Size = Msbd + 1; 1080 break; 1081 case Mips::DEXTM_MM64R6: 1082 IsMicroMips = true; 1083 LLVM_FALLTHROUGH; 1084 case Mips::DEXTM: 1085 Pos = Lsb; 1086 Size = Msbd + 1 + 32; 1087 break; 1088 case Mips::DEXTU_MM64R6: 1089 IsMicroMips = true; 1090 LLVM_FALLTHROUGH; 1091 case Mips::DEXTU: 1092 Pos = Lsb + 32; 1093 Size = Msbd + 1; 1094 break; 1095 default: 1096 llvm_unreachable("Unknown DEXT instruction!"); 1097 } 1098 1099 MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT); 1100 1101 // Although the format of the instruction is similar, rs and rt are swapped 1102 // for microMIPS64R6. 1103 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1104 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1105 if (IsMicroMips) 1106 std::swap(Rs, Rt); 1107 1108 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1109 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1110 MI.addOperand(MCOperand::createImm(Pos)); 1111 MI.addOperand(MCOperand::createImm(Size)); 1112 1113 return MCDisassembler::Success; 1114 } 1115 1116 // Override the generated disassembler to produce DINS all the time. This is 1117 // for feature / behaviour parity with binutils. 1118 template <typename InsnType> 1119 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1120 const void *Decoder) { 1121 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1122 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1123 unsigned Size = 0; 1124 unsigned Pos = 0; 1125 bool IsMicroMips = false; 1126 1127 switch (MI.getOpcode()) { 1128 case Mips::DINS_MM64R6: 1129 IsMicroMips = true; 1130 LLVM_FALLTHROUGH; 1131 case Mips::DINS: 1132 Pos = Lsb; 1133 Size = Msbd + 1 - Pos; 1134 break; 1135 case Mips::DINSM_MM64R6: 1136 IsMicroMips = true; 1137 LLVM_FALLTHROUGH; 1138 case Mips::DINSM: 1139 Pos = Lsb; 1140 Size = Msbd + 33 - Pos; 1141 break; 1142 case Mips::DINSU_MM64R6: 1143 IsMicroMips = true; 1144 LLVM_FALLTHROUGH; 1145 case Mips::DINSU: 1146 Pos = Lsb + 32; 1147 // mbsd = pos + size - 33 1148 // mbsd - pos + 33 = size 1149 Size = Msbd + 33 - Pos; 1150 break; 1151 default: 1152 llvm_unreachable("Unknown DINS instruction!"); 1153 } 1154 1155 // Although the format of the instruction is similar, rs and rt are swapped 1156 // for microMIPS64R6. 1157 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1158 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1159 if (IsMicroMips) 1160 std::swap(Rs, Rt); 1161 1162 MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS); 1163 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1164 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1165 MI.addOperand(MCOperand::createImm(Pos)); 1166 MI.addOperand(MCOperand::createImm(Size)); 1167 1168 return MCDisassembler::Success; 1169 } 1170 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1171 /// according to the given endianness. 1172 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1173 uint64_t &Size, uint32_t &Insn, 1174 bool IsBigEndian) { 1175 // We want to read exactly 2 Bytes of data. 1176 if (Bytes.size() < 2) { 1177 Size = 0; 1178 return MCDisassembler::Fail; 1179 } 1180 1181 if (IsBigEndian) { 1182 Insn = (Bytes[0] << 8) | Bytes[1]; 1183 } else { 1184 Insn = (Bytes[1] << 8) | Bytes[0]; 1185 } 1186 1187 return MCDisassembler::Success; 1188 } 1189 1190 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1191 /// according to the given endianness. 1192 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1193 uint64_t &Size, uint32_t &Insn, 1194 bool IsBigEndian, bool IsMicroMips) { 1195 // We want to read exactly 4 Bytes of data. 1196 if (Bytes.size() < 4) { 1197 Size = 0; 1198 return MCDisassembler::Fail; 1199 } 1200 1201 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1202 // always precede the low 16 bits in the instruction stream (that is, they 1203 // are placed at lower addresses in the instruction stream). 1204 // 1205 // microMIPS byte ordering: 1206 // Big-endian: 0 | 1 | 2 | 3 1207 // Little-endian: 1 | 0 | 3 | 2 1208 1209 if (IsBigEndian) { 1210 // Encoded as a big-endian 32-bit word in the stream. 1211 Insn = 1212 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1213 } else { 1214 if (IsMicroMips) { 1215 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1216 (Bytes[1] << 24); 1217 } else { 1218 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1219 (Bytes[3] << 24); 1220 } 1221 } 1222 1223 return MCDisassembler::Success; 1224 } 1225 1226 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1227 ArrayRef<uint8_t> Bytes, 1228 uint64_t Address, 1229 raw_ostream &VStream, 1230 raw_ostream &CStream) const { 1231 uint32_t Insn; 1232 DecodeStatus Result; 1233 Size = 0; 1234 1235 if (IsMicroMips) { 1236 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1237 if (Result == MCDisassembler::Fail) 1238 return MCDisassembler::Fail; 1239 1240 if (hasMips32r6()) { 1241 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1242 // Calling the auto-generated decoder function for microMIPS32R6 1243 // (and microMIPS64R6) 16-bit instructions. 1244 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1245 Address, this, STI); 1246 if (Result != MCDisassembler::Fail) { 1247 Size = 2; 1248 return Result; 1249 } 1250 } 1251 1252 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1253 // Calling the auto-generated decoder function for microMIPS 16-bit 1254 // instructions. 1255 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1256 this, STI); 1257 if (Result != MCDisassembler::Fail) { 1258 Size = 2; 1259 return Result; 1260 } 1261 1262 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1263 if (Result == MCDisassembler::Fail) 1264 return MCDisassembler::Fail; 1265 1266 if (hasMips32r6()) { 1267 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1268 // Calling the auto-generated decoder function. 1269 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1270 this, STI); 1271 if (Result != MCDisassembler::Fail) { 1272 Size = 4; 1273 return Result; 1274 } 1275 } 1276 1277 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1278 // Calling the auto-generated decoder function. 1279 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1280 this, STI); 1281 if (Result != MCDisassembler::Fail) { 1282 Size = 4; 1283 return Result; 1284 } 1285 1286 if (isFP64()) { 1287 DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1288 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1289 Address, this, STI); 1290 if (Result != MCDisassembler::Fail) { 1291 Size = 4; 1292 return Result; 1293 } 1294 } 1295 1296 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1297 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1298 // could form a valid instruction. The two bytes we rejected as an 1299 // instruction could have actually beeen an inline constant pool that is 1300 // unconditionally branched over. 1301 Size = 2; 1302 return MCDisassembler::Fail; 1303 } 1304 1305 // Attempt to read the instruction so that we can attempt to decode it. If 1306 // the buffer is not 4 bytes long, let the higher level logic figure out 1307 // what to do with a size of zero and MCDisassembler::Fail. 1308 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1309 if (Result == MCDisassembler::Fail) 1310 return MCDisassembler::Fail; 1311 1312 // The only instruction size for standard encoded MIPS. 1313 Size = 4; 1314 1315 if (hasCOP3()) { 1316 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1317 Result = 1318 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1319 if (Result != MCDisassembler::Fail) 1320 return Result; 1321 } 1322 1323 if (hasMips32r6() && isGP64()) { 1324 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1325 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1326 Address, this, STI); 1327 if (Result != MCDisassembler::Fail) 1328 return Result; 1329 } 1330 1331 if (hasMips32r6() && isPTR64()) { 1332 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1333 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1334 Address, this, STI); 1335 if (Result != MCDisassembler::Fail) 1336 return Result; 1337 } 1338 1339 if (hasMips32r6()) { 1340 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1341 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1342 Address, this, STI); 1343 if (Result != MCDisassembler::Fail) 1344 return Result; 1345 } 1346 1347 if (hasMips2() && isPTR64()) { 1348 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1349 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1350 Address, this, STI); 1351 if (Result != MCDisassembler::Fail) 1352 return Result; 1353 } 1354 1355 if (hasCnMips()) { 1356 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1357 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1358 Address, this, STI); 1359 if (Result != MCDisassembler::Fail) 1360 return Result; 1361 } 1362 1363 if (isGP64()) { 1364 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1365 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1366 Address, this, STI); 1367 if (Result != MCDisassembler::Fail) 1368 return Result; 1369 } 1370 1371 if (isFP64()) { 1372 DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1373 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1374 Address, this, STI); 1375 if (Result != MCDisassembler::Fail) 1376 return Result; 1377 } 1378 1379 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1380 // Calling the auto-generated decoder function. 1381 Result = 1382 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1383 if (Result != MCDisassembler::Fail) 1384 return Result; 1385 1386 return MCDisassembler::Fail; 1387 } 1388 1389 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1390 unsigned RegNo, 1391 uint64_t Address, 1392 const void *Decoder) { 1393 return MCDisassembler::Fail; 1394 } 1395 1396 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1397 unsigned RegNo, 1398 uint64_t Address, 1399 const void *Decoder) { 1400 if (RegNo > 31) 1401 return MCDisassembler::Fail; 1402 1403 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1404 Inst.addOperand(MCOperand::createReg(Reg)); 1405 return MCDisassembler::Success; 1406 } 1407 1408 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1409 unsigned RegNo, 1410 uint64_t Address, 1411 const void *Decoder) { 1412 if (RegNo > 7) 1413 return MCDisassembler::Fail; 1414 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1415 Inst.addOperand(MCOperand::createReg(Reg)); 1416 return MCDisassembler::Success; 1417 } 1418 1419 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1420 unsigned RegNo, 1421 uint64_t Address, 1422 const void *Decoder) { 1423 if (RegNo > 7) 1424 return MCDisassembler::Fail; 1425 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1426 Inst.addOperand(MCOperand::createReg(Reg)); 1427 return MCDisassembler::Success; 1428 } 1429 1430 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1431 unsigned RegNo, 1432 uint64_t Address, 1433 const void *Decoder) { 1434 if (RegNo > 7) 1435 return MCDisassembler::Fail; 1436 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1437 Inst.addOperand(MCOperand::createReg(Reg)); 1438 return MCDisassembler::Success; 1439 } 1440 1441 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1442 unsigned RegNo, 1443 uint64_t Address, 1444 const void *Decoder) { 1445 if (RegNo > 31) 1446 return MCDisassembler::Fail; 1447 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1448 Inst.addOperand(MCOperand::createReg(Reg)); 1449 return MCDisassembler::Success; 1450 } 1451 1452 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1453 unsigned RegNo, 1454 uint64_t Address, 1455 const void *Decoder) { 1456 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1457 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1458 1459 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1460 } 1461 1462 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1463 unsigned RegNo, 1464 uint64_t Address, 1465 const void *Decoder) { 1466 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1467 } 1468 1469 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1470 unsigned RegNo, 1471 uint64_t Address, 1472 const void *Decoder) { 1473 if (RegNo > 31) 1474 return MCDisassembler::Fail; 1475 1476 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1477 Inst.addOperand(MCOperand::createReg(Reg)); 1478 return MCDisassembler::Success; 1479 } 1480 1481 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1482 unsigned RegNo, 1483 uint64_t Address, 1484 const void *Decoder) { 1485 if (RegNo > 31) 1486 return MCDisassembler::Fail; 1487 1488 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1489 Inst.addOperand(MCOperand::createReg(Reg)); 1490 return MCDisassembler::Success; 1491 } 1492 1493 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1494 unsigned RegNo, 1495 uint64_t Address, 1496 const void *Decoder) { 1497 if (RegNo > 31) 1498 return MCDisassembler::Fail; 1499 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1500 Inst.addOperand(MCOperand::createReg(Reg)); 1501 return MCDisassembler::Success; 1502 } 1503 1504 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1505 unsigned RegNo, 1506 uint64_t Address, 1507 const void *Decoder) { 1508 if (RegNo > 7) 1509 return MCDisassembler::Fail; 1510 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1511 Inst.addOperand(MCOperand::createReg(Reg)); 1512 return MCDisassembler::Success; 1513 } 1514 1515 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1516 uint64_t Address, 1517 const void *Decoder) { 1518 if (RegNo > 31) 1519 return MCDisassembler::Fail; 1520 1521 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1522 Inst.addOperand(MCOperand::createReg(Reg)); 1523 return MCDisassembler::Success; 1524 } 1525 1526 static DecodeStatus DecodeMem(MCInst &Inst, 1527 unsigned Insn, 1528 uint64_t Address, 1529 const void *Decoder) { 1530 int Offset = SignExtend32<16>(Insn & 0xffff); 1531 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1532 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1533 1534 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1535 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1536 1537 if (Inst.getOpcode() == Mips::SC || 1538 Inst.getOpcode() == Mips::SCD) 1539 Inst.addOperand(MCOperand::createReg(Reg)); 1540 1541 Inst.addOperand(MCOperand::createReg(Reg)); 1542 Inst.addOperand(MCOperand::createReg(Base)); 1543 Inst.addOperand(MCOperand::createImm(Offset)); 1544 1545 return MCDisassembler::Success; 1546 } 1547 1548 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1549 unsigned Insn, 1550 uint64_t Address, 1551 const void *Decoder) { 1552 int Offset = SignExtend32<9>(Insn >> 7); 1553 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1554 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1555 1556 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1557 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1558 1559 if (Inst.getOpcode() == Mips::SCE) 1560 Inst.addOperand(MCOperand::createReg(Reg)); 1561 1562 Inst.addOperand(MCOperand::createReg(Reg)); 1563 Inst.addOperand(MCOperand::createReg(Base)); 1564 Inst.addOperand(MCOperand::createImm(Offset)); 1565 1566 return MCDisassembler::Success; 1567 } 1568 1569 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1570 unsigned Insn, 1571 uint64_t Address, 1572 const void *Decoder) { 1573 int Offset = SignExtend32<9>(Insn & 0x1ff); 1574 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1575 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1576 1577 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1578 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1579 1580 Inst.addOperand(MCOperand::createReg(Reg)); 1581 Inst.addOperand(MCOperand::createReg(Base)); 1582 Inst.addOperand(MCOperand::createImm(Offset)); 1583 1584 return MCDisassembler::Success; 1585 } 1586 1587 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1588 unsigned Insn, 1589 uint64_t Address, 1590 const void *Decoder) { 1591 int Offset = SignExtend32<16>(Insn & 0xffff); 1592 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1593 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1594 1595 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1596 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1597 1598 Inst.addOperand(MCOperand::createReg(Reg)); 1599 Inst.addOperand(MCOperand::createReg(Base)); 1600 Inst.addOperand(MCOperand::createImm(Offset)); 1601 1602 return MCDisassembler::Success; 1603 } 1604 1605 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1606 unsigned Insn, 1607 uint64_t Address, 1608 const void *Decoder) { 1609 int Offset = SignExtend32<16>(Insn & 0xffff); 1610 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1611 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1612 1613 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1614 1615 Inst.addOperand(MCOperand::createReg(Base)); 1616 Inst.addOperand(MCOperand::createImm(Offset)); 1617 Inst.addOperand(MCOperand::createImm(Hint)); 1618 1619 return MCDisassembler::Success; 1620 } 1621 1622 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1623 unsigned Insn, 1624 uint64_t Address, 1625 const void *Decoder) { 1626 int Offset = SignExtend32<12>(Insn & 0xfff); 1627 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1628 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1629 1630 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1631 1632 Inst.addOperand(MCOperand::createReg(Base)); 1633 Inst.addOperand(MCOperand::createImm(Offset)); 1634 Inst.addOperand(MCOperand::createImm(Hint)); 1635 1636 return MCDisassembler::Success; 1637 } 1638 1639 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1640 unsigned Insn, 1641 uint64_t Address, 1642 const void *Decoder) { 1643 int Offset = SignExtend32<9>(Insn & 0x1ff); 1644 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1645 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1646 1647 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1648 1649 Inst.addOperand(MCOperand::createReg(Base)); 1650 Inst.addOperand(MCOperand::createImm(Offset)); 1651 Inst.addOperand(MCOperand::createImm(Hint)); 1652 1653 return MCDisassembler::Success; 1654 } 1655 1656 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1657 unsigned Insn, 1658 uint64_t Address, 1659 const void *Decoder) { 1660 int Offset = SignExtend32<9>(Insn >> 7); 1661 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1662 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1663 1664 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1665 1666 Inst.addOperand(MCOperand::createReg(Base)); 1667 Inst.addOperand(MCOperand::createImm(Offset)); 1668 Inst.addOperand(MCOperand::createImm(Hint)); 1669 1670 return MCDisassembler::Success; 1671 } 1672 1673 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1674 unsigned Insn, 1675 uint64_t Address, 1676 const void *Decoder) { 1677 int Offset = SignExtend32<9>(Insn & 0x1ff); 1678 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1679 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1680 1681 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1682 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1683 1684 Inst.addOperand(MCOperand::createReg(Reg)); 1685 Inst.addOperand(MCOperand::createReg(Base)); 1686 Inst.addOperand(MCOperand::createImm(Offset)); 1687 1688 return MCDisassembler::Success; 1689 } 1690 1691 static DecodeStatus DecodeSyncI(MCInst &Inst, 1692 unsigned Insn, 1693 uint64_t Address, 1694 const void *Decoder) { 1695 int Offset = SignExtend32<16>(Insn & 0xffff); 1696 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1697 1698 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1699 1700 Inst.addOperand(MCOperand::createReg(Base)); 1701 Inst.addOperand(MCOperand::createImm(Offset)); 1702 1703 return MCDisassembler::Success; 1704 } 1705 1706 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1707 unsigned Insn, 1708 uint64_t Address, 1709 const void *Decoder) { 1710 int Immediate = SignExtend32<16>(Insn & 0xffff); 1711 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1712 1713 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1714 1715 Inst.addOperand(MCOperand::createReg(Base)); 1716 Inst.addOperand(MCOperand::createImm(Immediate)); 1717 1718 return MCDisassembler::Success; 1719 } 1720 1721 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1722 uint64_t Address, const void *Decoder) { 1723 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1724 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1725 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1726 1727 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1728 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1729 1730 Inst.addOperand(MCOperand::createReg(Reg)); 1731 Inst.addOperand(MCOperand::createReg(Base)); 1732 1733 // The immediate field of an LD/ST instruction is scaled which means it must 1734 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1735 // data format. 1736 // .b - 1 byte 1737 // .h - 2 bytes 1738 // .w - 4 bytes 1739 // .d - 8 bytes 1740 switch(Inst.getOpcode()) 1741 { 1742 default: 1743 assert(false && "Unexpected instruction"); 1744 return MCDisassembler::Fail; 1745 break; 1746 case Mips::LD_B: 1747 case Mips::ST_B: 1748 Inst.addOperand(MCOperand::createImm(Offset)); 1749 break; 1750 case Mips::LD_H: 1751 case Mips::ST_H: 1752 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1753 break; 1754 case Mips::LD_W: 1755 case Mips::ST_W: 1756 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1757 break; 1758 case Mips::LD_D: 1759 case Mips::ST_D: 1760 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1761 break; 1762 } 1763 1764 return MCDisassembler::Success; 1765 } 1766 1767 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1768 unsigned Insn, 1769 uint64_t Address, 1770 const void *Decoder) { 1771 unsigned Offset = Insn & 0xf; 1772 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1773 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1774 1775 switch (Inst.getOpcode()) { 1776 case Mips::LBU16_MM: 1777 case Mips::LHU16_MM: 1778 case Mips::LW16_MM: 1779 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1780 == MCDisassembler::Fail) 1781 return MCDisassembler::Fail; 1782 break; 1783 case Mips::SB16_MM: 1784 case Mips::SB16_MMR6: 1785 case Mips::SH16_MM: 1786 case Mips::SH16_MMR6: 1787 case Mips::SW16_MM: 1788 case Mips::SW16_MMR6: 1789 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1790 == MCDisassembler::Fail) 1791 return MCDisassembler::Fail; 1792 break; 1793 } 1794 1795 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1796 == MCDisassembler::Fail) 1797 return MCDisassembler::Fail; 1798 1799 switch (Inst.getOpcode()) { 1800 case Mips::LBU16_MM: 1801 if (Offset == 0xf) 1802 Inst.addOperand(MCOperand::createImm(-1)); 1803 else 1804 Inst.addOperand(MCOperand::createImm(Offset)); 1805 break; 1806 case Mips::SB16_MM: 1807 case Mips::SB16_MMR6: 1808 Inst.addOperand(MCOperand::createImm(Offset)); 1809 break; 1810 case Mips::LHU16_MM: 1811 case Mips::SH16_MM: 1812 case Mips::SH16_MMR6: 1813 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1814 break; 1815 case Mips::LW16_MM: 1816 case Mips::SW16_MM: 1817 case Mips::SW16_MMR6: 1818 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1819 break; 1820 } 1821 1822 return MCDisassembler::Success; 1823 } 1824 1825 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1826 unsigned Insn, 1827 uint64_t Address, 1828 const void *Decoder) { 1829 unsigned Offset = Insn & 0x1F; 1830 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1831 1832 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1833 1834 Inst.addOperand(MCOperand::createReg(Reg)); 1835 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1836 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1837 1838 return MCDisassembler::Success; 1839 } 1840 1841 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1842 unsigned Insn, 1843 uint64_t Address, 1844 const void *Decoder) { 1845 unsigned Offset = Insn & 0x7F; 1846 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1847 1848 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1849 1850 Inst.addOperand(MCOperand::createReg(Reg)); 1851 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1852 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1853 1854 return MCDisassembler::Success; 1855 } 1856 1857 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1858 unsigned Insn, 1859 uint64_t Address, 1860 const void *Decoder) { 1861 int Offset; 1862 switch (Inst.getOpcode()) { 1863 case Mips::LWM16_MMR6: 1864 case Mips::SWM16_MMR6: 1865 Offset = fieldFromInstruction(Insn, 4, 4); 1866 break; 1867 default: 1868 Offset = SignExtend32<4>(Insn & 0xf); 1869 break; 1870 } 1871 1872 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1873 == MCDisassembler::Fail) 1874 return MCDisassembler::Fail; 1875 1876 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1877 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1878 1879 return MCDisassembler::Success; 1880 } 1881 1882 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1883 unsigned Insn, 1884 uint64_t Address, 1885 const void *Decoder) { 1886 int Offset = SignExtend32<9>(Insn & 0x1ff); 1887 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1888 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1889 1890 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1891 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1892 1893 if (Inst.getOpcode() == Mips::SCE_MM) 1894 Inst.addOperand(MCOperand::createReg(Reg)); 1895 1896 Inst.addOperand(MCOperand::createReg(Reg)); 1897 Inst.addOperand(MCOperand::createReg(Base)); 1898 Inst.addOperand(MCOperand::createImm(Offset)); 1899 1900 return MCDisassembler::Success; 1901 } 1902 1903 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1904 unsigned Insn, 1905 uint64_t Address, 1906 const void *Decoder) { 1907 int Offset = SignExtend32<12>(Insn & 0x0fff); 1908 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1909 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1910 1911 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1912 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1913 1914 switch (Inst.getOpcode()) { 1915 case Mips::SWM32_MM: 1916 case Mips::LWM32_MM: 1917 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1918 == MCDisassembler::Fail) 1919 return MCDisassembler::Fail; 1920 Inst.addOperand(MCOperand::createReg(Base)); 1921 Inst.addOperand(MCOperand::createImm(Offset)); 1922 break; 1923 case Mips::SC_MM: 1924 Inst.addOperand(MCOperand::createReg(Reg)); 1925 LLVM_FALLTHROUGH; 1926 default: 1927 Inst.addOperand(MCOperand::createReg(Reg)); 1928 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1929 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1930 Inst.addOperand(MCOperand::createReg(Reg+1)); 1931 1932 Inst.addOperand(MCOperand::createReg(Base)); 1933 Inst.addOperand(MCOperand::createImm(Offset)); 1934 } 1935 1936 return MCDisassembler::Success; 1937 } 1938 1939 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1940 unsigned Insn, 1941 uint64_t Address, 1942 const void *Decoder) { 1943 int Offset = SignExtend32<16>(Insn & 0xffff); 1944 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1945 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1946 1947 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1948 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1949 1950 Inst.addOperand(MCOperand::createReg(Reg)); 1951 Inst.addOperand(MCOperand::createReg(Base)); 1952 Inst.addOperand(MCOperand::createImm(Offset)); 1953 1954 return MCDisassembler::Success; 1955 } 1956 1957 static DecodeStatus DecodeFMem(MCInst &Inst, 1958 unsigned Insn, 1959 uint64_t Address, 1960 const void *Decoder) { 1961 int Offset = SignExtend32<16>(Insn & 0xffff); 1962 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1963 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1964 1965 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1966 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1967 1968 Inst.addOperand(MCOperand::createReg(Reg)); 1969 Inst.addOperand(MCOperand::createReg(Base)); 1970 Inst.addOperand(MCOperand::createImm(Offset)); 1971 1972 return MCDisassembler::Success; 1973 } 1974 1975 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1976 uint64_t Address, const void *Decoder) { 1977 // This function is the same as DecodeFMem but with the Reg and Base fields 1978 // swapped according to microMIPS spec. 1979 int Offset = SignExtend32<16>(Insn & 0xffff); 1980 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1981 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1982 1983 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1984 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1985 1986 Inst.addOperand(MCOperand::createReg(Reg)); 1987 Inst.addOperand(MCOperand::createReg(Base)); 1988 Inst.addOperand(MCOperand::createImm(Offset)); 1989 1990 return MCDisassembler::Success; 1991 } 1992 1993 static DecodeStatus DecodeFMem2(MCInst &Inst, 1994 unsigned Insn, 1995 uint64_t Address, 1996 const void *Decoder) { 1997 int Offset = SignExtend32<16>(Insn & 0xffff); 1998 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1999 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2000 2001 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2002 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2003 2004 Inst.addOperand(MCOperand::createReg(Reg)); 2005 Inst.addOperand(MCOperand::createReg(Base)); 2006 Inst.addOperand(MCOperand::createImm(Offset)); 2007 2008 return MCDisassembler::Success; 2009 } 2010 2011 static DecodeStatus DecodeFMem3(MCInst &Inst, 2012 unsigned Insn, 2013 uint64_t Address, 2014 const void *Decoder) { 2015 int Offset = SignExtend32<16>(Insn & 0xffff); 2016 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2017 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2018 2019 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 2020 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2021 2022 Inst.addOperand(MCOperand::createReg(Reg)); 2023 Inst.addOperand(MCOperand::createReg(Base)); 2024 Inst.addOperand(MCOperand::createImm(Offset)); 2025 2026 return MCDisassembler::Success; 2027 } 2028 2029 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2030 unsigned Insn, 2031 uint64_t Address, 2032 const void *Decoder) { 2033 int Offset = SignExtend32<11>(Insn & 0x07ff); 2034 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2035 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2036 2037 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2038 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2039 2040 Inst.addOperand(MCOperand::createReg(Reg)); 2041 Inst.addOperand(MCOperand::createReg(Base)); 2042 Inst.addOperand(MCOperand::createImm(Offset)); 2043 2044 return MCDisassembler::Success; 2045 } 2046 2047 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2048 uint64_t Address, const void *Decoder) { 2049 int Offset = SignExtend32<11>(Insn & 0x07ff); 2050 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2051 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2052 2053 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2054 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2055 2056 Inst.addOperand(MCOperand::createReg(Reg)); 2057 Inst.addOperand(MCOperand::createReg(Base)); 2058 Inst.addOperand(MCOperand::createImm(Offset)); 2059 2060 return MCDisassembler::Success; 2061 } 2062 2063 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2064 unsigned Insn, 2065 uint64_t Address, 2066 const void *Decoder) { 2067 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2068 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2069 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2070 2071 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2072 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2073 2074 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2075 Inst.addOperand(MCOperand::createReg(Rt)); 2076 } 2077 2078 Inst.addOperand(MCOperand::createReg(Rt)); 2079 Inst.addOperand(MCOperand::createReg(Base)); 2080 Inst.addOperand(MCOperand::createImm(Offset)); 2081 2082 return MCDisassembler::Success; 2083 } 2084 2085 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2086 unsigned RegNo, 2087 uint64_t Address, 2088 const void *Decoder) { 2089 // Currently only hardware register 29 is supported. 2090 if (RegNo != 29) 2091 return MCDisassembler::Fail; 2092 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2093 return MCDisassembler::Success; 2094 } 2095 2096 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2097 unsigned RegNo, 2098 uint64_t Address, 2099 const void *Decoder) { 2100 if (RegNo > 30 || RegNo %2) 2101 return MCDisassembler::Fail; 2102 2103 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2104 Inst.addOperand(MCOperand::createReg(Reg)); 2105 return MCDisassembler::Success; 2106 } 2107 2108 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2109 unsigned RegNo, 2110 uint64_t Address, 2111 const void *Decoder) { 2112 if (RegNo >= 4) 2113 return MCDisassembler::Fail; 2114 2115 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2116 Inst.addOperand(MCOperand::createReg(Reg)); 2117 return MCDisassembler::Success; 2118 } 2119 2120 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2121 unsigned RegNo, 2122 uint64_t Address, 2123 const void *Decoder) { 2124 if (RegNo >= 4) 2125 return MCDisassembler::Fail; 2126 2127 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2128 Inst.addOperand(MCOperand::createReg(Reg)); 2129 return MCDisassembler::Success; 2130 } 2131 2132 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2133 unsigned RegNo, 2134 uint64_t Address, 2135 const void *Decoder) { 2136 if (RegNo >= 4) 2137 return MCDisassembler::Fail; 2138 2139 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2140 Inst.addOperand(MCOperand::createReg(Reg)); 2141 return MCDisassembler::Success; 2142 } 2143 2144 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2145 unsigned RegNo, 2146 uint64_t Address, 2147 const void *Decoder) { 2148 if (RegNo > 31) 2149 return MCDisassembler::Fail; 2150 2151 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2152 Inst.addOperand(MCOperand::createReg(Reg)); 2153 return MCDisassembler::Success; 2154 } 2155 2156 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2157 unsigned RegNo, 2158 uint64_t Address, 2159 const void *Decoder) { 2160 if (RegNo > 31) 2161 return MCDisassembler::Fail; 2162 2163 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2164 Inst.addOperand(MCOperand::createReg(Reg)); 2165 return MCDisassembler::Success; 2166 } 2167 2168 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2169 unsigned RegNo, 2170 uint64_t Address, 2171 const void *Decoder) { 2172 if (RegNo > 31) 2173 return MCDisassembler::Fail; 2174 2175 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2176 Inst.addOperand(MCOperand::createReg(Reg)); 2177 return MCDisassembler::Success; 2178 } 2179 2180 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2181 unsigned RegNo, 2182 uint64_t Address, 2183 const void *Decoder) { 2184 if (RegNo > 31) 2185 return MCDisassembler::Fail; 2186 2187 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2188 Inst.addOperand(MCOperand::createReg(Reg)); 2189 return MCDisassembler::Success; 2190 } 2191 2192 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2193 unsigned RegNo, 2194 uint64_t Address, 2195 const void *Decoder) { 2196 if (RegNo > 7) 2197 return MCDisassembler::Fail; 2198 2199 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2200 Inst.addOperand(MCOperand::createReg(Reg)); 2201 return MCDisassembler::Success; 2202 } 2203 2204 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2205 unsigned RegNo, 2206 uint64_t Address, 2207 const void *Decoder) { 2208 if (RegNo > 31) 2209 return MCDisassembler::Fail; 2210 2211 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2212 Inst.addOperand(MCOperand::createReg(Reg)); 2213 return MCDisassembler::Success; 2214 } 2215 2216 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2217 unsigned RegNo, 2218 uint64_t Address, 2219 const void *Decoder) { 2220 if (RegNo > 31) 2221 return MCDisassembler::Fail; 2222 2223 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2224 Inst.addOperand(MCOperand::createReg(Reg)); 2225 return MCDisassembler::Success; 2226 } 2227 2228 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2229 unsigned Offset, 2230 uint64_t Address, 2231 const void *Decoder) { 2232 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2233 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2234 return MCDisassembler::Success; 2235 } 2236 2237 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2238 unsigned Offset, 2239 uint64_t Address, 2240 const void *Decoder) { 2241 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2242 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2243 return MCDisassembler::Success; 2244 } 2245 2246 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2247 unsigned Insn, 2248 uint64_t Address, 2249 const void *Decoder) { 2250 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2251 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2252 return MCDisassembler::Success; 2253 } 2254 2255 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2256 unsigned Offset, 2257 uint64_t Address, 2258 const void *Decoder) { 2259 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2260 2261 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2262 return MCDisassembler::Success; 2263 } 2264 2265 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2266 unsigned Offset, 2267 uint64_t Address, 2268 const void *Decoder) { 2269 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2270 2271 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2272 return MCDisassembler::Success; 2273 } 2274 2275 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2276 unsigned Offset, 2277 uint64_t Address, 2278 const void *Decoder) { 2279 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2280 2281 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2282 return MCDisassembler::Success; 2283 } 2284 2285 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2286 unsigned Offset, 2287 uint64_t Address, 2288 const void *Decoder) { 2289 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2290 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2291 return MCDisassembler::Success; 2292 } 2293 2294 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2295 unsigned Offset, 2296 uint64_t Address, 2297 const void *Decoder) { 2298 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2299 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2300 return MCDisassembler::Success; 2301 } 2302 2303 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2304 unsigned Offset, 2305 uint64_t Address, 2306 const void *Decoder) { 2307 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2308 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2309 return MCDisassembler::Success; 2310 } 2311 2312 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2313 unsigned Offset, 2314 uint64_t Address, 2315 const void *Decoder) { 2316 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2317 2318 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2319 return MCDisassembler::Success; 2320 } 2321 2322 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2323 unsigned Insn, 2324 uint64_t Address, 2325 const void *Decoder) { 2326 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2327 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2328 return MCDisassembler::Success; 2329 } 2330 2331 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2332 unsigned Value, 2333 uint64_t Address, 2334 const void *Decoder) { 2335 if (Value == 0) 2336 Inst.addOperand(MCOperand::createImm(1)); 2337 else if (Value == 0x7) 2338 Inst.addOperand(MCOperand::createImm(-1)); 2339 else 2340 Inst.addOperand(MCOperand::createImm(Value << 2)); 2341 return MCDisassembler::Success; 2342 } 2343 2344 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2345 unsigned Value, 2346 uint64_t Address, 2347 const void *Decoder) { 2348 if (Value == 0x7F) 2349 Inst.addOperand(MCOperand::createImm(-1)); 2350 else 2351 Inst.addOperand(MCOperand::createImm(Value)); 2352 return MCDisassembler::Success; 2353 } 2354 2355 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2356 unsigned Value, 2357 uint64_t Address, 2358 const void *Decoder) { 2359 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2360 return MCDisassembler::Success; 2361 } 2362 2363 template <unsigned Bits, int Offset, int Scale> 2364 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2365 uint64_t Address, 2366 const void *Decoder) { 2367 Value &= ((1 << Bits) - 1); 2368 Value *= Scale; 2369 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2370 return MCDisassembler::Success; 2371 } 2372 2373 template <unsigned Bits, int Offset, int ScaleBy> 2374 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2375 uint64_t Address, 2376 const void *Decoder) { 2377 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2378 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2379 return MCDisassembler::Success; 2380 } 2381 2382 static DecodeStatus DecodeInsSize(MCInst &Inst, 2383 unsigned Insn, 2384 uint64_t Address, 2385 const void *Decoder) { 2386 // First we need to grab the pos(lsb) from MCInst. 2387 // This function only handles the 32 bit variants of ins, as dins 2388 // variants are handled differently. 2389 int Pos = Inst.getOperand(2).getImm(); 2390 int Size = (int) Insn - Pos + 1; 2391 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2392 return MCDisassembler::Success; 2393 } 2394 2395 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2396 uint64_t Address, const void *Decoder) { 2397 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2398 return MCDisassembler::Success; 2399 } 2400 2401 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2402 uint64_t Address, const void *Decoder) { 2403 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2404 return MCDisassembler::Success; 2405 } 2406 2407 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2408 uint64_t Address, const void *Decoder) { 2409 int32_t DecodedValue; 2410 switch (Insn) { 2411 case 0: DecodedValue = 256; break; 2412 case 1: DecodedValue = 257; break; 2413 case 510: DecodedValue = -258; break; 2414 case 511: DecodedValue = -257; break; 2415 default: DecodedValue = SignExtend32<9>(Insn); break; 2416 } 2417 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2418 return MCDisassembler::Success; 2419 } 2420 2421 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2422 uint64_t Address, const void *Decoder) { 2423 // Insn must be >= 0, since it is unsigned that condition is always true. 2424 assert(Insn < 16); 2425 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2426 255, 32768, 65535}; 2427 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2428 return MCDisassembler::Success; 2429 } 2430 2431 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2432 unsigned Insn, 2433 uint64_t Address, 2434 const void *Decoder) { 2435 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2436 Mips::S6, Mips::S7, Mips::FP}; 2437 unsigned RegNum; 2438 2439 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2440 2441 // Empty register lists are not allowed. 2442 if (RegLst == 0) 2443 return MCDisassembler::Fail; 2444 2445 RegNum = RegLst & 0xf; 2446 2447 // RegLst values 10-15, and 26-31 are reserved. 2448 if (RegNum > 9) 2449 return MCDisassembler::Fail; 2450 2451 for (unsigned i = 0; i < RegNum; i++) 2452 Inst.addOperand(MCOperand::createReg(Regs[i])); 2453 2454 if (RegLst & 0x10) 2455 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2456 2457 return MCDisassembler::Success; 2458 } 2459 2460 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2461 uint64_t Address, 2462 const void *Decoder) { 2463 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2464 unsigned RegLst; 2465 switch(Inst.getOpcode()) { 2466 default: 2467 RegLst = fieldFromInstruction(Insn, 4, 2); 2468 break; 2469 case Mips::LWM16_MMR6: 2470 case Mips::SWM16_MMR6: 2471 RegLst = fieldFromInstruction(Insn, 8, 2); 2472 break; 2473 } 2474 unsigned RegNum = RegLst & 0x3; 2475 2476 for (unsigned i = 0; i <= RegNum; i++) 2477 Inst.addOperand(MCOperand::createReg(Regs[i])); 2478 2479 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2480 2481 return MCDisassembler::Success; 2482 } 2483 2484 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2485 uint64_t Address, const void *Decoder) { 2486 switch (RegPair) { 2487 default: 2488 return MCDisassembler::Fail; 2489 case 0: 2490 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2491 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2492 break; 2493 case 1: 2494 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2495 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2496 break; 2497 case 2: 2498 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2499 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2500 break; 2501 case 3: 2502 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2503 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2504 break; 2505 case 4: 2506 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2507 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2508 break; 2509 case 5: 2510 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2511 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2512 break; 2513 case 6: 2514 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2515 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2516 break; 2517 case 7: 2518 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2519 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2520 break; 2521 } 2522 2523 return MCDisassembler::Success; 2524 } 2525 2526 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2527 uint64_t Address, const void *Decoder) { 2528 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2529 return MCDisassembler::Success; 2530 } 2531 2532 template <typename InsnType> 2533 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2534 uint64_t Address, 2535 const void *Decoder) { 2536 // We have: 2537 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2538 // Invalid if rt == 0 2539 // BGTZALC_MMR6 if rs == 0 && rt != 0 2540 // BLTZALC_MMR6 if rs != 0 && rs == rt 2541 // BLTUC_MMR6 if rs != 0 && rs != rt 2542 2543 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2544 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2545 InsnType Imm = 0; 2546 bool HasRs = false; 2547 bool HasRt = false; 2548 2549 if (Rt == 0) 2550 return MCDisassembler::Fail; 2551 else if (Rs == 0) { 2552 MI.setOpcode(Mips::BGTZALC_MMR6); 2553 HasRt = true; 2554 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2555 } 2556 else if (Rs == Rt) { 2557 MI.setOpcode(Mips::BLTZALC_MMR6); 2558 HasRs = true; 2559 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2560 } 2561 else { 2562 MI.setOpcode(Mips::BLTUC_MMR6); 2563 HasRs = true; 2564 HasRt = true; 2565 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2566 } 2567 2568 if (HasRs) 2569 MI.addOperand( 2570 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2571 2572 if (HasRt) 2573 MI.addOperand( 2574 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2575 2576 MI.addOperand(MCOperand::createImm(Imm)); 2577 2578 return MCDisassembler::Success; 2579 } 2580 2581 template <typename InsnType> 2582 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2583 uint64_t Address, 2584 const void *Decoder) { 2585 // We have: 2586 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2587 // Invalid if rt == 0 2588 // BLEZALC_MMR6 if rs == 0 && rt != 0 2589 // BGEZALC_MMR6 if rs == rt && rt != 0 2590 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2591 2592 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2593 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2594 InsnType Imm = 0; 2595 bool HasRs = false; 2596 2597 if (Rt == 0) 2598 return MCDisassembler::Fail; 2599 else if (Rs == 0) { 2600 MI.setOpcode(Mips::BLEZALC_MMR6); 2601 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2602 } 2603 else if (Rs == Rt) { 2604 MI.setOpcode(Mips::BGEZALC_MMR6); 2605 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2606 } 2607 else { 2608 HasRs = true; 2609 MI.setOpcode(Mips::BGEUC_MMR6); 2610 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2611 } 2612 2613 if (HasRs) 2614 MI.addOperand( 2615 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2616 MI.addOperand( 2617 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2618 2619 MI.addOperand(MCOperand::createImm(Imm)); 2620 2621 return MCDisassembler::Success; 2622 } 2623