1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 43 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 44 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 45 bool hasMips32r6() const { 46 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 47 } 48 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 49 50 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 51 52 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 53 54 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 55 56 bool hasCOP3() const { 57 // Only present in MIPS-I and MIPS-II 58 return !hasMips32() && !hasMips3(); 59 } 60 61 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 62 ArrayRef<uint8_t> Bytes, uint64_t Address, 63 raw_ostream &VStream, 64 raw_ostream &CStream) const override; 65 }; 66 67 } // end anonymous namespace 68 69 // Forward declare these because the autogenerated code will reference them. 70 // Definitions are further down. 71 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 72 unsigned RegNo, 73 uint64_t Address, 74 const void *Decoder); 75 76 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 77 unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 81 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 102 unsigned Insn, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 112 unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 136 unsigned Insn, 137 uint64_t Address, 138 const void *Decoder); 139 140 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 141 unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 146 unsigned RegNo, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 196 unsigned Offset, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 201 unsigned Offset, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 216 unsigned Offset, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 235 unsigned Offset, 236 uint64_t Address, 237 const void *Decoder); 238 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 240 // shifted left by 1 bit. 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 242 unsigned Offset, 243 uint64_t Address, 244 const void *Decoder); 245 246 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 247 // shifted left by 1 bit. 248 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 249 unsigned Offset, 250 uint64_t Address, 251 const void *Decoder); 252 253 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 254 // shifted left by 1 bit. 255 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 260 static DecodeStatus DecodeMem(MCInst &Inst, 261 unsigned Insn, 262 uint64_t Address, 263 const void *Decoder); 264 265 static DecodeStatus DecodeMemEVA(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeCacheOp(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 291 unsigned Insn, 292 uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 296 unsigned Insn, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 301 unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodeSyncI(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSynciR6(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 318 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 319 unsigned Insn, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 324 unsigned Insn, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 334 unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 354 uint64_t Address, 355 const void *Decoder); 356 357 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 370 unsigned Insn, 371 uint64_t Address, 372 const void *Decoder); 373 374 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 375 unsigned Value, 376 uint64_t Address, 377 const void *Decoder); 378 379 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 380 unsigned Value, 381 uint64_t Address, 382 const void *Decoder); 383 384 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 385 unsigned Value, 386 uint64_t Address, 387 const void *Decoder); 388 389 template <unsigned Bits, int Offset, int Scale> 390 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 391 uint64_t Address, 392 const void *Decoder); 393 394 template <unsigned Bits, int Offset> 395 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 396 uint64_t Address, 397 const void *Decoder) { 398 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 399 Decoder); 400 } 401 402 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 403 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder); 406 407 static DecodeStatus DecodeInsSize(MCInst &Inst, 408 unsigned Insn, 409 uint64_t Address, 410 const void *Decoder); 411 412 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void *Decoder); 414 415 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 416 uint64_t Address, const void *Decoder); 417 418 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 419 uint64_t Address, const void *Decoder); 420 421 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void *Decoder); 423 424 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void *Decoder); 426 427 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 428 /// handle. 429 template <typename InsnType> 430 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 431 const void *Decoder); 432 433 template <typename InsnType> 434 static DecodeStatus 435 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 436 const void *Decoder); 437 438 template <typename InsnType> 439 static DecodeStatus 440 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 441 const void *Decoder); 442 443 template <typename InsnType> 444 static DecodeStatus 445 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 446 const void *Decoder); 447 448 template <typename InsnType> 449 static DecodeStatus 450 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 451 const void *Decoder); 452 453 template <typename InsnType> 454 static DecodeStatus 455 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus 460 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 461 const void *Decoder); 462 463 template <typename InsnType> 464 static DecodeStatus 465 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 466 const void *Decoder); 467 468 template <typename InsnType> 469 static DecodeStatus 470 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 471 const void *Decoder); 472 473 template <typename InsnType> 474 static DecodeStatus 475 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 476 const void *Decoder); 477 478 template <typename InsnType> 479 static DecodeStatus 480 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 481 const void *Decoder); 482 483 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 484 uint64_t Address, 485 const void *Decoder); 486 487 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 488 uint64_t Address, 489 const void *Decoder); 490 491 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 492 uint64_t Address, 493 const void *Decoder); 494 495 namespace llvm { 496 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 497 TheMips64elTarget; 498 } 499 500 static MCDisassembler *createMipsDisassembler( 501 const Target &T, 502 const MCSubtargetInfo &STI, 503 MCContext &Ctx) { 504 return new MipsDisassembler(STI, Ctx, true); 505 } 506 507 static MCDisassembler *createMipselDisassembler( 508 const Target &T, 509 const MCSubtargetInfo &STI, 510 MCContext &Ctx) { 511 return new MipsDisassembler(STI, Ctx, false); 512 } 513 514 extern "C" void LLVMInitializeMipsDisassembler() { 515 // Register the disassembler. 516 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 517 createMipsDisassembler); 518 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 519 createMipselDisassembler); 520 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 521 createMipsDisassembler); 522 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 523 createMipselDisassembler); 524 } 525 526 #include "MipsGenDisassemblerTables.inc" 527 528 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 529 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 530 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 531 return *(RegInfo->getRegClass(RC).begin() + RegNo); 532 } 533 534 template <typename InsnType> 535 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 536 const void *Decoder) { 537 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 538 // The size of the n field depends on the element size 539 // The register class also depends on this. 540 InsnType tmp = fieldFromInstruction(insn, 17, 5); 541 unsigned NSize = 0; 542 DecodeFN RegDecoder = nullptr; 543 if ((tmp & 0x18) == 0x00) { // INSVE_B 544 NSize = 4; 545 RegDecoder = DecodeMSA128BRegisterClass; 546 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 547 NSize = 3; 548 RegDecoder = DecodeMSA128HRegisterClass; 549 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 550 NSize = 2; 551 RegDecoder = DecodeMSA128WRegisterClass; 552 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 553 NSize = 1; 554 RegDecoder = DecodeMSA128DRegisterClass; 555 } else 556 llvm_unreachable("Invalid encoding"); 557 558 assert(NSize != 0 && RegDecoder != nullptr); 559 560 // $wd 561 tmp = fieldFromInstruction(insn, 6, 5); 562 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 563 return MCDisassembler::Fail; 564 // $wd_in 565 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 566 return MCDisassembler::Fail; 567 // $n 568 tmp = fieldFromInstruction(insn, 16, NSize); 569 MI.addOperand(MCOperand::createImm(tmp)); 570 // $ws 571 tmp = fieldFromInstruction(insn, 11, 5); 572 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 573 return MCDisassembler::Fail; 574 // $n2 575 MI.addOperand(MCOperand::createImm(0)); 576 577 return MCDisassembler::Success; 578 } 579 580 template <typename InsnType> 581 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 582 uint64_t Address, 583 const void *Decoder) { 584 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 585 // (otherwise we would have matched the ADDI instruction from the earlier 586 // ISA's instead). 587 // 588 // We have: 589 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 590 // BOVC if rs >= rt 591 // BEQZALC if rs == 0 && rt != 0 592 // BEQC if rs < rt && rs != 0 593 594 InsnType Rs = fieldFromInstruction(insn, 21, 5); 595 InsnType Rt = fieldFromInstruction(insn, 16, 5); 596 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 597 bool HasRs = false; 598 599 if (Rs >= Rt) { 600 MI.setOpcode(Mips::BOVC); 601 HasRs = true; 602 } else if (Rs != 0 && Rs < Rt) { 603 MI.setOpcode(Mips::BEQC); 604 HasRs = true; 605 } else 606 MI.setOpcode(Mips::BEQZALC); 607 608 if (HasRs) 609 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 610 Rs))); 611 612 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 613 Rt))); 614 MI.addOperand(MCOperand::createImm(Imm)); 615 616 return MCDisassembler::Success; 617 } 618 619 template <typename InsnType> 620 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 621 uint64_t Address, 622 const void *Decoder) { 623 InsnType Rt = fieldFromInstruction(insn, 21, 5); 624 InsnType Rs = fieldFromInstruction(insn, 16, 5); 625 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 626 627 if (Rs >= Rt) { 628 MI.setOpcode(Mips::BOVC_MMR6); 629 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 630 Rt))); 631 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 632 Rs))); 633 } else if (Rs != 0 && Rs < Rt) { 634 MI.setOpcode(Mips::BEQC_MMR6); 635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 636 Rs))); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 638 Rt))); 639 } else { 640 MI.setOpcode(Mips::BEQZALC_MMR6); 641 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 642 Rt))); 643 } 644 645 MI.addOperand(MCOperand::createImm(Imm)); 646 647 return MCDisassembler::Success; 648 } 649 650 template <typename InsnType> 651 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 652 uint64_t Address, 653 const void *Decoder) { 654 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 655 // (otherwise we would have matched the ADDI instruction from the earlier 656 // ISA's instead). 657 // 658 // We have: 659 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 660 // BNVC if rs >= rt 661 // BNEZALC if rs == 0 && rt != 0 662 // BNEC if rs < rt && rs != 0 663 664 InsnType Rs = fieldFromInstruction(insn, 21, 5); 665 InsnType Rt = fieldFromInstruction(insn, 16, 5); 666 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 667 bool HasRs = false; 668 669 if (Rs >= Rt) { 670 MI.setOpcode(Mips::BNVC); 671 HasRs = true; 672 } else if (Rs != 0 && Rs < Rt) { 673 MI.setOpcode(Mips::BNEC); 674 HasRs = true; 675 } else 676 MI.setOpcode(Mips::BNEZALC); 677 678 if (HasRs) 679 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 680 Rs))); 681 682 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 683 Rt))); 684 MI.addOperand(MCOperand::createImm(Imm)); 685 686 return MCDisassembler::Success; 687 } 688 689 template <typename InsnType> 690 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 691 uint64_t Address, 692 const void *Decoder) { 693 InsnType Rt = fieldFromInstruction(insn, 21, 5); 694 InsnType Rs = fieldFromInstruction(insn, 16, 5); 695 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 696 697 if (Rs >= Rt) { 698 MI.setOpcode(Mips::BNVC_MMR6); 699 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 700 Rt))); 701 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 702 Rs))); 703 } else if (Rs != 0 && Rs < Rt) { 704 MI.setOpcode(Mips::BNEC_MMR6); 705 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 706 Rs))); 707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 708 Rt))); 709 } else { 710 MI.setOpcode(Mips::BNEZALC_MMR6); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rt))); 713 } 714 715 MI.addOperand(MCOperand::createImm(Imm)); 716 717 return MCDisassembler::Success; 718 } 719 720 template <typename InsnType> 721 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 722 uint64_t Address, 723 const void *Decoder) { 724 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 725 // (otherwise we would have matched the BLEZL instruction from the earlier 726 // ISA's instead). 727 // 728 // We have: 729 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 730 // Invalid if rs == 0 731 // BLEZC if rs == 0 && rt != 0 732 // BGEZC if rs == rt && rt != 0 733 // BGEC if rs != rt && rs != 0 && rt != 0 734 735 InsnType Rs = fieldFromInstruction(insn, 21, 5); 736 InsnType Rt = fieldFromInstruction(insn, 16, 5); 737 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 738 bool HasRs = false; 739 740 if (Rt == 0) 741 return MCDisassembler::Fail; 742 else if (Rs == 0) 743 MI.setOpcode(Mips::BLEZC); 744 else if (Rs == Rt) 745 MI.setOpcode(Mips::BGEZC); 746 else { 747 HasRs = true; 748 MI.setOpcode(Mips::BGEC); 749 } 750 751 if (HasRs) 752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 753 Rs))); 754 755 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 756 Rt))); 757 758 MI.addOperand(MCOperand::createImm(Imm)); 759 760 return MCDisassembler::Success; 761 } 762 763 template <typename InsnType> 764 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 765 uint64_t Address, 766 const void *Decoder) { 767 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 768 // (otherwise we would have matched the BGTZL instruction from the earlier 769 // ISA's instead). 770 // 771 // We have: 772 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 773 // Invalid if rs == 0 774 // BGTZC if rs == 0 && rt != 0 775 // BLTZC if rs == rt && rt != 0 776 // BLTC if rs != rt && rs != 0 && rt != 0 777 778 bool HasRs = false; 779 780 InsnType Rs = fieldFromInstruction(insn, 21, 5); 781 InsnType Rt = fieldFromInstruction(insn, 16, 5); 782 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 783 784 if (Rt == 0) 785 return MCDisassembler::Fail; 786 else if (Rs == 0) 787 MI.setOpcode(Mips::BGTZC); 788 else if (Rs == Rt) 789 MI.setOpcode(Mips::BLTZC); 790 else { 791 MI.setOpcode(Mips::BLTC); 792 HasRs = true; 793 } 794 795 if (HasRs) 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rs))); 798 799 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 800 Rt))); 801 802 MI.addOperand(MCOperand::createImm(Imm)); 803 804 return MCDisassembler::Success; 805 } 806 807 template <typename InsnType> 808 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 809 uint64_t Address, 810 const void *Decoder) { 811 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 812 // (otherwise we would have matched the BGTZ instruction from the earlier 813 // ISA's instead). 814 // 815 // We have: 816 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 817 // BGTZ if rt == 0 818 // BGTZALC if rs == 0 && rt != 0 819 // BLTZALC if rs != 0 && rs == rt 820 // BLTUC if rs != 0 && rs != rt 821 822 InsnType Rs = fieldFromInstruction(insn, 21, 5); 823 InsnType Rt = fieldFromInstruction(insn, 16, 5); 824 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 825 bool HasRs = false; 826 bool HasRt = false; 827 828 if (Rt == 0) { 829 MI.setOpcode(Mips::BGTZ); 830 HasRs = true; 831 } else if (Rs == 0) { 832 MI.setOpcode(Mips::BGTZALC); 833 HasRt = true; 834 } else if (Rs == Rt) { 835 MI.setOpcode(Mips::BLTZALC); 836 HasRs = true; 837 } else { 838 MI.setOpcode(Mips::BLTUC); 839 HasRs = true; 840 HasRt = true; 841 } 842 843 if (HasRs) 844 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 845 Rs))); 846 847 if (HasRt) 848 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 849 Rt))); 850 851 MI.addOperand(MCOperand::createImm(Imm)); 852 853 return MCDisassembler::Success; 854 } 855 856 template <typename InsnType> 857 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 858 uint64_t Address, 859 const void *Decoder) { 860 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 861 // (otherwise we would have matched the BLEZL instruction from the earlier 862 // ISA's instead). 863 // 864 // We have: 865 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 866 // Invalid if rs == 0 867 // BLEZALC if rs == 0 && rt != 0 868 // BGEZALC if rs == rt && rt != 0 869 // BGEUC if rs != rt && rs != 0 && rt != 0 870 871 InsnType Rs = fieldFromInstruction(insn, 21, 5); 872 InsnType Rt = fieldFromInstruction(insn, 16, 5); 873 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 874 bool HasRs = false; 875 876 if (Rt == 0) 877 return MCDisassembler::Fail; 878 else if (Rs == 0) 879 MI.setOpcode(Mips::BLEZALC); 880 else if (Rs == Rt) 881 MI.setOpcode(Mips::BGEZALC); 882 else { 883 HasRs = true; 884 MI.setOpcode(Mips::BGEUC); 885 } 886 887 if (HasRs) 888 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 889 Rs))); 890 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 891 Rt))); 892 893 MI.addOperand(MCOperand::createImm(Imm)); 894 895 return MCDisassembler::Success; 896 } 897 898 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 899 /// according to the given endianess. 900 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 901 uint64_t &Size, uint32_t &Insn, 902 bool IsBigEndian) { 903 // We want to read exactly 2 Bytes of data. 904 if (Bytes.size() < 2) { 905 Size = 0; 906 return MCDisassembler::Fail; 907 } 908 909 if (IsBigEndian) { 910 Insn = (Bytes[0] << 8) | Bytes[1]; 911 } else { 912 Insn = (Bytes[1] << 8) | Bytes[0]; 913 } 914 915 return MCDisassembler::Success; 916 } 917 918 /// Read four bytes from the ArrayRef and return 32 bit word sorted 919 /// according to the given endianess 920 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 921 uint64_t &Size, uint32_t &Insn, 922 bool IsBigEndian, bool IsMicroMips) { 923 // We want to read exactly 4 Bytes of data. 924 if (Bytes.size() < 4) { 925 Size = 0; 926 return MCDisassembler::Fail; 927 } 928 929 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 930 // always precede the low 16 bits in the instruction stream (that is, they 931 // are placed at lower addresses in the instruction stream). 932 // 933 // microMIPS byte ordering: 934 // Big-endian: 0 | 1 | 2 | 3 935 // Little-endian: 1 | 0 | 3 | 2 936 937 if (IsBigEndian) { 938 // Encoded as a big-endian 32-bit word in the stream. 939 Insn = 940 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 941 } else { 942 if (IsMicroMips) { 943 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 944 (Bytes[1] << 24); 945 } else { 946 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 947 (Bytes[3] << 24); 948 } 949 } 950 951 return MCDisassembler::Success; 952 } 953 954 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 955 ArrayRef<uint8_t> Bytes, 956 uint64_t Address, 957 raw_ostream &VStream, 958 raw_ostream &CStream) const { 959 uint32_t Insn; 960 DecodeStatus Result; 961 962 if (IsMicroMips) { 963 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 964 if (Result == MCDisassembler::Fail) 965 return MCDisassembler::Fail; 966 967 if (hasMips32r6()) { 968 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 969 // Calling the auto-generated decoder function for microMIPS32R6 970 // (and microMIPS64R6) 16-bit instructions. 971 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 972 Address, this, STI); 973 if (Result != MCDisassembler::Fail) { 974 Size = 2; 975 return Result; 976 } 977 } 978 979 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 980 // Calling the auto-generated decoder function for microMIPS 16-bit 981 // instructions. 982 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 983 this, STI); 984 if (Result != MCDisassembler::Fail) { 985 Size = 2; 986 return Result; 987 } 988 989 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 990 if (Result == MCDisassembler::Fail) 991 return MCDisassembler::Fail; 992 993 if (hasMips32r6()) { 994 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 995 // Calling the auto-generated decoder function. 996 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 997 this, STI); 998 if (Result != MCDisassembler::Fail) { 999 Size = 4; 1000 return Result; 1001 } 1002 } 1003 1004 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1005 // Calling the auto-generated decoder function. 1006 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1007 this, STI); 1008 if (Result != MCDisassembler::Fail) { 1009 Size = 4; 1010 return Result; 1011 } 1012 1013 if (hasMips32r6() && isFP64()) { 1014 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 1015 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 1016 Address, this, STI); 1017 if (Result != MCDisassembler::Fail) { 1018 Size = 4; 1019 return Result; 1020 } 1021 } 1022 1023 // This is an invalid instruction. Let the disassembler move forward by the 1024 // minimum instruction size. 1025 Size = 2; 1026 return MCDisassembler::Fail; 1027 } 1028 1029 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1030 if (Result == MCDisassembler::Fail) { 1031 Size = 4; 1032 return MCDisassembler::Fail; 1033 } 1034 1035 if (hasCOP3()) { 1036 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1037 Result = 1038 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1039 if (Result != MCDisassembler::Fail) { 1040 Size = 4; 1041 return Result; 1042 } 1043 } 1044 1045 if (hasMips32r6() && isGP64()) { 1046 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1047 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1048 Address, this, STI); 1049 if (Result != MCDisassembler::Fail) { 1050 Size = 4; 1051 return Result; 1052 } 1053 } 1054 1055 if (hasMips32r6() && isPTR64()) { 1056 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1057 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1058 Address, this, STI); 1059 if (Result != MCDisassembler::Fail) { 1060 Size = 4; 1061 return Result; 1062 } 1063 } 1064 1065 if (hasMips32r6()) { 1066 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1067 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1068 Address, this, STI); 1069 if (Result != MCDisassembler::Fail) { 1070 Size = 4; 1071 return Result; 1072 } 1073 } 1074 1075 if (hasMips2() && isPTR64()) { 1076 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1077 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1078 Address, this, STI); 1079 if (Result != MCDisassembler::Fail) { 1080 Size = 4; 1081 return Result; 1082 } 1083 } 1084 1085 if (hasCnMips()) { 1086 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1087 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1088 Address, this, STI); 1089 if (Result != MCDisassembler::Fail) { 1090 Size = 4; 1091 return Result; 1092 } 1093 } 1094 1095 if (isGP64()) { 1096 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1097 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1098 Address, this, STI); 1099 if (Result != MCDisassembler::Fail) { 1100 Size = 4; 1101 return Result; 1102 } 1103 } 1104 1105 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1106 // Calling the auto-generated decoder function. 1107 Result = 1108 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1109 if (Result != MCDisassembler::Fail) { 1110 Size = 4; 1111 return Result; 1112 } 1113 1114 Size = 4; 1115 return MCDisassembler::Fail; 1116 } 1117 1118 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1119 unsigned RegNo, 1120 uint64_t Address, 1121 const void *Decoder) { 1122 1123 return MCDisassembler::Fail; 1124 1125 } 1126 1127 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1128 unsigned RegNo, 1129 uint64_t Address, 1130 const void *Decoder) { 1131 1132 if (RegNo > 31) 1133 return MCDisassembler::Fail; 1134 1135 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1136 Inst.addOperand(MCOperand::createReg(Reg)); 1137 return MCDisassembler::Success; 1138 } 1139 1140 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1141 unsigned RegNo, 1142 uint64_t Address, 1143 const void *Decoder) { 1144 if (RegNo > 7) 1145 return MCDisassembler::Fail; 1146 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1147 Inst.addOperand(MCOperand::createReg(Reg)); 1148 return MCDisassembler::Success; 1149 } 1150 1151 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1152 unsigned RegNo, 1153 uint64_t Address, 1154 const void *Decoder) { 1155 if (RegNo > 7) 1156 return MCDisassembler::Fail; 1157 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1158 Inst.addOperand(MCOperand::createReg(Reg)); 1159 return MCDisassembler::Success; 1160 } 1161 1162 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1163 unsigned RegNo, 1164 uint64_t Address, 1165 const void *Decoder) { 1166 if (RegNo > 7) 1167 return MCDisassembler::Fail; 1168 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1169 Inst.addOperand(MCOperand::createReg(Reg)); 1170 return MCDisassembler::Success; 1171 } 1172 1173 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1174 unsigned RegNo, 1175 uint64_t Address, 1176 const void *Decoder) { 1177 if (RegNo > 31) 1178 return MCDisassembler::Fail; 1179 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1180 Inst.addOperand(MCOperand::createReg(Reg)); 1181 return MCDisassembler::Success; 1182 } 1183 1184 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1185 unsigned RegNo, 1186 uint64_t Address, 1187 const void *Decoder) { 1188 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1189 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1190 1191 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1192 } 1193 1194 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1195 unsigned RegNo, 1196 uint64_t Address, 1197 const void *Decoder) { 1198 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1199 } 1200 1201 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1202 unsigned RegNo, 1203 uint64_t Address, 1204 const void *Decoder) { 1205 if (RegNo > 31) 1206 return MCDisassembler::Fail; 1207 1208 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1209 Inst.addOperand(MCOperand::createReg(Reg)); 1210 return MCDisassembler::Success; 1211 } 1212 1213 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1214 unsigned RegNo, 1215 uint64_t Address, 1216 const void *Decoder) { 1217 if (RegNo > 31) 1218 return MCDisassembler::Fail; 1219 1220 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1221 Inst.addOperand(MCOperand::createReg(Reg)); 1222 return MCDisassembler::Success; 1223 } 1224 1225 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1226 unsigned RegNo, 1227 uint64_t Address, 1228 const void *Decoder) { 1229 if (RegNo > 31) 1230 return MCDisassembler::Fail; 1231 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1232 Inst.addOperand(MCOperand::createReg(Reg)); 1233 return MCDisassembler::Success; 1234 } 1235 1236 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1237 unsigned RegNo, 1238 uint64_t Address, 1239 const void *Decoder) { 1240 if (RegNo > 7) 1241 return MCDisassembler::Fail; 1242 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1243 Inst.addOperand(MCOperand::createReg(Reg)); 1244 return MCDisassembler::Success; 1245 } 1246 1247 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1248 uint64_t Address, 1249 const void *Decoder) { 1250 if (RegNo > 31) 1251 return MCDisassembler::Fail; 1252 1253 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1254 Inst.addOperand(MCOperand::createReg(Reg)); 1255 return MCDisassembler::Success; 1256 } 1257 1258 static DecodeStatus DecodeMem(MCInst &Inst, 1259 unsigned Insn, 1260 uint64_t Address, 1261 const void *Decoder) { 1262 int Offset = SignExtend32<16>(Insn & 0xffff); 1263 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1264 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1265 1266 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1267 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1268 1269 if (Inst.getOpcode() == Mips::SC || 1270 Inst.getOpcode() == Mips::SCD) 1271 Inst.addOperand(MCOperand::createReg(Reg)); 1272 1273 Inst.addOperand(MCOperand::createReg(Reg)); 1274 Inst.addOperand(MCOperand::createReg(Base)); 1275 Inst.addOperand(MCOperand::createImm(Offset)); 1276 1277 return MCDisassembler::Success; 1278 } 1279 1280 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1281 unsigned Insn, 1282 uint64_t Address, 1283 const void *Decoder) { 1284 int Offset = SignExtend32<9>(Insn >> 7); 1285 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1286 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1287 1288 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1289 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1290 1291 if (Inst.getOpcode() == Mips::SCE) 1292 Inst.addOperand(MCOperand::createReg(Reg)); 1293 1294 Inst.addOperand(MCOperand::createReg(Reg)); 1295 Inst.addOperand(MCOperand::createReg(Base)); 1296 Inst.addOperand(MCOperand::createImm(Offset)); 1297 1298 return MCDisassembler::Success; 1299 } 1300 1301 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1302 unsigned Insn, 1303 uint64_t Address, 1304 const void *Decoder) { 1305 int Offset = SignExtend32<9>(Insn & 0x1ff); 1306 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1307 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1308 1309 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1310 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1311 1312 Inst.addOperand(MCOperand::createReg(Reg)); 1313 Inst.addOperand(MCOperand::createReg(Base)); 1314 Inst.addOperand(MCOperand::createImm(Offset)); 1315 1316 return MCDisassembler::Success; 1317 } 1318 1319 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1320 unsigned Insn, 1321 uint64_t Address, 1322 const void *Decoder) { 1323 int Offset = SignExtend32<16>(Insn & 0xffff); 1324 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1325 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1326 1327 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1328 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1329 1330 Inst.addOperand(MCOperand::createReg(Reg)); 1331 Inst.addOperand(MCOperand::createReg(Base)); 1332 Inst.addOperand(MCOperand::createImm(Offset)); 1333 1334 return MCDisassembler::Success; 1335 } 1336 1337 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1338 unsigned Insn, 1339 uint64_t Address, 1340 const void *Decoder) { 1341 int Offset = SignExtend32<16>(Insn & 0xffff); 1342 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1343 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1344 1345 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1346 1347 Inst.addOperand(MCOperand::createReg(Base)); 1348 Inst.addOperand(MCOperand::createImm(Offset)); 1349 Inst.addOperand(MCOperand::createImm(Hint)); 1350 1351 return MCDisassembler::Success; 1352 } 1353 1354 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1355 unsigned Insn, 1356 uint64_t Address, 1357 const void *Decoder) { 1358 int Offset = SignExtend32<12>(Insn & 0xfff); 1359 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1360 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1361 1362 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1363 1364 Inst.addOperand(MCOperand::createReg(Base)); 1365 Inst.addOperand(MCOperand::createImm(Offset)); 1366 Inst.addOperand(MCOperand::createImm(Hint)); 1367 1368 return MCDisassembler::Success; 1369 } 1370 1371 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1372 unsigned Insn, 1373 uint64_t Address, 1374 const void *Decoder) { 1375 int Offset = SignExtend32<9>(Insn & 0x1ff); 1376 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1377 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1378 1379 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1380 1381 Inst.addOperand(MCOperand::createReg(Base)); 1382 Inst.addOperand(MCOperand::createImm(Offset)); 1383 Inst.addOperand(MCOperand::createImm(Hint)); 1384 1385 return MCDisassembler::Success; 1386 } 1387 1388 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1389 unsigned Insn, 1390 uint64_t Address, 1391 const void *Decoder) { 1392 int Offset = SignExtend32<9>(Insn >> 7); 1393 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1394 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1395 1396 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1397 1398 Inst.addOperand(MCOperand::createReg(Base)); 1399 Inst.addOperand(MCOperand::createImm(Offset)); 1400 Inst.addOperand(MCOperand::createImm(Hint)); 1401 1402 return MCDisassembler::Success; 1403 } 1404 1405 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1406 unsigned Insn, 1407 uint64_t Address, 1408 const void *Decoder) { 1409 int Offset = SignExtend32<9>(Insn & 0x1ff); 1410 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1411 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1412 1413 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1414 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1415 1416 Inst.addOperand(MCOperand::createReg(Reg)); 1417 Inst.addOperand(MCOperand::createReg(Base)); 1418 Inst.addOperand(MCOperand::createImm(Offset)); 1419 1420 return MCDisassembler::Success; 1421 } 1422 1423 static DecodeStatus DecodeSyncI(MCInst &Inst, 1424 unsigned Insn, 1425 uint64_t Address, 1426 const void *Decoder) { 1427 int Offset = SignExtend32<16>(Insn & 0xffff); 1428 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1429 1430 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1431 1432 Inst.addOperand(MCOperand::createReg(Base)); 1433 Inst.addOperand(MCOperand::createImm(Offset)); 1434 1435 return MCDisassembler::Success; 1436 } 1437 1438 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1439 unsigned Insn, 1440 uint64_t Address, 1441 const void *Decoder) { 1442 int Immediate = SignExtend32<16>(Insn & 0xffff); 1443 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1444 1445 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1446 1447 Inst.addOperand(MCOperand::createReg(Base)); 1448 Inst.addOperand(MCOperand::createImm(Immediate)); 1449 1450 return MCDisassembler::Success; 1451 } 1452 1453 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1454 uint64_t Address, const void *Decoder) { 1455 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1456 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1457 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1458 1459 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1460 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1461 1462 Inst.addOperand(MCOperand::createReg(Reg)); 1463 Inst.addOperand(MCOperand::createReg(Base)); 1464 1465 // The immediate field of an LD/ST instruction is scaled which means it must 1466 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1467 // data format. 1468 // .b - 1 byte 1469 // .h - 2 bytes 1470 // .w - 4 bytes 1471 // .d - 8 bytes 1472 switch(Inst.getOpcode()) 1473 { 1474 default: 1475 assert (0 && "Unexpected instruction"); 1476 return MCDisassembler::Fail; 1477 break; 1478 case Mips::LD_B: 1479 case Mips::ST_B: 1480 Inst.addOperand(MCOperand::createImm(Offset)); 1481 break; 1482 case Mips::LD_H: 1483 case Mips::ST_H: 1484 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1485 break; 1486 case Mips::LD_W: 1487 case Mips::ST_W: 1488 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1489 break; 1490 case Mips::LD_D: 1491 case Mips::ST_D: 1492 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1493 break; 1494 } 1495 1496 return MCDisassembler::Success; 1497 } 1498 1499 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1500 unsigned Insn, 1501 uint64_t Address, 1502 const void *Decoder) { 1503 unsigned Offset = Insn & 0xf; 1504 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1505 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1506 1507 switch (Inst.getOpcode()) { 1508 case Mips::LBU16_MM: 1509 case Mips::LHU16_MM: 1510 case Mips::LW16_MM: 1511 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1512 == MCDisassembler::Fail) 1513 return MCDisassembler::Fail; 1514 break; 1515 case Mips::SB16_MM: 1516 case Mips::SB16_MMR6: 1517 case Mips::SH16_MM: 1518 case Mips::SH16_MMR6: 1519 case Mips::SW16_MM: 1520 case Mips::SW16_MMR6: 1521 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1522 == MCDisassembler::Fail) 1523 return MCDisassembler::Fail; 1524 break; 1525 } 1526 1527 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1528 == MCDisassembler::Fail) 1529 return MCDisassembler::Fail; 1530 1531 switch (Inst.getOpcode()) { 1532 case Mips::LBU16_MM: 1533 if (Offset == 0xf) 1534 Inst.addOperand(MCOperand::createImm(-1)); 1535 else 1536 Inst.addOperand(MCOperand::createImm(Offset)); 1537 break; 1538 case Mips::SB16_MM: 1539 case Mips::SB16_MMR6: 1540 Inst.addOperand(MCOperand::createImm(Offset)); 1541 break; 1542 case Mips::LHU16_MM: 1543 case Mips::SH16_MM: 1544 case Mips::SH16_MMR6: 1545 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1546 break; 1547 case Mips::LW16_MM: 1548 case Mips::SW16_MM: 1549 case Mips::SW16_MMR6: 1550 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1551 break; 1552 } 1553 1554 return MCDisassembler::Success; 1555 } 1556 1557 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1558 unsigned Insn, 1559 uint64_t Address, 1560 const void *Decoder) { 1561 unsigned Offset = Insn & 0x1F; 1562 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1563 1564 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1565 1566 Inst.addOperand(MCOperand::createReg(Reg)); 1567 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1568 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1569 1570 return MCDisassembler::Success; 1571 } 1572 1573 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1574 unsigned Insn, 1575 uint64_t Address, 1576 const void *Decoder) { 1577 unsigned Offset = Insn & 0x7F; 1578 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1579 1580 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1581 1582 Inst.addOperand(MCOperand::createReg(Reg)); 1583 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1584 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1585 1586 return MCDisassembler::Success; 1587 } 1588 1589 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1590 unsigned Insn, 1591 uint64_t Address, 1592 const void *Decoder) { 1593 int Offset; 1594 switch (Inst.getOpcode()) { 1595 case Mips::LWM16_MMR6: 1596 case Mips::SWM16_MMR6: 1597 Offset = fieldFromInstruction(Insn, 4, 4); 1598 break; 1599 default: 1600 Offset = SignExtend32<4>(Insn & 0xf); 1601 break; 1602 } 1603 1604 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1605 == MCDisassembler::Fail) 1606 return MCDisassembler::Fail; 1607 1608 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1609 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1610 1611 return MCDisassembler::Success; 1612 } 1613 1614 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1615 unsigned Insn, 1616 uint64_t Address, 1617 const void *Decoder) { 1618 int Offset = SignExtend32<9>(Insn & 0x1ff); 1619 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1620 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1621 1622 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1623 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1624 1625 if (Inst.getOpcode() == Mips::SCE_MM) 1626 Inst.addOperand(MCOperand::createReg(Reg)); 1627 1628 Inst.addOperand(MCOperand::createReg(Reg)); 1629 Inst.addOperand(MCOperand::createReg(Base)); 1630 Inst.addOperand(MCOperand::createImm(Offset)); 1631 1632 return MCDisassembler::Success; 1633 } 1634 1635 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1636 unsigned Insn, 1637 uint64_t Address, 1638 const void *Decoder) { 1639 int Offset = SignExtend32<12>(Insn & 0x0fff); 1640 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1641 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1642 1643 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1644 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1645 1646 switch (Inst.getOpcode()) { 1647 case Mips::SWM32_MM: 1648 case Mips::LWM32_MM: 1649 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1650 == MCDisassembler::Fail) 1651 return MCDisassembler::Fail; 1652 Inst.addOperand(MCOperand::createReg(Base)); 1653 Inst.addOperand(MCOperand::createImm(Offset)); 1654 break; 1655 case Mips::SC_MM: 1656 Inst.addOperand(MCOperand::createReg(Reg)); 1657 // fallthrough 1658 default: 1659 Inst.addOperand(MCOperand::createReg(Reg)); 1660 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1661 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1662 Inst.addOperand(MCOperand::createReg(Reg+1)); 1663 1664 Inst.addOperand(MCOperand::createReg(Base)); 1665 Inst.addOperand(MCOperand::createImm(Offset)); 1666 } 1667 1668 return MCDisassembler::Success; 1669 } 1670 1671 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1672 unsigned Insn, 1673 uint64_t Address, 1674 const void *Decoder) { 1675 int Offset = SignExtend32<16>(Insn & 0xffff); 1676 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1677 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1678 1679 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1680 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1681 1682 Inst.addOperand(MCOperand::createReg(Reg)); 1683 Inst.addOperand(MCOperand::createReg(Base)); 1684 Inst.addOperand(MCOperand::createImm(Offset)); 1685 1686 return MCDisassembler::Success; 1687 } 1688 1689 static DecodeStatus DecodeFMem(MCInst &Inst, 1690 unsigned Insn, 1691 uint64_t Address, 1692 const void *Decoder) { 1693 int Offset = SignExtend32<16>(Insn & 0xffff); 1694 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1695 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1696 1697 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1698 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1699 1700 Inst.addOperand(MCOperand::createReg(Reg)); 1701 Inst.addOperand(MCOperand::createReg(Base)); 1702 Inst.addOperand(MCOperand::createImm(Offset)); 1703 1704 return MCDisassembler::Success; 1705 } 1706 1707 static DecodeStatus DecodeFMem2(MCInst &Inst, 1708 unsigned Insn, 1709 uint64_t Address, 1710 const void *Decoder) { 1711 int Offset = SignExtend32<16>(Insn & 0xffff); 1712 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1713 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1714 1715 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1716 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1717 1718 Inst.addOperand(MCOperand::createReg(Reg)); 1719 Inst.addOperand(MCOperand::createReg(Base)); 1720 Inst.addOperand(MCOperand::createImm(Offset)); 1721 1722 return MCDisassembler::Success; 1723 } 1724 1725 static DecodeStatus DecodeFMem3(MCInst &Inst, 1726 unsigned Insn, 1727 uint64_t Address, 1728 const void *Decoder) { 1729 int Offset = SignExtend32<16>(Insn & 0xffff); 1730 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1731 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1732 1733 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1734 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1735 1736 Inst.addOperand(MCOperand::createReg(Reg)); 1737 Inst.addOperand(MCOperand::createReg(Base)); 1738 Inst.addOperand(MCOperand::createImm(Offset)); 1739 1740 return MCDisassembler::Success; 1741 } 1742 1743 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1744 unsigned Insn, 1745 uint64_t Address, 1746 const void *Decoder) { 1747 int Offset = SignExtend32<11>(Insn & 0x07ff); 1748 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1749 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1750 1751 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1752 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1753 1754 Inst.addOperand(MCOperand::createReg(Reg)); 1755 Inst.addOperand(MCOperand::createReg(Base)); 1756 Inst.addOperand(MCOperand::createImm(Offset)); 1757 1758 return MCDisassembler::Success; 1759 } 1760 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1761 unsigned Insn, 1762 uint64_t Address, 1763 const void *Decoder) { 1764 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1765 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1766 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1767 1768 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1769 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1770 1771 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1772 Inst.addOperand(MCOperand::createReg(Rt)); 1773 } 1774 1775 Inst.addOperand(MCOperand::createReg(Rt)); 1776 Inst.addOperand(MCOperand::createReg(Base)); 1777 Inst.addOperand(MCOperand::createImm(Offset)); 1778 1779 return MCDisassembler::Success; 1780 } 1781 1782 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1783 unsigned RegNo, 1784 uint64_t Address, 1785 const void *Decoder) { 1786 // Currently only hardware register 29 is supported. 1787 if (RegNo != 29) 1788 return MCDisassembler::Fail; 1789 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1790 return MCDisassembler::Success; 1791 } 1792 1793 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1794 unsigned RegNo, 1795 uint64_t Address, 1796 const void *Decoder) { 1797 if (RegNo > 30 || RegNo %2) 1798 return MCDisassembler::Fail; 1799 1800 ; 1801 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1802 Inst.addOperand(MCOperand::createReg(Reg)); 1803 return MCDisassembler::Success; 1804 } 1805 1806 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1807 unsigned RegNo, 1808 uint64_t Address, 1809 const void *Decoder) { 1810 if (RegNo >= 4) 1811 return MCDisassembler::Fail; 1812 1813 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1814 Inst.addOperand(MCOperand::createReg(Reg)); 1815 return MCDisassembler::Success; 1816 } 1817 1818 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1819 unsigned RegNo, 1820 uint64_t Address, 1821 const void *Decoder) { 1822 if (RegNo >= 4) 1823 return MCDisassembler::Fail; 1824 1825 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1826 Inst.addOperand(MCOperand::createReg(Reg)); 1827 return MCDisassembler::Success; 1828 } 1829 1830 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1831 unsigned RegNo, 1832 uint64_t Address, 1833 const void *Decoder) { 1834 if (RegNo >= 4) 1835 return MCDisassembler::Fail; 1836 1837 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1838 Inst.addOperand(MCOperand::createReg(Reg)); 1839 return MCDisassembler::Success; 1840 } 1841 1842 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1843 unsigned RegNo, 1844 uint64_t Address, 1845 const void *Decoder) { 1846 if (RegNo > 31) 1847 return MCDisassembler::Fail; 1848 1849 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1850 Inst.addOperand(MCOperand::createReg(Reg)); 1851 return MCDisassembler::Success; 1852 } 1853 1854 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1855 unsigned RegNo, 1856 uint64_t Address, 1857 const void *Decoder) { 1858 if (RegNo > 31) 1859 return MCDisassembler::Fail; 1860 1861 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1862 Inst.addOperand(MCOperand::createReg(Reg)); 1863 return MCDisassembler::Success; 1864 } 1865 1866 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1867 unsigned RegNo, 1868 uint64_t Address, 1869 const void *Decoder) { 1870 if (RegNo > 31) 1871 return MCDisassembler::Fail; 1872 1873 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1874 Inst.addOperand(MCOperand::createReg(Reg)); 1875 return MCDisassembler::Success; 1876 } 1877 1878 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1879 unsigned RegNo, 1880 uint64_t Address, 1881 const void *Decoder) { 1882 if (RegNo > 31) 1883 return MCDisassembler::Fail; 1884 1885 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1886 Inst.addOperand(MCOperand::createReg(Reg)); 1887 return MCDisassembler::Success; 1888 } 1889 1890 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1891 unsigned RegNo, 1892 uint64_t Address, 1893 const void *Decoder) { 1894 if (RegNo > 7) 1895 return MCDisassembler::Fail; 1896 1897 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1898 Inst.addOperand(MCOperand::createReg(Reg)); 1899 return MCDisassembler::Success; 1900 } 1901 1902 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1903 unsigned RegNo, 1904 uint64_t Address, 1905 const void *Decoder) { 1906 if (RegNo > 31) 1907 return MCDisassembler::Fail; 1908 1909 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1910 Inst.addOperand(MCOperand::createReg(Reg)); 1911 return MCDisassembler::Success; 1912 } 1913 1914 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1915 unsigned RegNo, 1916 uint64_t Address, 1917 const void *Decoder) { 1918 if (RegNo > 31) 1919 return MCDisassembler::Fail; 1920 1921 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1922 Inst.addOperand(MCOperand::createReg(Reg)); 1923 return MCDisassembler::Success; 1924 } 1925 1926 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1927 unsigned Offset, 1928 uint64_t Address, 1929 const void *Decoder) { 1930 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1931 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1932 return MCDisassembler::Success; 1933 } 1934 1935 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 1936 unsigned Offset, 1937 uint64_t Address, 1938 const void *Decoder) { 1939 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 1940 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1941 return MCDisassembler::Success; 1942 } 1943 1944 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1945 unsigned Insn, 1946 uint64_t Address, 1947 const void *Decoder) { 1948 1949 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1950 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1951 return MCDisassembler::Success; 1952 } 1953 1954 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1955 unsigned Offset, 1956 uint64_t Address, 1957 const void *Decoder) { 1958 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 1959 1960 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1961 return MCDisassembler::Success; 1962 } 1963 1964 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 1965 unsigned Offset, 1966 uint64_t Address, 1967 const void *Decoder) { 1968 int32_t BranchOffset = SignExtend32<21>(Offset) << 1; 1969 1970 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1971 return MCDisassembler::Success; 1972 } 1973 1974 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1975 unsigned Offset, 1976 uint64_t Address, 1977 const void *Decoder) { 1978 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 1979 1980 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1981 return MCDisassembler::Success; 1982 } 1983 1984 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1985 unsigned Offset, 1986 uint64_t Address, 1987 const void *Decoder) { 1988 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1989 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1990 return MCDisassembler::Success; 1991 } 1992 1993 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1994 unsigned Offset, 1995 uint64_t Address, 1996 const void *Decoder) { 1997 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1998 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1999 return MCDisassembler::Success; 2000 } 2001 2002 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2003 unsigned Offset, 2004 uint64_t Address, 2005 const void *Decoder) { 2006 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 2007 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2008 return MCDisassembler::Success; 2009 } 2010 2011 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2012 unsigned Offset, 2013 uint64_t Address, 2014 const void *Decoder) { 2015 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 2016 2017 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2018 return MCDisassembler::Success; 2019 } 2020 2021 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2022 unsigned Insn, 2023 uint64_t Address, 2024 const void *Decoder) { 2025 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2026 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2027 return MCDisassembler::Success; 2028 } 2029 2030 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2031 unsigned Value, 2032 uint64_t Address, 2033 const void *Decoder) { 2034 if (Value == 0) 2035 Inst.addOperand(MCOperand::createImm(1)); 2036 else if (Value == 0x7) 2037 Inst.addOperand(MCOperand::createImm(-1)); 2038 else 2039 Inst.addOperand(MCOperand::createImm(Value << 2)); 2040 return MCDisassembler::Success; 2041 } 2042 2043 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2044 unsigned Value, 2045 uint64_t Address, 2046 const void *Decoder) { 2047 if (Value == 0x7F) 2048 Inst.addOperand(MCOperand::createImm(-1)); 2049 else 2050 Inst.addOperand(MCOperand::createImm(Value)); 2051 return MCDisassembler::Success; 2052 } 2053 2054 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2055 unsigned Value, 2056 uint64_t Address, 2057 const void *Decoder) { 2058 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2059 return MCDisassembler::Success; 2060 } 2061 2062 template <unsigned Bits, int Offset, int Scale> 2063 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2064 uint64_t Address, 2065 const void *Decoder) { 2066 Value &= ((1 << Bits) - 1); 2067 Value *= Scale; 2068 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2069 return MCDisassembler::Success; 2070 } 2071 2072 template <unsigned Bits, int Offset, int ScaleBy> 2073 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2074 uint64_t Address, 2075 const void *Decoder) { 2076 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2077 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2078 return MCDisassembler::Success; 2079 } 2080 2081 static DecodeStatus DecodeInsSize(MCInst &Inst, 2082 unsigned Insn, 2083 uint64_t Address, 2084 const void *Decoder) { 2085 // First we need to grab the pos(lsb) from MCInst. 2086 int Pos = Inst.getOperand(2).getImm(); 2087 int Size = (int) Insn - Pos + 1; 2088 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2089 return MCDisassembler::Success; 2090 } 2091 2092 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2093 uint64_t Address, const void *Decoder) { 2094 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2095 return MCDisassembler::Success; 2096 } 2097 2098 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2099 uint64_t Address, const void *Decoder) { 2100 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2101 return MCDisassembler::Success; 2102 } 2103 2104 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2105 uint64_t Address, const void *Decoder) { 2106 int32_t DecodedValue; 2107 switch (Insn) { 2108 case 0: DecodedValue = 256; break; 2109 case 1: DecodedValue = 257; break; 2110 case 510: DecodedValue = -258; break; 2111 case 511: DecodedValue = -257; break; 2112 default: DecodedValue = SignExtend32<9>(Insn); break; 2113 } 2114 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2115 return MCDisassembler::Success; 2116 } 2117 2118 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2119 uint64_t Address, const void *Decoder) { 2120 // Insn must be >= 0, since it is unsigned that condition is always true. 2121 assert(Insn < 16); 2122 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2123 255, 32768, 65535}; 2124 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2125 return MCDisassembler::Success; 2126 } 2127 2128 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2129 unsigned Insn, 2130 uint64_t Address, 2131 const void *Decoder) { 2132 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2133 Mips::S6, Mips::S7, Mips::FP}; 2134 unsigned RegNum; 2135 2136 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2137 2138 // Empty register lists are not allowed. 2139 if (RegLst == 0) 2140 return MCDisassembler::Fail; 2141 2142 RegNum = RegLst & 0xf; 2143 2144 // RegLst values 10-15, and 26-31 are reserved. 2145 if (RegNum > 9) 2146 return MCDisassembler::Fail; 2147 2148 for (unsigned i = 0; i < RegNum; i++) 2149 Inst.addOperand(MCOperand::createReg(Regs[i])); 2150 2151 if (RegLst & 0x10) 2152 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2153 2154 return MCDisassembler::Success; 2155 } 2156 2157 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2158 uint64_t Address, 2159 const void *Decoder) { 2160 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2161 unsigned RegLst; 2162 switch(Inst.getOpcode()) { 2163 default: 2164 RegLst = fieldFromInstruction(Insn, 4, 2); 2165 break; 2166 case Mips::LWM16_MMR6: 2167 case Mips::SWM16_MMR6: 2168 RegLst = fieldFromInstruction(Insn, 8, 2); 2169 break; 2170 } 2171 unsigned RegNum = RegLst & 0x3; 2172 2173 for (unsigned i = 0; i <= RegNum; i++) 2174 Inst.addOperand(MCOperand::createReg(Regs[i])); 2175 2176 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2177 2178 return MCDisassembler::Success; 2179 } 2180 2181 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2182 uint64_t Address, const void *Decoder) { 2183 2184 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2185 2186 switch (RegPair) { 2187 default: 2188 return MCDisassembler::Fail; 2189 case 0: 2190 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2191 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2192 break; 2193 case 1: 2194 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2195 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2196 break; 2197 case 2: 2198 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2199 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2200 break; 2201 case 3: 2202 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2203 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2204 break; 2205 case 4: 2206 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2207 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2208 break; 2209 case 5: 2210 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2211 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2212 break; 2213 case 6: 2214 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2215 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2216 break; 2217 case 7: 2218 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2219 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2220 break; 2221 } 2222 2223 return MCDisassembler::Success; 2224 } 2225 2226 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2227 uint64_t Address, const void *Decoder) { 2228 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2229 return MCDisassembler::Success; 2230 } 2231 2232 template <typename InsnType> 2233 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2234 uint64_t Address, 2235 const void *Decoder) { 2236 // We have: 2237 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2238 // Invalid if rt == 0 2239 // BGTZALC_MMR6 if rs == 0 && rt != 0 2240 // BLTZALC_MMR6 if rs != 0 && rs == rt 2241 // BLTUC_MMR6 if rs != 0 && rs != rt 2242 2243 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2244 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2245 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2246 bool HasRs = false; 2247 bool HasRt = false; 2248 2249 if (Rt == 0) 2250 return MCDisassembler::Fail; 2251 else if (Rs == 0) { 2252 MI.setOpcode(Mips::BGTZALC_MMR6); 2253 HasRt = true; 2254 } 2255 else if (Rs == Rt) { 2256 MI.setOpcode(Mips::BLTZALC_MMR6); 2257 HasRs = true; 2258 } 2259 else { 2260 MI.setOpcode(Mips::BLTUC_MMR6); 2261 HasRs = true; 2262 HasRt = true; 2263 } 2264 2265 if (HasRs) 2266 MI.addOperand( 2267 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2268 2269 if (HasRt) 2270 MI.addOperand( 2271 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2272 2273 MI.addOperand(MCOperand::createImm(Imm)); 2274 2275 return MCDisassembler::Success; 2276 } 2277 2278 template <typename InsnType> 2279 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2280 uint64_t Address, 2281 const void *Decoder) { 2282 // We have: 2283 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2284 // Invalid if rs == 0 2285 // BLEZALC_MMR6 if rs == 0 && rt != 0 2286 // BGEZALC_MMR6 if rs == rt && rt != 0 2287 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2288 2289 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2290 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2291 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2292 bool HasRs = false; 2293 2294 if (Rt == 0) 2295 return MCDisassembler::Fail; 2296 else if (Rs == 0) 2297 MI.setOpcode(Mips::BLEZALC_MMR6); 2298 else if (Rs == Rt) 2299 MI.setOpcode(Mips::BGEZALC_MMR6); 2300 else { 2301 HasRs = true; 2302 MI.setOpcode(Mips::BGEUC_MMR6); 2303 } 2304 2305 if (HasRs) 2306 MI.addOperand( 2307 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2308 MI.addOperand( 2309 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2310 2311 MI.addOperand(MCOperand::createImm(Imm)); 2312 2313 return MCDisassembler::Success; 2314 } 2315