1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/MipsABIFlagsSection.h" 10 #include "MCTargetDesc/MipsABIInfo.h" 11 #include "MCTargetDesc/MipsBaseInfo.h" 12 #include "MCTargetDesc/MipsMCExpr.h" 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "MipsTargetStreamer.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/APFloat.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/ADT/Triple.h" 22 #include "llvm/ADT/Twine.h" 23 #include "llvm/BinaryFormat/ELF.h" 24 #include "llvm/MC/MCContext.h" 25 #include "llvm/MC/MCExpr.h" 26 #include "llvm/MC/MCInst.h" 27 #include "llvm/MC/MCInstrDesc.h" 28 #include "llvm/MC/MCObjectFileInfo.h" 29 #include "llvm/MC/MCParser/MCAsmLexer.h" 30 #include "llvm/MC/MCParser/MCAsmParser.h" 31 #include "llvm/MC/MCParser/MCAsmParserExtension.h" 32 #include "llvm/MC/MCParser/MCAsmParserUtils.h" 33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 35 #include "llvm/MC/MCSectionELF.h" 36 #include "llvm/MC/MCStreamer.h" 37 #include "llvm/MC/MCSubtargetInfo.h" 38 #include "llvm/MC/MCSymbol.h" 39 #include "llvm/MC/MCSymbolELF.h" 40 #include "llvm/MC/MCValue.h" 41 #include "llvm/MC/SubtargetFeature.h" 42 #include "llvm/Support/Alignment.h" 43 #include "llvm/Support/Casting.h" 44 #include "llvm/Support/CommandLine.h" 45 #include "llvm/Support/Compiler.h" 46 #include "llvm/Support/Debug.h" 47 #include "llvm/Support/ErrorHandling.h" 48 #include "llvm/Support/MathExtras.h" 49 #include "llvm/Support/SMLoc.h" 50 #include "llvm/Support/SourceMgr.h" 51 #include "llvm/Support/TargetRegistry.h" 52 #include "llvm/Support/raw_ostream.h" 53 #include <algorithm> 54 #include <cassert> 55 #include <cstdint> 56 #include <memory> 57 #include <string> 58 #include <utility> 59 60 using namespace llvm; 61 62 #define DEBUG_TYPE "mips-asm-parser" 63 64 namespace llvm { 65 66 class MCInstrInfo; 67 68 } // end namespace llvm 69 70 extern cl::opt<bool> EmitJalrReloc; 71 72 namespace { 73 74 class MipsAssemblerOptions { 75 public: 76 MipsAssemblerOptions(const FeatureBitset &Features_) : Features(Features_) {} 77 78 MipsAssemblerOptions(const MipsAssemblerOptions *Opts) { 79 ATReg = Opts->getATRegIndex(); 80 Reorder = Opts->isReorder(); 81 Macro = Opts->isMacro(); 82 Features = Opts->getFeatures(); 83 } 84 85 unsigned getATRegIndex() const { return ATReg; } 86 bool setATRegIndex(unsigned Reg) { 87 if (Reg > 31) 88 return false; 89 90 ATReg = Reg; 91 return true; 92 } 93 94 bool isReorder() const { return Reorder; } 95 void setReorder() { Reorder = true; } 96 void setNoReorder() { Reorder = false; } 97 98 bool isMacro() const { return Macro; } 99 void setMacro() { Macro = true; } 100 void setNoMacro() { Macro = false; } 101 102 const FeatureBitset &getFeatures() const { return Features; } 103 void setFeatures(const FeatureBitset &Features_) { Features = Features_; } 104 105 // Set of features that are either architecture features or referenced 106 // by them (e.g.: FeatureNaN2008 implied by FeatureMips32r6). 107 // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]). 108 // The reason we need this mask is explained in the selectArch function. 109 // FIXME: Ideally we would like TableGen to generate this information. 110 static const FeatureBitset AllArchRelatedMask; 111 112 private: 113 unsigned ATReg = 1; 114 bool Reorder = true; 115 bool Macro = true; 116 FeatureBitset Features; 117 }; 118 119 } // end anonymous namespace 120 121 const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = { 122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3, 123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4, 124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5, 125 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2, 126 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6, 127 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3, 128 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips, 129 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, 130 Mips::FeatureNaN2008 131 }; 132 133 namespace { 134 135 class MipsAsmParser : public MCTargetAsmParser { 136 MipsTargetStreamer &getTargetStreamer() { 137 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 138 return static_cast<MipsTargetStreamer &>(TS); 139 } 140 141 MipsABIInfo ABI; 142 SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions; 143 MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a 144 // nullptr, which indicates that no function is currently 145 // selected. This usually happens after an '.end func' 146 // directive. 147 bool IsLittleEndian; 148 bool IsPicEnabled; 149 bool IsCpRestoreSet; 150 int CpRestoreOffset; 151 unsigned GPReg; 152 unsigned CpSaveLocation; 153 /// If true, then CpSaveLocation is a register, otherwise it's an offset. 154 bool CpSaveLocationIsRegister; 155 156 // Map of register aliases created via the .set directive. 157 StringMap<AsmToken> RegisterSets; 158 159 // Print a warning along with its fix-it message at the given range. 160 void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg, 161 SMRange Range, bool ShowColors = true); 162 163 void ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands); 164 165 #define GET_ASSEMBLER_HEADER 166 #include "MipsGenAsmMatcher.inc" 167 168 unsigned 169 checkEarlyTargetMatchPredicate(MCInst &Inst, 170 const OperandVector &Operands) override; 171 unsigned checkTargetMatchPredicate(MCInst &Inst) override; 172 173 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 174 OperandVector &Operands, MCStreamer &Out, 175 uint64_t &ErrorInfo, 176 bool MatchingInlineAsm) override; 177 178 /// Parse a register as used in CFI directives 179 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 180 181 bool parseParenSuffix(StringRef Name, OperandVector &Operands); 182 183 bool parseBracketSuffix(StringRef Name, OperandVector &Operands); 184 185 bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID); 186 187 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 188 SMLoc NameLoc, OperandVector &Operands) override; 189 190 bool ParseDirective(AsmToken DirectiveID) override; 191 192 OperandMatchResultTy parseMemOperand(OperandVector &Operands); 193 OperandMatchResultTy 194 matchAnyRegisterNameWithoutDollar(OperandVector &Operands, 195 StringRef Identifier, SMLoc S); 196 OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands, 197 const AsmToken &Token, 198 SMLoc S); 199 OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands, 200 SMLoc S); 201 OperandMatchResultTy parseAnyRegister(OperandVector &Operands); 202 OperandMatchResultTy parseImm(OperandVector &Operands); 203 OperandMatchResultTy parseJumpTarget(OperandVector &Operands); 204 OperandMatchResultTy parseInvNum(OperandVector &Operands); 205 OperandMatchResultTy parseRegisterList(OperandVector &Operands); 206 207 bool searchSymbolAlias(OperandVector &Operands); 208 209 bool parseOperand(OperandVector &, StringRef Mnemonic); 210 211 enum MacroExpanderResultTy { 212 MER_NotAMacro, 213 MER_Success, 214 MER_Fail, 215 }; 216 217 // Expands assembly pseudo instructions. 218 MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, 219 MCStreamer &Out, 220 const MCSubtargetInfo *STI); 221 222 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 223 const MCSubtargetInfo *STI); 224 225 bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg, 226 bool Is32BitImm, bool IsAddress, SMLoc IDLoc, 227 MCStreamer &Out, const MCSubtargetInfo *STI); 228 229 bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, 230 unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc, 231 MCStreamer &Out, const MCSubtargetInfo *STI); 232 233 bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym); 234 235 bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, 236 MCStreamer &Out, const MCSubtargetInfo *STI); 237 238 bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 239 const MCSubtargetInfo *STI); 240 bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 241 const MCSubtargetInfo *STI); 242 bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 243 const MCSubtargetInfo *STI); 244 bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc, 245 MCStreamer &Out, const MCSubtargetInfo *STI); 246 247 bool expandLoadAddress(unsigned DstReg, unsigned BaseReg, 248 const MCOperand &Offset, bool Is32BitAddress, 249 SMLoc IDLoc, MCStreamer &Out, 250 const MCSubtargetInfo *STI); 251 252 bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 253 const MCSubtargetInfo *STI); 254 255 void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 256 const MCSubtargetInfo *STI, bool IsLoad); 257 258 bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 259 const MCSubtargetInfo *STI); 260 261 bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 262 const MCSubtargetInfo *STI); 263 264 bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 265 const MCSubtargetInfo *STI); 266 267 bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 268 const MCSubtargetInfo *STI); 269 270 bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 271 const MCSubtargetInfo *STI, const bool IsMips64, 272 const bool Signed); 273 274 bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc, 275 MCStreamer &Out, const MCSubtargetInfo *STI); 276 277 bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out, 278 const MCSubtargetInfo *STI); 279 280 bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 281 const MCSubtargetInfo *STI); 282 283 bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 284 const MCSubtargetInfo *STI); 285 286 bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 287 const MCSubtargetInfo *STI); 288 289 bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 290 const MCSubtargetInfo *STI); 291 292 bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 293 const MCSubtargetInfo *STI); 294 295 bool expandRotation(MCInst &Inst, SMLoc IDLoc, 296 MCStreamer &Out, const MCSubtargetInfo *STI); 297 bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 298 const MCSubtargetInfo *STI); 299 bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 300 const MCSubtargetInfo *STI); 301 bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 302 const MCSubtargetInfo *STI); 303 304 bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 305 const MCSubtargetInfo *STI); 306 307 bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 308 const MCSubtargetInfo *STI); 309 310 bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 311 const MCSubtargetInfo *STI); 312 313 bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 314 const MCSubtargetInfo *STI); 315 316 bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 317 const MCSubtargetInfo *STI); 318 319 bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 320 const MCSubtargetInfo *STI, bool IsLoad); 321 322 bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 323 const MCSubtargetInfo *STI); 324 325 bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 326 const MCSubtargetInfo *STI); 327 328 bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 329 const MCSubtargetInfo *STI); 330 331 bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 332 const MCSubtargetInfo *STI); 333 334 bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 335 const MCSubtargetInfo *STI); 336 337 bool reportParseError(Twine ErrorMsg); 338 bool reportParseError(SMLoc Loc, Twine ErrorMsg); 339 340 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr); 341 342 bool isEvaluated(const MCExpr *Expr); 343 bool parseSetMips0Directive(); 344 bool parseSetArchDirective(); 345 bool parseSetFeature(uint64_t Feature); 346 bool isPicAndNotNxxAbi(); // Used by .cpload, .cprestore, and .cpsetup. 347 bool parseDirectiveCpLoad(SMLoc Loc); 348 bool parseDirectiveCpLocal(SMLoc Loc); 349 bool parseDirectiveCpRestore(SMLoc Loc); 350 bool parseDirectiveCPSetup(); 351 bool parseDirectiveCPReturn(); 352 bool parseDirectiveNaN(); 353 bool parseDirectiveSet(); 354 bool parseDirectiveOption(); 355 bool parseInsnDirective(); 356 bool parseRSectionDirective(StringRef Section); 357 bool parseSSectionDirective(StringRef Section, unsigned Type); 358 359 bool parseSetAtDirective(); 360 bool parseSetNoAtDirective(); 361 bool parseSetMacroDirective(); 362 bool parseSetNoMacroDirective(); 363 bool parseSetMsaDirective(); 364 bool parseSetNoMsaDirective(); 365 bool parseSetNoDspDirective(); 366 bool parseSetReorderDirective(); 367 bool parseSetNoReorderDirective(); 368 bool parseSetMips16Directive(); 369 bool parseSetNoMips16Directive(); 370 bool parseSetFpDirective(); 371 bool parseSetOddSPRegDirective(); 372 bool parseSetNoOddSPRegDirective(); 373 bool parseSetPopDirective(); 374 bool parseSetPushDirective(); 375 bool parseSetSoftFloatDirective(); 376 bool parseSetHardFloatDirective(); 377 bool parseSetMtDirective(); 378 bool parseSetNoMtDirective(); 379 bool parseSetNoCRCDirective(); 380 bool parseSetNoVirtDirective(); 381 bool parseSetNoGINVDirective(); 382 383 bool parseSetAssignment(); 384 385 bool parseDirectiveGpWord(); 386 bool parseDirectiveGpDWord(); 387 bool parseDirectiveDtpRelWord(); 388 bool parseDirectiveDtpRelDWord(); 389 bool parseDirectiveTpRelWord(); 390 bool parseDirectiveTpRelDWord(); 391 bool parseDirectiveModule(); 392 bool parseDirectiveModuleFP(); 393 bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI, 394 StringRef Directive); 395 396 bool parseInternalDirectiveReallowModule(); 397 398 bool eatComma(StringRef ErrorStr); 399 400 int matchCPURegisterName(StringRef Symbol); 401 402 int matchHWRegsRegisterName(StringRef Symbol); 403 404 int matchFPURegisterName(StringRef Name); 405 406 int matchFCCRegisterName(StringRef Name); 407 408 int matchACRegisterName(StringRef Name); 409 410 int matchMSA128RegisterName(StringRef Name); 411 412 int matchMSA128CtrlRegisterName(StringRef Name); 413 414 unsigned getReg(int RC, int RegNo); 415 416 /// Returns the internal register number for the current AT. Also checks if 417 /// the current AT is unavailable (set to $0) and gives an error if it is. 418 /// This should be used in pseudo-instruction expansions which need AT. 419 unsigned getATReg(SMLoc Loc); 420 421 bool canUseATReg(); 422 423 bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 424 const MCSubtargetInfo *STI); 425 426 // Helper function that checks if the value of a vector index is within the 427 // boundaries of accepted values for each RegisterKind 428 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0 429 bool validateMSAIndex(int Val, int RegKind); 430 431 // Selects a new architecture by updating the FeatureBits with the necessary 432 // info including implied dependencies. 433 // Internally, it clears all the feature bits related to *any* architecture 434 // and selects the new one using the ToggleFeature functionality of the 435 // MCSubtargetInfo object that handles implied dependencies. The reason we 436 // clear all the arch related bits manually is because ToggleFeature only 437 // clears the features that imply the feature being cleared and not the 438 // features implied by the feature being cleared. This is easier to see 439 // with an example: 440 // -------------------------------------------------- 441 // | Feature | Implies | 442 // | -------------------------------------------------| 443 // | FeatureMips1 | None | 444 // | FeatureMips2 | FeatureMips1 | 445 // | FeatureMips3 | FeatureMips2 | FeatureMipsGP64 | 446 // | FeatureMips4 | FeatureMips3 | 447 // | ... | | 448 // -------------------------------------------------- 449 // 450 // Setting Mips3 is equivalent to set: (FeatureMips3 | FeatureMips2 | 451 // FeatureMipsGP64 | FeatureMips1) 452 // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4). 453 void selectArch(StringRef ArchFeature) { 454 MCSubtargetInfo &STI = copySTI(); 455 FeatureBitset FeatureBits = STI.getFeatureBits(); 456 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; 457 STI.setFeatureBits(FeatureBits); 458 setAvailableFeatures( 459 ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature))); 460 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); 461 } 462 463 void setFeatureBits(uint64_t Feature, StringRef FeatureString) { 464 if (!(getSTI().getFeatureBits()[Feature])) { 465 MCSubtargetInfo &STI = copySTI(); 466 setAvailableFeatures( 467 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); 468 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); 469 } 470 } 471 472 void clearFeatureBits(uint64_t Feature, StringRef FeatureString) { 473 if (getSTI().getFeatureBits()[Feature]) { 474 MCSubtargetInfo &STI = copySTI(); 475 setAvailableFeatures( 476 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); 477 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); 478 } 479 } 480 481 void setModuleFeatureBits(uint64_t Feature, StringRef FeatureString) { 482 setFeatureBits(Feature, FeatureString); 483 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits()); 484 } 485 486 void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) { 487 clearFeatureBits(Feature, FeatureString); 488 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits()); 489 } 490 491 public: 492 enum MipsMatchResultTy { 493 Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY, 494 Match_RequiresDifferentOperands, 495 Match_RequiresNoZeroRegister, 496 Match_RequiresSameSrcAndDst, 497 Match_NoFCCRegisterForCurrentISA, 498 Match_NonZeroOperandForSync, 499 Match_NonZeroOperandForMTCX, 500 Match_RequiresPosSizeRange0_32, 501 Match_RequiresPosSizeRange33_64, 502 Match_RequiresPosSizeUImm6, 503 #define GET_OPERAND_DIAGNOSTIC_TYPES 504 #include "MipsGenAsmMatcher.inc" 505 #undef GET_OPERAND_DIAGNOSTIC_TYPES 506 }; 507 508 MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, 509 const MCInstrInfo &MII, const MCTargetOptions &Options) 510 : MCTargetAsmParser(Options, sti, MII), 511 ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()), 512 sti.getCPU(), Options)) { 513 MCAsmParserExtension::Initialize(parser); 514 515 parser.addAliasForDirective(".asciiz", ".asciz"); 516 parser.addAliasForDirective(".hword", ".2byte"); 517 parser.addAliasForDirective(".word", ".4byte"); 518 parser.addAliasForDirective(".dword", ".8byte"); 519 520 // Initialize the set of available features. 521 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 522 523 // Remember the initial assembler options. The user can not modify these. 524 AssemblerOptions.push_back( 525 std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits())); 526 527 // Create an assembler options environment for the user to modify. 528 AssemblerOptions.push_back( 529 std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits())); 530 531 getTargetStreamer().updateABIInfo(*this); 532 533 if (!isABI_O32() && !useOddSPReg() != 0) 534 report_fatal_error("-mno-odd-spreg requires the O32 ABI"); 535 536 CurrentFn = nullptr; 537 538 IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent(); 539 540 IsCpRestoreSet = false; 541 CpRestoreOffset = -1; 542 GPReg = ABI.GetGlobalPtr(); 543 544 const Triple &TheTriple = sti.getTargetTriple(); 545 IsLittleEndian = TheTriple.isLittleEndian(); 546 547 if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode()) 548 report_fatal_error("microMIPS64R6 is not supported", false); 549 550 if (!isABI_O32() && inMicroMipsMode()) 551 report_fatal_error("microMIPS64 is not supported", false); 552 } 553 554 /// True if all of $fcc0 - $fcc7 exist for the current ISA. 555 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); } 556 557 bool isGP64bit() const { 558 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; 559 } 560 561 bool isFP64bit() const { 562 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit]; 563 } 564 565 const MipsABIInfo &getABI() const { return ABI; } 566 bool isABI_N32() const { return ABI.IsN32(); } 567 bool isABI_N64() const { return ABI.IsN64(); } 568 bool isABI_O32() const { return ABI.IsO32(); } 569 bool isABI_FPXX() const { 570 return getSTI().getFeatureBits()[Mips::FeatureFPXX]; 571 } 572 573 bool useOddSPReg() const { 574 return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]); 575 } 576 577 bool inMicroMipsMode() const { 578 return getSTI().getFeatureBits()[Mips::FeatureMicroMips]; 579 } 580 581 bool hasMips1() const { 582 return getSTI().getFeatureBits()[Mips::FeatureMips1]; 583 } 584 585 bool hasMips2() const { 586 return getSTI().getFeatureBits()[Mips::FeatureMips2]; 587 } 588 589 bool hasMips3() const { 590 return getSTI().getFeatureBits()[Mips::FeatureMips3]; 591 } 592 593 bool hasMips4() const { 594 return getSTI().getFeatureBits()[Mips::FeatureMips4]; 595 } 596 597 bool hasMips5() const { 598 return getSTI().getFeatureBits()[Mips::FeatureMips5]; 599 } 600 601 bool hasMips32() const { 602 return getSTI().getFeatureBits()[Mips::FeatureMips32]; 603 } 604 605 bool hasMips64() const { 606 return getSTI().getFeatureBits()[Mips::FeatureMips64]; 607 } 608 609 bool hasMips32r2() const { 610 return getSTI().getFeatureBits()[Mips::FeatureMips32r2]; 611 } 612 613 bool hasMips64r2() const { 614 return getSTI().getFeatureBits()[Mips::FeatureMips64r2]; 615 } 616 617 bool hasMips32r3() const { 618 return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]); 619 } 620 621 bool hasMips64r3() const { 622 return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]); 623 } 624 625 bool hasMips32r5() const { 626 return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]); 627 } 628 629 bool hasMips64r5() const { 630 return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]); 631 } 632 633 bool hasMips32r6() const { 634 return getSTI().getFeatureBits()[Mips::FeatureMips32r6]; 635 } 636 637 bool hasMips64r6() const { 638 return getSTI().getFeatureBits()[Mips::FeatureMips64r6]; 639 } 640 641 bool hasDSP() const { 642 return getSTI().getFeatureBits()[Mips::FeatureDSP]; 643 } 644 645 bool hasDSPR2() const { 646 return getSTI().getFeatureBits()[Mips::FeatureDSPR2]; 647 } 648 649 bool hasDSPR3() const { 650 return getSTI().getFeatureBits()[Mips::FeatureDSPR3]; 651 } 652 653 bool hasMSA() const { 654 return getSTI().getFeatureBits()[Mips::FeatureMSA]; 655 } 656 657 bool hasCnMips() const { 658 return (getSTI().getFeatureBits()[Mips::FeatureCnMips]); 659 } 660 661 bool hasCnMipsP() const { 662 return (getSTI().getFeatureBits()[Mips::FeatureCnMipsP]); 663 } 664 665 bool inPicMode() { 666 return IsPicEnabled; 667 } 668 669 bool inMips16Mode() const { 670 return getSTI().getFeatureBits()[Mips::FeatureMips16]; 671 } 672 673 bool useTraps() const { 674 return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV]; 675 } 676 677 bool useSoftFloat() const { 678 return getSTI().getFeatureBits()[Mips::FeatureSoftFloat]; 679 } 680 bool hasMT() const { 681 return getSTI().getFeatureBits()[Mips::FeatureMT]; 682 } 683 684 bool hasCRC() const { 685 return getSTI().getFeatureBits()[Mips::FeatureCRC]; 686 } 687 688 bool hasVirt() const { 689 return getSTI().getFeatureBits()[Mips::FeatureVirt]; 690 } 691 692 bool hasGINV() const { 693 return getSTI().getFeatureBits()[Mips::FeatureGINV]; 694 } 695 696 /// Warn if RegIndex is the same as the current AT. 697 void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc); 698 699 void warnIfNoMacro(SMLoc Loc); 700 701 bool isLittle() const { return IsLittleEndian; } 702 703 const MCExpr *createTargetUnaryExpr(const MCExpr *E, 704 AsmToken::TokenKind OperatorToken, 705 MCContext &Ctx) override { 706 switch(OperatorToken) { 707 default: 708 llvm_unreachable("Unknown token"); 709 return nullptr; 710 case AsmToken::PercentCall16: 711 return MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, E, Ctx); 712 case AsmToken::PercentCall_Hi: 713 return MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16, E, Ctx); 714 case AsmToken::PercentCall_Lo: 715 return MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16, E, Ctx); 716 case AsmToken::PercentDtprel_Hi: 717 return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_HI, E, Ctx); 718 case AsmToken::PercentDtprel_Lo: 719 return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_LO, E, Ctx); 720 case AsmToken::PercentGot: 721 return MipsMCExpr::create(MipsMCExpr::MEK_GOT, E, Ctx); 722 case AsmToken::PercentGot_Disp: 723 return MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, E, Ctx); 724 case AsmToken::PercentGot_Hi: 725 return MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, E, Ctx); 726 case AsmToken::PercentGot_Lo: 727 return MipsMCExpr::create(MipsMCExpr::MEK_GOT_LO16, E, Ctx); 728 case AsmToken::PercentGot_Ofst: 729 return MipsMCExpr::create(MipsMCExpr::MEK_GOT_OFST, E, Ctx); 730 case AsmToken::PercentGot_Page: 731 return MipsMCExpr::create(MipsMCExpr::MEK_GOT_PAGE, E, Ctx); 732 case AsmToken::PercentGottprel: 733 return MipsMCExpr::create(MipsMCExpr::MEK_GOTTPREL, E, Ctx); 734 case AsmToken::PercentGp_Rel: 735 return MipsMCExpr::create(MipsMCExpr::MEK_GPREL, E, Ctx); 736 case AsmToken::PercentHi: 737 return MipsMCExpr::create(MipsMCExpr::MEK_HI, E, Ctx); 738 case AsmToken::PercentHigher: 739 return MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, E, Ctx); 740 case AsmToken::PercentHighest: 741 return MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, E, Ctx); 742 case AsmToken::PercentLo: 743 return MipsMCExpr::create(MipsMCExpr::MEK_LO, E, Ctx); 744 case AsmToken::PercentNeg: 745 return MipsMCExpr::create(MipsMCExpr::MEK_NEG, E, Ctx); 746 case AsmToken::PercentPcrel_Hi: 747 return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_HI16, E, Ctx); 748 case AsmToken::PercentPcrel_Lo: 749 return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_LO16, E, Ctx); 750 case AsmToken::PercentTlsgd: 751 return MipsMCExpr::create(MipsMCExpr::MEK_TLSGD, E, Ctx); 752 case AsmToken::PercentTlsldm: 753 return MipsMCExpr::create(MipsMCExpr::MEK_TLSLDM, E, Ctx); 754 case AsmToken::PercentTprel_Hi: 755 return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_HI, E, Ctx); 756 case AsmToken::PercentTprel_Lo: 757 return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_LO, E, Ctx); 758 } 759 } 760 }; 761 762 /// MipsOperand - Instances of this class represent a parsed Mips machine 763 /// instruction. 764 class MipsOperand : public MCParsedAsmOperand { 765 public: 766 /// Broad categories of register classes 767 /// The exact class is finalized by the render method. 768 enum RegKind { 769 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64bit()) 770 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and 771 /// isFP64bit()) 772 RegKind_FCC = 4, /// FCC 773 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which) 774 RegKind_MSACtrl = 16, /// MSA control registers 775 RegKind_COP2 = 32, /// COP2 776 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on 777 /// context). 778 RegKind_CCR = 128, /// CCR 779 RegKind_HWRegs = 256, /// HWRegs 780 RegKind_COP3 = 512, /// COP3 781 RegKind_COP0 = 1024, /// COP0 782 /// Potentially any (e.g. $1) 783 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 | 784 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC | 785 RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0 786 }; 787 788 private: 789 enum KindTy { 790 k_Immediate, /// An immediate (possibly involving symbol references) 791 k_Memory, /// Base + Offset Memory Address 792 k_RegisterIndex, /// A register index in one or more RegKind. 793 k_Token, /// A simple token 794 k_RegList, /// A physical register list 795 } Kind; 796 797 public: 798 MipsOperand(KindTy K, MipsAsmParser &Parser) 799 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {} 800 801 ~MipsOperand() override { 802 switch (Kind) { 803 case k_Memory: 804 delete Mem.Base; 805 break; 806 case k_RegList: 807 delete RegList.List; 808 break; 809 case k_Immediate: 810 case k_RegisterIndex: 811 case k_Token: 812 break; 813 } 814 } 815 816 private: 817 /// For diagnostics, and checking the assembler temporary 818 MipsAsmParser &AsmParser; 819 820 struct Token { 821 const char *Data; 822 unsigned Length; 823 }; 824 825 struct RegIdxOp { 826 unsigned Index; /// Index into the register class 827 RegKind Kind; /// Bitfield of the kinds it could possibly be 828 struct Token Tok; /// The input token this operand originated from. 829 const MCRegisterInfo *RegInfo; 830 }; 831 832 struct ImmOp { 833 const MCExpr *Val; 834 }; 835 836 struct MemOp { 837 MipsOperand *Base; 838 const MCExpr *Off; 839 }; 840 841 struct RegListOp { 842 SmallVector<unsigned, 10> *List; 843 }; 844 845 union { 846 struct Token Tok; 847 struct RegIdxOp RegIdx; 848 struct ImmOp Imm; 849 struct MemOp Mem; 850 struct RegListOp RegList; 851 }; 852 853 SMLoc StartLoc, EndLoc; 854 855 /// Internal constructor for register kinds 856 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str, 857 RegKind RegKind, 858 const MCRegisterInfo *RegInfo, 859 SMLoc S, SMLoc E, 860 MipsAsmParser &Parser) { 861 auto Op = std::make_unique<MipsOperand>(k_RegisterIndex, Parser); 862 Op->RegIdx.Index = Index; 863 Op->RegIdx.RegInfo = RegInfo; 864 Op->RegIdx.Kind = RegKind; 865 Op->RegIdx.Tok.Data = Str.data(); 866 Op->RegIdx.Tok.Length = Str.size(); 867 Op->StartLoc = S; 868 Op->EndLoc = E; 869 return Op; 870 } 871 872 public: 873 /// Coerce the register to GPR32 and return the real register for the current 874 /// target. 875 unsigned getGPR32Reg() const { 876 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); 877 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); 878 unsigned ClassID = Mips::GPR32RegClassID; 879 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 880 } 881 882 /// Coerce the register to GPR32 and return the real register for the current 883 /// target. 884 unsigned getGPRMM16Reg() const { 885 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); 886 unsigned ClassID = Mips::GPR32RegClassID; 887 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 888 } 889 890 /// Coerce the register to GPR64 and return the real register for the current 891 /// target. 892 unsigned getGPR64Reg() const { 893 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); 894 unsigned ClassID = Mips::GPR64RegClassID; 895 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 896 } 897 898 private: 899 /// Coerce the register to AFGR64 and return the real register for the current 900 /// target. 901 unsigned getAFGR64Reg() const { 902 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!"); 903 if (RegIdx.Index % 2 != 0) 904 AsmParser.Warning(StartLoc, "Float register should be even."); 905 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) 906 .getRegister(RegIdx.Index / 2); 907 } 908 909 /// Coerce the register to FGR64 and return the real register for the current 910 /// target. 911 unsigned getFGR64Reg() const { 912 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!"); 913 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) 914 .getRegister(RegIdx.Index); 915 } 916 917 /// Coerce the register to FGR32 and return the real register for the current 918 /// target. 919 unsigned getFGR32Reg() const { 920 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!"); 921 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) 922 .getRegister(RegIdx.Index); 923 } 924 925 /// Coerce the register to FCC and return the real register for the current 926 /// target. 927 unsigned getFCCReg() const { 928 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!"); 929 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID) 930 .getRegister(RegIdx.Index); 931 } 932 933 /// Coerce the register to MSA128 and return the real register for the current 934 /// target. 935 unsigned getMSA128Reg() const { 936 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!"); 937 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all 938 // identical 939 unsigned ClassID = Mips::MSA128BRegClassID; 940 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 941 } 942 943 /// Coerce the register to MSACtrl and return the real register for the 944 /// current target. 945 unsigned getMSACtrlReg() const { 946 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!"); 947 unsigned ClassID = Mips::MSACtrlRegClassID; 948 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 949 } 950 951 /// Coerce the register to COP0 and return the real register for the 952 /// current target. 953 unsigned getCOP0Reg() const { 954 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!"); 955 unsigned ClassID = Mips::COP0RegClassID; 956 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 957 } 958 959 /// Coerce the register to COP2 and return the real register for the 960 /// current target. 961 unsigned getCOP2Reg() const { 962 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!"); 963 unsigned ClassID = Mips::COP2RegClassID; 964 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 965 } 966 967 /// Coerce the register to COP3 and return the real register for the 968 /// current target. 969 unsigned getCOP3Reg() const { 970 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!"); 971 unsigned ClassID = Mips::COP3RegClassID; 972 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 973 } 974 975 /// Coerce the register to ACC64DSP and return the real register for the 976 /// current target. 977 unsigned getACC64DSPReg() const { 978 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!"); 979 unsigned ClassID = Mips::ACC64DSPRegClassID; 980 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 981 } 982 983 /// Coerce the register to HI32DSP and return the real register for the 984 /// current target. 985 unsigned getHI32DSPReg() const { 986 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!"); 987 unsigned ClassID = Mips::HI32DSPRegClassID; 988 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 989 } 990 991 /// Coerce the register to LO32DSP and return the real register for the 992 /// current target. 993 unsigned getLO32DSPReg() const { 994 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!"); 995 unsigned ClassID = Mips::LO32DSPRegClassID; 996 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 997 } 998 999 /// Coerce the register to CCR and return the real register for the 1000 /// current target. 1001 unsigned getCCRReg() const { 1002 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!"); 1003 unsigned ClassID = Mips::CCRRegClassID; 1004 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 1005 } 1006 1007 /// Coerce the register to HWRegs and return the real register for the 1008 /// current target. 1009 unsigned getHWRegsReg() const { 1010 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!"); 1011 unsigned ClassID = Mips::HWRegsRegClassID; 1012 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); 1013 } 1014 1015 public: 1016 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1017 // Add as immediate when possible. Null MCExpr = 0. 1018 if (!Expr) 1019 Inst.addOperand(MCOperand::createImm(0)); 1020 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1021 Inst.addOperand(MCOperand::createImm(CE->getValue())); 1022 else 1023 Inst.addOperand(MCOperand::createExpr(Expr)); 1024 } 1025 1026 void addRegOperands(MCInst &Inst, unsigned N) const { 1027 llvm_unreachable("Use a custom parser instead"); 1028 } 1029 1030 /// Render the operand to an MCInst as a GPR32 1031 /// Asserts if the wrong number of operands are requested, or the operand 1032 /// is not a k_RegisterIndex compatible with RegKind_GPR 1033 void addGPR32ZeroAsmRegOperands(MCInst &Inst, unsigned N) const { 1034 assert(N == 1 && "Invalid number of operands!"); 1035 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); 1036 } 1037 1038 void addGPR32NonZeroAsmRegOperands(MCInst &Inst, unsigned N) const { 1039 assert(N == 1 && "Invalid number of operands!"); 1040 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); 1041 } 1042 1043 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const { 1044 assert(N == 1 && "Invalid number of operands!"); 1045 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); 1046 } 1047 1048 void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const { 1049 assert(N == 1 && "Invalid number of operands!"); 1050 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1051 } 1052 1053 void addGPRMM16AsmRegZeroOperands(MCInst &Inst, unsigned N) const { 1054 assert(N == 1 && "Invalid number of operands!"); 1055 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1056 } 1057 1058 void addGPRMM16AsmRegMovePOperands(MCInst &Inst, unsigned N) const { 1059 assert(N == 1 && "Invalid number of operands!"); 1060 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1061 } 1062 1063 void addGPRMM16AsmRegMovePPairFirstOperands(MCInst &Inst, unsigned N) const { 1064 assert(N == 1 && "Invalid number of operands!"); 1065 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1066 } 1067 1068 void addGPRMM16AsmRegMovePPairSecondOperands(MCInst &Inst, 1069 unsigned N) const { 1070 assert(N == 1 && "Invalid number of operands!"); 1071 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); 1072 } 1073 1074 /// Render the operand to an MCInst as a GPR64 1075 /// Asserts if the wrong number of operands are requested, or the operand 1076 /// is not a k_RegisterIndex compatible with RegKind_GPR 1077 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const { 1078 assert(N == 1 && "Invalid number of operands!"); 1079 Inst.addOperand(MCOperand::createReg(getGPR64Reg())); 1080 } 1081 1082 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const { 1083 assert(N == 1 && "Invalid number of operands!"); 1084 Inst.addOperand(MCOperand::createReg(getAFGR64Reg())); 1085 } 1086 1087 void addStrictlyAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const { 1088 assert(N == 1 && "Invalid number of operands!"); 1089 Inst.addOperand(MCOperand::createReg(getAFGR64Reg())); 1090 } 1091 1092 void addStrictlyFGR64AsmRegOperands(MCInst &Inst, unsigned N) const { 1093 assert(N == 1 && "Invalid number of operands!"); 1094 Inst.addOperand(MCOperand::createReg(getFGR64Reg())); 1095 } 1096 1097 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const { 1098 assert(N == 1 && "Invalid number of operands!"); 1099 Inst.addOperand(MCOperand::createReg(getFGR64Reg())); 1100 } 1101 1102 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const { 1103 assert(N == 1 && "Invalid number of operands!"); 1104 Inst.addOperand(MCOperand::createReg(getFGR32Reg())); 1105 // FIXME: We ought to do this for -integrated-as without -via-file-asm too. 1106 // FIXME: This should propagate failure up to parseStatement. 1107 if (!AsmParser.useOddSPReg() && RegIdx.Index & 1) 1108 AsmParser.getParser().printError( 1109 StartLoc, "-mno-odd-spreg prohibits the use of odd FPU " 1110 "registers"); 1111 } 1112 1113 void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const { 1114 assert(N == 1 && "Invalid number of operands!"); 1115 Inst.addOperand(MCOperand::createReg(getFGR32Reg())); 1116 // FIXME: We ought to do this for -integrated-as without -via-file-asm too. 1117 if (!AsmParser.useOddSPReg() && RegIdx.Index & 1) 1118 AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU " 1119 "registers"); 1120 } 1121 1122 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const { 1123 assert(N == 1 && "Invalid number of operands!"); 1124 Inst.addOperand(MCOperand::createReg(getFCCReg())); 1125 } 1126 1127 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const { 1128 assert(N == 1 && "Invalid number of operands!"); 1129 Inst.addOperand(MCOperand::createReg(getMSA128Reg())); 1130 } 1131 1132 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const { 1133 assert(N == 1 && "Invalid number of operands!"); 1134 Inst.addOperand(MCOperand::createReg(getMSACtrlReg())); 1135 } 1136 1137 void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const { 1138 assert(N == 1 && "Invalid number of operands!"); 1139 Inst.addOperand(MCOperand::createReg(getCOP0Reg())); 1140 } 1141 1142 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const { 1143 assert(N == 1 && "Invalid number of operands!"); 1144 Inst.addOperand(MCOperand::createReg(getCOP2Reg())); 1145 } 1146 1147 void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const { 1148 assert(N == 1 && "Invalid number of operands!"); 1149 Inst.addOperand(MCOperand::createReg(getCOP3Reg())); 1150 } 1151 1152 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const { 1153 assert(N == 1 && "Invalid number of operands!"); 1154 Inst.addOperand(MCOperand::createReg(getACC64DSPReg())); 1155 } 1156 1157 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const { 1158 assert(N == 1 && "Invalid number of operands!"); 1159 Inst.addOperand(MCOperand::createReg(getHI32DSPReg())); 1160 } 1161 1162 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const { 1163 assert(N == 1 && "Invalid number of operands!"); 1164 Inst.addOperand(MCOperand::createReg(getLO32DSPReg())); 1165 } 1166 1167 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const { 1168 assert(N == 1 && "Invalid number of operands!"); 1169 Inst.addOperand(MCOperand::createReg(getCCRReg())); 1170 } 1171 1172 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const { 1173 assert(N == 1 && "Invalid number of operands!"); 1174 Inst.addOperand(MCOperand::createReg(getHWRegsReg())); 1175 } 1176 1177 template <unsigned Bits, int Offset = 0, int AdjustOffset = 0> 1178 void addConstantUImmOperands(MCInst &Inst, unsigned N) const { 1179 assert(N == 1 && "Invalid number of operands!"); 1180 uint64_t Imm = getConstantImm() - Offset; 1181 Imm &= (1ULL << Bits) - 1; 1182 Imm += Offset; 1183 Imm += AdjustOffset; 1184 Inst.addOperand(MCOperand::createImm(Imm)); 1185 } 1186 1187 template <unsigned Bits> 1188 void addSImmOperands(MCInst &Inst, unsigned N) const { 1189 if (isImm() && !isConstantImm()) { 1190 addExpr(Inst, getImm()); 1191 return; 1192 } 1193 addConstantSImmOperands<Bits, 0, 0>(Inst, N); 1194 } 1195 1196 template <unsigned Bits> 1197 void addUImmOperands(MCInst &Inst, unsigned N) const { 1198 if (isImm() && !isConstantImm()) { 1199 addExpr(Inst, getImm()); 1200 return; 1201 } 1202 addConstantUImmOperands<Bits, 0, 0>(Inst, N); 1203 } 1204 1205 template <unsigned Bits, int Offset = 0, int AdjustOffset = 0> 1206 void addConstantSImmOperands(MCInst &Inst, unsigned N) const { 1207 assert(N == 1 && "Invalid number of operands!"); 1208 int64_t Imm = getConstantImm() - Offset; 1209 Imm = SignExtend64<Bits>(Imm); 1210 Imm += Offset; 1211 Imm += AdjustOffset; 1212 Inst.addOperand(MCOperand::createImm(Imm)); 1213 } 1214 1215 void addImmOperands(MCInst &Inst, unsigned N) const { 1216 assert(N == 1 && "Invalid number of operands!"); 1217 const MCExpr *Expr = getImm(); 1218 addExpr(Inst, Expr); 1219 } 1220 1221 void addMemOperands(MCInst &Inst, unsigned N) const { 1222 assert(N == 2 && "Invalid number of operands!"); 1223 1224 Inst.addOperand(MCOperand::createReg(AsmParser.getABI().ArePtrs64bit() 1225 ? getMemBase()->getGPR64Reg() 1226 : getMemBase()->getGPR32Reg())); 1227 1228 const MCExpr *Expr = getMemOff(); 1229 addExpr(Inst, Expr); 1230 } 1231 1232 void addMicroMipsMemOperands(MCInst &Inst, unsigned N) const { 1233 assert(N == 2 && "Invalid number of operands!"); 1234 1235 Inst.addOperand(MCOperand::createReg(getMemBase()->getGPRMM16Reg())); 1236 1237 const MCExpr *Expr = getMemOff(); 1238 addExpr(Inst, Expr); 1239 } 1240 1241 void addRegListOperands(MCInst &Inst, unsigned N) const { 1242 assert(N == 1 && "Invalid number of operands!"); 1243 1244 for (auto RegNo : getRegList()) 1245 Inst.addOperand(MCOperand::createReg(RegNo)); 1246 } 1247 1248 bool isReg() const override { 1249 // As a special case until we sort out the definition of div/divu, accept 1250 // $0/$zero here so that MCK_ZERO works correctly. 1251 return isGPRAsmReg() && RegIdx.Index == 0; 1252 } 1253 1254 bool isRegIdx() const { return Kind == k_RegisterIndex; } 1255 bool isImm() const override { return Kind == k_Immediate; } 1256 1257 bool isConstantImm() const { 1258 int64_t Res; 1259 return isImm() && getImm()->evaluateAsAbsolute(Res); 1260 } 1261 1262 bool isConstantImmz() const { 1263 return isConstantImm() && getConstantImm() == 0; 1264 } 1265 1266 template <unsigned Bits, int Offset = 0> bool isConstantUImm() const { 1267 return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset); 1268 } 1269 1270 template <unsigned Bits> bool isSImm() const { 1271 return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm(); 1272 } 1273 1274 template <unsigned Bits> bool isUImm() const { 1275 return isConstantImm() ? isUInt<Bits>(getConstantImm()) : isImm(); 1276 } 1277 1278 template <unsigned Bits> bool isAnyImm() const { 1279 return isConstantImm() ? (isInt<Bits>(getConstantImm()) || 1280 isUInt<Bits>(getConstantImm())) 1281 : isImm(); 1282 } 1283 1284 template <unsigned Bits, int Offset = 0> bool isConstantSImm() const { 1285 return isConstantImm() && isInt<Bits>(getConstantImm() - Offset); 1286 } 1287 1288 template <unsigned Bottom, unsigned Top> bool isConstantUImmRange() const { 1289 return isConstantImm() && getConstantImm() >= Bottom && 1290 getConstantImm() <= Top; 1291 } 1292 1293 bool isToken() const override { 1294 // Note: It's not possible to pretend that other operand kinds are tokens. 1295 // The matcher emitter checks tokens first. 1296 return Kind == k_Token; 1297 } 1298 1299 bool isMem() const override { return Kind == k_Memory; } 1300 1301 bool isConstantMemOff() const { 1302 return isMem() && isa<MCConstantExpr>(getMemOff()); 1303 } 1304 1305 // Allow relocation operators. 1306 // FIXME: This predicate and others need to look through binary expressions 1307 // and determine whether a Value is a constant or not. 1308 template <unsigned Bits, unsigned ShiftAmount = 0> 1309 bool isMemWithSimmOffset() const { 1310 if (!isMem()) 1311 return false; 1312 if (!getMemBase()->isGPRAsmReg()) 1313 return false; 1314 if (isa<MCTargetExpr>(getMemOff()) || 1315 (isConstantMemOff() && 1316 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) 1317 return true; 1318 MCValue Res; 1319 bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr); 1320 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); 1321 } 1322 1323 bool isMemWithPtrSizeOffset() const { 1324 if (!isMem()) 1325 return false; 1326 if (!getMemBase()->isGPRAsmReg()) 1327 return false; 1328 const unsigned PtrBits = AsmParser.getABI().ArePtrs64bit() ? 64 : 32; 1329 if (isa<MCTargetExpr>(getMemOff()) || 1330 (isConstantMemOff() && isIntN(PtrBits, getConstantMemOff()))) 1331 return true; 1332 MCValue Res; 1333 bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr); 1334 return IsReloc && isIntN(PtrBits, Res.getConstant()); 1335 } 1336 1337 bool isMemWithGRPMM16Base() const { 1338 return isMem() && getMemBase()->isMM16AsmReg(); 1339 } 1340 1341 template <unsigned Bits> bool isMemWithUimmOffsetSP() const { 1342 return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff()) 1343 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP); 1344 } 1345 1346 template <unsigned Bits> bool isMemWithUimmWordAlignedOffsetSP() const { 1347 return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff()) 1348 && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx() 1349 && (getMemBase()->getGPR32Reg() == Mips::SP); 1350 } 1351 1352 template <unsigned Bits> bool isMemWithSimmWordAlignedOffsetGP() const { 1353 return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff()) 1354 && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx() 1355 && (getMemBase()->getGPR32Reg() == Mips::GP); 1356 } 1357 1358 template <unsigned Bits, unsigned ShiftLeftAmount> 1359 bool isScaledUImm() const { 1360 return isConstantImm() && 1361 isShiftedUInt<Bits, ShiftLeftAmount>(getConstantImm()); 1362 } 1363 1364 template <unsigned Bits, unsigned ShiftLeftAmount> 1365 bool isScaledSImm() const { 1366 if (isConstantImm() && 1367 isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) 1368 return true; 1369 // Operand can also be a symbol or symbol plus 1370 // offset in case of relocations. 1371 if (Kind != k_Immediate) 1372 return false; 1373 MCValue Res; 1374 bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr); 1375 return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant()); 1376 } 1377 1378 bool isRegList16() const { 1379 if (!isRegList()) 1380 return false; 1381 1382 int Size = RegList.List->size(); 1383 if (Size < 2 || Size > 5) 1384 return false; 1385 1386 unsigned R0 = RegList.List->front(); 1387 unsigned R1 = RegList.List->back(); 1388 if (!((R0 == Mips::S0 && R1 == Mips::RA) || 1389 (R0 == Mips::S0_64 && R1 == Mips::RA_64))) 1390 return false; 1391 1392 int PrevReg = *RegList.List->begin(); 1393 for (int i = 1; i < Size - 1; i++) { 1394 int Reg = (*(RegList.List))[i]; 1395 if ( Reg != PrevReg + 1) 1396 return false; 1397 PrevReg = Reg; 1398 } 1399 1400 return true; 1401 } 1402 1403 bool isInvNum() const { return Kind == k_Immediate; } 1404 1405 bool isLSAImm() const { 1406 if (!isConstantImm()) 1407 return false; 1408 int64_t Val = getConstantImm(); 1409 return 1 <= Val && Val <= 4; 1410 } 1411 1412 bool isRegList() const { return Kind == k_RegList; } 1413 1414 StringRef getToken() const { 1415 assert(Kind == k_Token && "Invalid access!"); 1416 return StringRef(Tok.Data, Tok.Length); 1417 } 1418 1419 unsigned getReg() const override { 1420 // As a special case until we sort out the definition of div/divu, accept 1421 // $0/$zero here so that MCK_ZERO works correctly. 1422 if (Kind == k_RegisterIndex && RegIdx.Index == 0 && 1423 RegIdx.Kind & RegKind_GPR) 1424 return getGPR32Reg(); // FIXME: GPR64 too 1425 1426 llvm_unreachable("Invalid access!"); 1427 return 0; 1428 } 1429 1430 const MCExpr *getImm() const { 1431 assert((Kind == k_Immediate) && "Invalid access!"); 1432 return Imm.Val; 1433 } 1434 1435 int64_t getConstantImm() const { 1436 const MCExpr *Val = getImm(); 1437 int64_t Value = 0; 1438 (void)Val->evaluateAsAbsolute(Value); 1439 return Value; 1440 } 1441 1442 MipsOperand *getMemBase() const { 1443 assert((Kind == k_Memory) && "Invalid access!"); 1444 return Mem.Base; 1445 } 1446 1447 const MCExpr *getMemOff() const { 1448 assert((Kind == k_Memory) && "Invalid access!"); 1449 return Mem.Off; 1450 } 1451 1452 int64_t getConstantMemOff() const { 1453 return static_cast<const MCConstantExpr *>(getMemOff())->getValue(); 1454 } 1455 1456 const SmallVectorImpl<unsigned> &getRegList() const { 1457 assert((Kind == k_RegList) && "Invalid access!"); 1458 return *(RegList.List); 1459 } 1460 1461 static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S, 1462 MipsAsmParser &Parser) { 1463 auto Op = std::make_unique<MipsOperand>(k_Token, Parser); 1464 Op->Tok.Data = Str.data(); 1465 Op->Tok.Length = Str.size(); 1466 Op->StartLoc = S; 1467 Op->EndLoc = S; 1468 return Op; 1469 } 1470 1471 /// Create a numeric register (e.g. $1). The exact register remains 1472 /// unresolved until an instruction successfully matches 1473 static std::unique_ptr<MipsOperand> 1474 createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1475 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1476 LLVM_DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n"); 1477 return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser); 1478 } 1479 1480 /// Create a register that is definitely a GPR. 1481 /// This is typically only used for named registers such as $gp. 1482 static std::unique_ptr<MipsOperand> 1483 createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1484 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1485 return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser); 1486 } 1487 1488 /// Create a register that is definitely a FGR. 1489 /// This is typically only used for named registers such as $f0. 1490 static std::unique_ptr<MipsOperand> 1491 createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1492 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1493 return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser); 1494 } 1495 1496 /// Create a register that is definitely a HWReg. 1497 /// This is typically only used for named registers such as $hwr_cpunum. 1498 static std::unique_ptr<MipsOperand> 1499 createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1500 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1501 return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser); 1502 } 1503 1504 /// Create a register that is definitely an FCC. 1505 /// This is typically only used for named registers such as $fcc0. 1506 static std::unique_ptr<MipsOperand> 1507 createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1508 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1509 return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser); 1510 } 1511 1512 /// Create a register that is definitely an ACC. 1513 /// This is typically only used for named registers such as $ac0. 1514 static std::unique_ptr<MipsOperand> 1515 createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1516 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1517 return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser); 1518 } 1519 1520 /// Create a register that is definitely an MSA128. 1521 /// This is typically only used for named registers such as $w0. 1522 static std::unique_ptr<MipsOperand> 1523 createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1524 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1525 return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser); 1526 } 1527 1528 /// Create a register that is definitely an MSACtrl. 1529 /// This is typically only used for named registers such as $msaaccess. 1530 static std::unique_ptr<MipsOperand> 1531 createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, 1532 SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1533 return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser); 1534 } 1535 1536 static std::unique_ptr<MipsOperand> 1537 CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) { 1538 auto Op = std::make_unique<MipsOperand>(k_Immediate, Parser); 1539 Op->Imm.Val = Val; 1540 Op->StartLoc = S; 1541 Op->EndLoc = E; 1542 return Op; 1543 } 1544 1545 static std::unique_ptr<MipsOperand> 1546 CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S, 1547 SMLoc E, MipsAsmParser &Parser) { 1548 auto Op = std::make_unique<MipsOperand>(k_Memory, Parser); 1549 Op->Mem.Base = Base.release(); 1550 Op->Mem.Off = Off; 1551 Op->StartLoc = S; 1552 Op->EndLoc = E; 1553 return Op; 1554 } 1555 1556 static std::unique_ptr<MipsOperand> 1557 CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, 1558 MipsAsmParser &Parser) { 1559 assert(Regs.size() > 0 && "Empty list not allowed"); 1560 1561 auto Op = std::make_unique<MipsOperand>(k_RegList, Parser); 1562 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end()); 1563 Op->StartLoc = StartLoc; 1564 Op->EndLoc = EndLoc; 1565 return Op; 1566 } 1567 1568 bool isGPRZeroAsmReg() const { 1569 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index == 0; 1570 } 1571 1572 bool isGPRNonZeroAsmReg() const { 1573 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index > 0 && 1574 RegIdx.Index <= 31; 1575 } 1576 1577 bool isGPRAsmReg() const { 1578 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31; 1579 } 1580 1581 bool isMM16AsmReg() const { 1582 if (!(isRegIdx() && RegIdx.Kind)) 1583 return false; 1584 return ((RegIdx.Index >= 2 && RegIdx.Index <= 7) 1585 || RegIdx.Index == 16 || RegIdx.Index == 17); 1586 1587 } 1588 bool isMM16AsmRegZero() const { 1589 if (!(isRegIdx() && RegIdx.Kind)) 1590 return false; 1591 return (RegIdx.Index == 0 || 1592 (RegIdx.Index >= 2 && RegIdx.Index <= 7) || 1593 RegIdx.Index == 17); 1594 } 1595 1596 bool isMM16AsmRegMoveP() const { 1597 if (!(isRegIdx() && RegIdx.Kind)) 1598 return false; 1599 return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) || 1600 (RegIdx.Index >= 16 && RegIdx.Index <= 20)); 1601 } 1602 1603 bool isMM16AsmRegMovePPairFirst() const { 1604 if (!(isRegIdx() && RegIdx.Kind)) 1605 return false; 1606 return RegIdx.Index >= 4 && RegIdx.Index <= 6; 1607 } 1608 1609 bool isMM16AsmRegMovePPairSecond() const { 1610 if (!(isRegIdx() && RegIdx.Kind)) 1611 return false; 1612 return (RegIdx.Index == 21 || RegIdx.Index == 22 || 1613 (RegIdx.Index >= 5 && RegIdx.Index <= 7)); 1614 } 1615 1616 bool isFGRAsmReg() const { 1617 // AFGR64 is $0-$15 but we handle this in getAFGR64() 1618 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31; 1619 } 1620 1621 bool isStrictlyFGRAsmReg() const { 1622 // AFGR64 is $0-$15 but we handle this in getAFGR64() 1623 return isRegIdx() && RegIdx.Kind == RegKind_FGR && RegIdx.Index <= 31; 1624 } 1625 1626 bool isHWRegsAsmReg() const { 1627 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31; 1628 } 1629 1630 bool isCCRAsmReg() const { 1631 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31; 1632 } 1633 1634 bool isFCCAsmReg() const { 1635 if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC)) 1636 return false; 1637 return RegIdx.Index <= 7; 1638 } 1639 1640 bool isACCAsmReg() const { 1641 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3; 1642 } 1643 1644 bool isCOP0AsmReg() const { 1645 return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31; 1646 } 1647 1648 bool isCOP2AsmReg() const { 1649 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31; 1650 } 1651 1652 bool isCOP3AsmReg() const { 1653 return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31; 1654 } 1655 1656 bool isMSA128AsmReg() const { 1657 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31; 1658 } 1659 1660 bool isMSACtrlAsmReg() const { 1661 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7; 1662 } 1663 1664 /// getStartLoc - Get the location of the first token of this operand. 1665 SMLoc getStartLoc() const override { return StartLoc; } 1666 /// getEndLoc - Get the location of the last token of this operand. 1667 SMLoc getEndLoc() const override { return EndLoc; } 1668 1669 void print(raw_ostream &OS) const override { 1670 switch (Kind) { 1671 case k_Immediate: 1672 OS << "Imm<"; 1673 OS << *Imm.Val; 1674 OS << ">"; 1675 break; 1676 case k_Memory: 1677 OS << "Mem<"; 1678 Mem.Base->print(OS); 1679 OS << ", "; 1680 OS << *Mem.Off; 1681 OS << ">"; 1682 break; 1683 case k_RegisterIndex: 1684 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", " 1685 << StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">"; 1686 break; 1687 case k_Token: 1688 OS << getToken(); 1689 break; 1690 case k_RegList: 1691 OS << "RegList< "; 1692 for (auto Reg : (*RegList.List)) 1693 OS << Reg << " "; 1694 OS << ">"; 1695 break; 1696 } 1697 } 1698 1699 bool isValidForTie(const MipsOperand &Other) const { 1700 if (Kind != Other.Kind) 1701 return false; 1702 1703 switch (Kind) { 1704 default: 1705 llvm_unreachable("Unexpected kind"); 1706 return false; 1707 case k_RegisterIndex: { 1708 StringRef Token(RegIdx.Tok.Data, RegIdx.Tok.Length); 1709 StringRef OtherToken(Other.RegIdx.Tok.Data, Other.RegIdx.Tok.Length); 1710 return Token == OtherToken; 1711 } 1712 } 1713 } 1714 }; // class MipsOperand 1715 1716 } // end anonymous namespace 1717 1718 namespace llvm { 1719 1720 extern const MCInstrDesc MipsInsts[]; 1721 1722 } // end namespace llvm 1723 1724 static const MCInstrDesc &getInstDesc(unsigned Opcode) { 1725 return MipsInsts[Opcode]; 1726 } 1727 1728 static bool hasShortDelaySlot(MCInst &Inst) { 1729 switch (Inst.getOpcode()) { 1730 case Mips::BEQ_MM: 1731 case Mips::BNE_MM: 1732 case Mips::BLTZ_MM: 1733 case Mips::BGEZ_MM: 1734 case Mips::BLEZ_MM: 1735 case Mips::BGTZ_MM: 1736 case Mips::JRC16_MM: 1737 case Mips::JALS_MM: 1738 case Mips::JALRS_MM: 1739 case Mips::JALRS16_MM: 1740 case Mips::BGEZALS_MM: 1741 case Mips::BLTZALS_MM: 1742 return true; 1743 case Mips::J_MM: 1744 return !Inst.getOperand(0).isReg(); 1745 default: 1746 return false; 1747 } 1748 } 1749 1750 static const MCSymbol *getSingleMCSymbol(const MCExpr *Expr) { 1751 if (const MCSymbolRefExpr *SRExpr = dyn_cast<MCSymbolRefExpr>(Expr)) { 1752 return &SRExpr->getSymbol(); 1753 } 1754 1755 if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr)) { 1756 const MCSymbol *LHSSym = getSingleMCSymbol(BExpr->getLHS()); 1757 const MCSymbol *RHSSym = getSingleMCSymbol(BExpr->getRHS()); 1758 1759 if (LHSSym) 1760 return LHSSym; 1761 1762 if (RHSSym) 1763 return RHSSym; 1764 1765 return nullptr; 1766 } 1767 1768 if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr)) 1769 return getSingleMCSymbol(UExpr->getSubExpr()); 1770 1771 return nullptr; 1772 } 1773 1774 static unsigned countMCSymbolRefExpr(const MCExpr *Expr) { 1775 if (isa<MCSymbolRefExpr>(Expr)) 1776 return 1; 1777 1778 if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr)) 1779 return countMCSymbolRefExpr(BExpr->getLHS()) + 1780 countMCSymbolRefExpr(BExpr->getRHS()); 1781 1782 if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr)) 1783 return countMCSymbolRefExpr(UExpr->getSubExpr()); 1784 1785 return 0; 1786 } 1787 1788 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, 1789 MCStreamer &Out, 1790 const MCSubtargetInfo *STI) { 1791 MipsTargetStreamer &TOut = getTargetStreamer(); 1792 const unsigned Opcode = Inst.getOpcode(); 1793 const MCInstrDesc &MCID = getInstDesc(Opcode); 1794 bool ExpandedJalSym = false; 1795 1796 Inst.setLoc(IDLoc); 1797 1798 if (MCID.isBranch() || MCID.isCall()) { 1799 MCOperand Offset; 1800 1801 switch (Opcode) { 1802 default: 1803 break; 1804 case Mips::BBIT0: 1805 case Mips::BBIT032: 1806 case Mips::BBIT1: 1807 case Mips::BBIT132: 1808 assert(hasCnMips() && "instruction only valid for octeon cpus"); 1809 LLVM_FALLTHROUGH; 1810 1811 case Mips::BEQ: 1812 case Mips::BNE: 1813 case Mips::BEQ_MM: 1814 case Mips::BNE_MM: 1815 assert(MCID.getNumOperands() == 3 && "unexpected number of operands"); 1816 Offset = Inst.getOperand(2); 1817 if (!Offset.isImm()) 1818 break; // We'll deal with this situation later on when applying fixups. 1819 if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm())) 1820 return Error(IDLoc, "branch target out of range"); 1821 if (offsetToAlignment(Offset.getImm(), 1822 (inMicroMipsMode() ? Align(2) : Align(4)))) 1823 return Error(IDLoc, "branch to misaligned address"); 1824 break; 1825 case Mips::BGEZ: 1826 case Mips::BGTZ: 1827 case Mips::BLEZ: 1828 case Mips::BLTZ: 1829 case Mips::BGEZAL: 1830 case Mips::BLTZAL: 1831 case Mips::BC1F: 1832 case Mips::BC1T: 1833 case Mips::BGEZ_MM: 1834 case Mips::BGTZ_MM: 1835 case Mips::BLEZ_MM: 1836 case Mips::BLTZ_MM: 1837 case Mips::BGEZAL_MM: 1838 case Mips::BLTZAL_MM: 1839 case Mips::BC1F_MM: 1840 case Mips::BC1T_MM: 1841 case Mips::BC1EQZC_MMR6: 1842 case Mips::BC1NEZC_MMR6: 1843 case Mips::BC2EQZC_MMR6: 1844 case Mips::BC2NEZC_MMR6: 1845 assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); 1846 Offset = Inst.getOperand(1); 1847 if (!Offset.isImm()) 1848 break; // We'll deal with this situation later on when applying fixups. 1849 if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm())) 1850 return Error(IDLoc, "branch target out of range"); 1851 if (offsetToAlignment(Offset.getImm(), 1852 (inMicroMipsMode() ? Align(2) : Align(4)))) 1853 return Error(IDLoc, "branch to misaligned address"); 1854 break; 1855 case Mips::BGEC: case Mips::BGEC_MMR6: 1856 case Mips::BLTC: case Mips::BLTC_MMR6: 1857 case Mips::BGEUC: case Mips::BGEUC_MMR6: 1858 case Mips::BLTUC: case Mips::BLTUC_MMR6: 1859 case Mips::BEQC: case Mips::BEQC_MMR6: 1860 case Mips::BNEC: case Mips::BNEC_MMR6: 1861 assert(MCID.getNumOperands() == 3 && "unexpected number of operands"); 1862 Offset = Inst.getOperand(2); 1863 if (!Offset.isImm()) 1864 break; // We'll deal with this situation later on when applying fixups. 1865 if (!isIntN(18, Offset.getImm())) 1866 return Error(IDLoc, "branch target out of range"); 1867 if (offsetToAlignment(Offset.getImm(), Align(4))) 1868 return Error(IDLoc, "branch to misaligned address"); 1869 break; 1870 case Mips::BLEZC: case Mips::BLEZC_MMR6: 1871 case Mips::BGEZC: case Mips::BGEZC_MMR6: 1872 case Mips::BGTZC: case Mips::BGTZC_MMR6: 1873 case Mips::BLTZC: case Mips::BLTZC_MMR6: 1874 assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); 1875 Offset = Inst.getOperand(1); 1876 if (!Offset.isImm()) 1877 break; // We'll deal with this situation later on when applying fixups. 1878 if (!isIntN(18, Offset.getImm())) 1879 return Error(IDLoc, "branch target out of range"); 1880 if (offsetToAlignment(Offset.getImm(), Align(4))) 1881 return Error(IDLoc, "branch to misaligned address"); 1882 break; 1883 case Mips::BEQZC: case Mips::BEQZC_MMR6: 1884 case Mips::BNEZC: case Mips::BNEZC_MMR6: 1885 assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); 1886 Offset = Inst.getOperand(1); 1887 if (!Offset.isImm()) 1888 break; // We'll deal with this situation later on when applying fixups. 1889 if (!isIntN(23, Offset.getImm())) 1890 return Error(IDLoc, "branch target out of range"); 1891 if (offsetToAlignment(Offset.getImm(), Align(4))) 1892 return Error(IDLoc, "branch to misaligned address"); 1893 break; 1894 case Mips::BEQZ16_MM: 1895 case Mips::BEQZC16_MMR6: 1896 case Mips::BNEZ16_MM: 1897 case Mips::BNEZC16_MMR6: 1898 assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); 1899 Offset = Inst.getOperand(1); 1900 if (!Offset.isImm()) 1901 break; // We'll deal with this situation later on when applying fixups. 1902 if (!isInt<8>(Offset.getImm())) 1903 return Error(IDLoc, "branch target out of range"); 1904 if (offsetToAlignment(Offset.getImm(), Align(2))) 1905 return Error(IDLoc, "branch to misaligned address"); 1906 break; 1907 } 1908 } 1909 1910 // SSNOP is deprecated on MIPS32r6/MIPS64r6 1911 // We still accept it but it is a normal nop. 1912 if (hasMips32r6() && Opcode == Mips::SSNOP) { 1913 std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; 1914 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a " 1915 "nop instruction"); 1916 } 1917 1918 if (hasCnMips()) { 1919 MCOperand Opnd; 1920 int Imm; 1921 1922 switch (Opcode) { 1923 default: 1924 break; 1925 1926 case Mips::BBIT0: 1927 case Mips::BBIT032: 1928 case Mips::BBIT1: 1929 case Mips::BBIT132: 1930 assert(MCID.getNumOperands() == 3 && "unexpected number of operands"); 1931 // The offset is handled above 1932 Opnd = Inst.getOperand(1); 1933 if (!Opnd.isImm()) 1934 return Error(IDLoc, "expected immediate operand kind"); 1935 Imm = Opnd.getImm(); 1936 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 || 1937 Opcode == Mips::BBIT1 ? 63 : 31)) 1938 return Error(IDLoc, "immediate operand value out of range"); 1939 if (Imm > 31) { 1940 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032 1941 : Mips::BBIT132); 1942 Inst.getOperand(1).setImm(Imm - 32); 1943 } 1944 break; 1945 1946 case Mips::SEQi: 1947 case Mips::SNEi: 1948 assert(MCID.getNumOperands() == 3 && "unexpected number of operands"); 1949 Opnd = Inst.getOperand(2); 1950 if (!Opnd.isImm()) 1951 return Error(IDLoc, "expected immediate operand kind"); 1952 Imm = Opnd.getImm(); 1953 if (!isInt<10>(Imm)) 1954 return Error(IDLoc, "immediate operand value out of range"); 1955 break; 1956 } 1957 } 1958 1959 // Warn on division by zero. We're checking here as all instructions get 1960 // processed here, not just the macros that need expansion. 1961 // 1962 // The MIPS backend models most of the divison instructions and macros as 1963 // three operand instructions. The pre-R6 divide instructions however have 1964 // two operands and explicitly define HI/LO as part of the instruction, 1965 // not in the operands. 1966 unsigned FirstOp = 1; 1967 unsigned SecondOp = 2; 1968 switch (Opcode) { 1969 default: 1970 break; 1971 case Mips::SDivIMacro: 1972 case Mips::UDivIMacro: 1973 case Mips::DSDivIMacro: 1974 case Mips::DUDivIMacro: 1975 if (Inst.getOperand(2).getImm() == 0) { 1976 if (Inst.getOperand(1).getReg() == Mips::ZERO || 1977 Inst.getOperand(1).getReg() == Mips::ZERO_64) 1978 Warning(IDLoc, "dividing zero by zero"); 1979 else 1980 Warning(IDLoc, "division by zero"); 1981 } 1982 break; 1983 case Mips::DSDIV: 1984 case Mips::SDIV: 1985 case Mips::UDIV: 1986 case Mips::DUDIV: 1987 case Mips::UDIV_MM: 1988 case Mips::SDIV_MM: 1989 FirstOp = 0; 1990 SecondOp = 1; 1991 LLVM_FALLTHROUGH; 1992 case Mips::SDivMacro: 1993 case Mips::DSDivMacro: 1994 case Mips::UDivMacro: 1995 case Mips::DUDivMacro: 1996 case Mips::DIV: 1997 case Mips::DIVU: 1998 case Mips::DDIV: 1999 case Mips::DDIVU: 2000 case Mips::DIVU_MMR6: 2001 case Mips::DIV_MMR6: 2002 if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO || 2003 Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) { 2004 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO || 2005 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64) 2006 Warning(IDLoc, "dividing zero by zero"); 2007 else 2008 Warning(IDLoc, "division by zero"); 2009 } 2010 break; 2011 } 2012 2013 // For PIC code convert unconditional jump to unconditional branch. 2014 if ((Opcode == Mips::J || Opcode == Mips::J_MM) && inPicMode()) { 2015 MCInst BInst; 2016 BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ); 2017 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); 2018 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); 2019 BInst.addOperand(Inst.getOperand(0)); 2020 Inst = BInst; 2021 } 2022 2023 // This expansion is not in a function called by tryExpandInstruction() 2024 // because the pseudo-instruction doesn't have a distinct opcode. 2025 if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { 2026 warnIfNoMacro(IDLoc); 2027 2028 const MCExpr *JalExpr = Inst.getOperand(0).getExpr(); 2029 2030 // We can do this expansion if there's only 1 symbol in the argument 2031 // expression. 2032 if (countMCSymbolRefExpr(JalExpr) > 1) 2033 return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode"); 2034 2035 // FIXME: This is checking the expression can be handled by the later stages 2036 // of the assembler. We ought to leave it to those later stages. 2037 const MCSymbol *JalSym = getSingleMCSymbol(JalExpr); 2038 2039 if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0), 2040 !isGP64bit(), IDLoc, Out, STI)) 2041 return true; 2042 2043 MCInst JalrInst; 2044 if (inMicroMipsMode()) 2045 JalrInst.setOpcode(IsCpRestoreSet ? Mips::JALRS_MM : Mips::JALR_MM); 2046 else 2047 JalrInst.setOpcode(Mips::JALR); 2048 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); 2049 JalrInst.addOperand(MCOperand::createReg(Mips::T9)); 2050 2051 if (EmitJalrReloc) { 2052 // As an optimization hint for the linker, before the JALR we add: 2053 // .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol 2054 // tmplabel: 2055 MCSymbol *TmpLabel = getContext().createTempSymbol(); 2056 const MCExpr *TmpExpr = MCSymbolRefExpr::create(TmpLabel, getContext()); 2057 const MCExpr *RelocJalrExpr = 2058 MCSymbolRefExpr::create(JalSym, MCSymbolRefExpr::VK_None, 2059 getContext(), IDLoc); 2060 2061 TOut.getStreamer().EmitRelocDirective(*TmpExpr, 2062 inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR", 2063 RelocJalrExpr, IDLoc, *STI); 2064 TOut.getStreamer().EmitLabel(TmpLabel); 2065 } 2066 2067 Inst = JalrInst; 2068 ExpandedJalSym = true; 2069 } 2070 2071 bool IsPCRelativeLoad = (MCID.TSFlags & MipsII::IsPCRelativeLoad) != 0; 2072 if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) { 2073 // Check the offset of memory operand, if it is a symbol 2074 // reference or immediate we may have to expand instructions. 2075 for (unsigned i = 0; i < MCID.getNumOperands(); i++) { 2076 const MCOperandInfo &OpInfo = MCID.OpInfo[i]; 2077 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) || 2078 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) { 2079 MCOperand &Op = Inst.getOperand(i); 2080 if (Op.isImm()) { 2081 if (!isInt<16>(Op.getImm())) { 2082 // Offset can't exceed 16bit value. 2083 expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad()); 2084 return getParser().hasPendingError(); 2085 } 2086 } else if (Op.isExpr()) { 2087 const MCExpr *Expr = Op.getExpr(); 2088 if (Expr->getKind() == MCExpr::SymbolRef) { 2089 const MCSymbolRefExpr *SR = 2090 static_cast<const MCSymbolRefExpr *>(Expr); 2091 if (SR->getKind() == MCSymbolRefExpr::VK_None) { 2092 // Expand symbol. 2093 expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad()); 2094 return getParser().hasPendingError(); 2095 } 2096 } else if (!isEvaluated(Expr)) { 2097 expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad()); 2098 return getParser().hasPendingError(); 2099 } 2100 } 2101 } 2102 } // for 2103 } // if load/store 2104 2105 if (inMicroMipsMode()) { 2106 if (MCID.mayLoad() && Opcode != Mips::LWP_MM) { 2107 // Try to create 16-bit GP relative load instruction. 2108 for (unsigned i = 0; i < MCID.getNumOperands(); i++) { 2109 const MCOperandInfo &OpInfo = MCID.OpInfo[i]; 2110 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) || 2111 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) { 2112 MCOperand &Op = Inst.getOperand(i); 2113 if (Op.isImm()) { 2114 int MemOffset = Op.getImm(); 2115 MCOperand &DstReg = Inst.getOperand(0); 2116 MCOperand &BaseReg = Inst.getOperand(1); 2117 if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) && 2118 getContext().getRegisterInfo()->getRegClass( 2119 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && 2120 (BaseReg.getReg() == Mips::GP || 2121 BaseReg.getReg() == Mips::GP_64)) { 2122 2123 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, 2124 IDLoc, STI); 2125 return false; 2126 } 2127 } 2128 } 2129 } // for 2130 } // if load 2131 2132 // TODO: Handle this with the AsmOperandClass.PredicateMethod. 2133 2134 MCOperand Opnd; 2135 int Imm; 2136 2137 switch (Opcode) { 2138 default: 2139 break; 2140 case Mips::ADDIUSP_MM: 2141 Opnd = Inst.getOperand(0); 2142 if (!Opnd.isImm()) 2143 return Error(IDLoc, "expected immediate operand kind"); 2144 Imm = Opnd.getImm(); 2145 if (Imm < -1032 || Imm > 1028 || (Imm < 8 && Imm > -12) || 2146 Imm % 4 != 0) 2147 return Error(IDLoc, "immediate operand value out of range"); 2148 break; 2149 case Mips::SLL16_MM: 2150 case Mips::SRL16_MM: 2151 Opnd = Inst.getOperand(2); 2152 if (!Opnd.isImm()) 2153 return Error(IDLoc, "expected immediate operand kind"); 2154 Imm = Opnd.getImm(); 2155 if (Imm < 1 || Imm > 8) 2156 return Error(IDLoc, "immediate operand value out of range"); 2157 break; 2158 case Mips::LI16_MM: 2159 Opnd = Inst.getOperand(1); 2160 if (!Opnd.isImm()) 2161 return Error(IDLoc, "expected immediate operand kind"); 2162 Imm = Opnd.getImm(); 2163 if (Imm < -1 || Imm > 126) 2164 return Error(IDLoc, "immediate operand value out of range"); 2165 break; 2166 case Mips::ADDIUR2_MM: 2167 Opnd = Inst.getOperand(2); 2168 if (!Opnd.isImm()) 2169 return Error(IDLoc, "expected immediate operand kind"); 2170 Imm = Opnd.getImm(); 2171 if (!(Imm == 1 || Imm == -1 || 2172 ((Imm % 4 == 0) && Imm < 28 && Imm > 0))) 2173 return Error(IDLoc, "immediate operand value out of range"); 2174 break; 2175 case Mips::ANDI16_MM: 2176 Opnd = Inst.getOperand(2); 2177 if (!Opnd.isImm()) 2178 return Error(IDLoc, "expected immediate operand kind"); 2179 Imm = Opnd.getImm(); 2180 if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || 2181 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || 2182 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535)) 2183 return Error(IDLoc, "immediate operand value out of range"); 2184 break; 2185 case Mips::LBU16_MM: 2186 Opnd = Inst.getOperand(2); 2187 if (!Opnd.isImm()) 2188 return Error(IDLoc, "expected immediate operand kind"); 2189 Imm = Opnd.getImm(); 2190 if (Imm < -1 || Imm > 14) 2191 return Error(IDLoc, "immediate operand value out of range"); 2192 break; 2193 case Mips::SB16_MM: 2194 case Mips::SB16_MMR6: 2195 Opnd = Inst.getOperand(2); 2196 if (!Opnd.isImm()) 2197 return Error(IDLoc, "expected immediate operand kind"); 2198 Imm = Opnd.getImm(); 2199 if (Imm < 0 || Imm > 15) 2200 return Error(IDLoc, "immediate operand value out of range"); 2201 break; 2202 case Mips::LHU16_MM: 2203 case Mips::SH16_MM: 2204 case Mips::SH16_MMR6: 2205 Opnd = Inst.getOperand(2); 2206 if (!Opnd.isImm()) 2207 return Error(IDLoc, "expected immediate operand kind"); 2208 Imm = Opnd.getImm(); 2209 if (Imm < 0 || Imm > 30 || (Imm % 2 != 0)) 2210 return Error(IDLoc, "immediate operand value out of range"); 2211 break; 2212 case Mips::LW16_MM: 2213 case Mips::SW16_MM: 2214 case Mips::SW16_MMR6: 2215 Opnd = Inst.getOperand(2); 2216 if (!Opnd.isImm()) 2217 return Error(IDLoc, "expected immediate operand kind"); 2218 Imm = Opnd.getImm(); 2219 if (Imm < 0 || Imm > 60 || (Imm % 4 != 0)) 2220 return Error(IDLoc, "immediate operand value out of range"); 2221 break; 2222 case Mips::ADDIUPC_MM: 2223 Opnd = Inst.getOperand(1); 2224 if (!Opnd.isImm()) 2225 return Error(IDLoc, "expected immediate operand kind"); 2226 Imm = Opnd.getImm(); 2227 if ((Imm % 4 != 0) || !isInt<25>(Imm)) 2228 return Error(IDLoc, "immediate operand value out of range"); 2229 break; 2230 case Mips::LWP_MM: 2231 case Mips::SWP_MM: 2232 if (Inst.getOperand(0).getReg() == Mips::RA) 2233 return Error(IDLoc, "invalid operand for instruction"); 2234 break; 2235 case Mips::MOVEP_MM: 2236 case Mips::MOVEP_MMR6: { 2237 unsigned R0 = Inst.getOperand(0).getReg(); 2238 unsigned R1 = Inst.getOperand(1).getReg(); 2239 bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) || 2240 (R0 == Mips::A1 && R1 == Mips::A3) || 2241 (R0 == Mips::A2 && R1 == Mips::A3) || 2242 (R0 == Mips::A0 && R1 == Mips::S5) || 2243 (R0 == Mips::A0 && R1 == Mips::S6) || 2244 (R0 == Mips::A0 && R1 == Mips::A1) || 2245 (R0 == Mips::A0 && R1 == Mips::A2) || 2246 (R0 == Mips::A0 && R1 == Mips::A3)); 2247 if (!RegPair) 2248 return Error(IDLoc, "invalid operand for instruction"); 2249 break; 2250 } 2251 } 2252 } 2253 2254 bool FillDelaySlot = 2255 MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder(); 2256 if (FillDelaySlot) 2257 TOut.emitDirectiveSetNoReorder(); 2258 2259 MacroExpanderResultTy ExpandResult = 2260 tryExpandInstruction(Inst, IDLoc, Out, STI); 2261 switch (ExpandResult) { 2262 case MER_NotAMacro: 2263 Out.EmitInstruction(Inst, *STI); 2264 break; 2265 case MER_Success: 2266 break; 2267 case MER_Fail: 2268 return true; 2269 } 2270 2271 // We know we emitted an instruction on the MER_NotAMacro or MER_Success path. 2272 // If we're in microMIPS mode then we must also set EF_MIPS_MICROMIPS. 2273 if (inMicroMipsMode()) { 2274 TOut.setUsesMicroMips(); 2275 TOut.updateABIInfo(*this); 2276 } 2277 2278 // If this instruction has a delay slot and .set reorder is active, 2279 // emit a NOP after it. 2280 if (FillDelaySlot) { 2281 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI); 2282 TOut.emitDirectiveSetReorder(); 2283 } 2284 2285 if ((Opcode == Mips::JalOneReg || Opcode == Mips::JalTwoReg || 2286 ExpandedJalSym) && 2287 isPicAndNotNxxAbi()) { 2288 if (IsCpRestoreSet) { 2289 // We need a NOP between the JALR and the LW: 2290 // If .set reorder has been used, we've already emitted a NOP. 2291 // If .set noreorder has been used, we need to emit a NOP at this point. 2292 if (!AssemblerOptions.back()->isReorder()) 2293 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, 2294 STI); 2295 2296 // Load the $gp from the stack. 2297 TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI); 2298 } else 2299 Warning(IDLoc, "no .cprestore used in PIC mode"); 2300 } 2301 2302 return false; 2303 } 2304 2305 MipsAsmParser::MacroExpanderResultTy 2306 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 2307 const MCSubtargetInfo *STI) { 2308 switch (Inst.getOpcode()) { 2309 default: 2310 return MER_NotAMacro; 2311 case Mips::LoadImm32: 2312 return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2313 case Mips::LoadImm64: 2314 return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2315 case Mips::LoadAddrImm32: 2316 case Mips::LoadAddrImm64: 2317 assert(Inst.getOperand(0).isReg() && "expected register operand kind"); 2318 assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && 2319 "expected immediate operand kind"); 2320 2321 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, 2322 Inst.getOperand(1), 2323 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, 2324 Out, STI) 2325 ? MER_Fail 2326 : MER_Success; 2327 case Mips::LoadAddrReg32: 2328 case Mips::LoadAddrReg64: 2329 assert(Inst.getOperand(0).isReg() && "expected register operand kind"); 2330 assert(Inst.getOperand(1).isReg() && "expected register operand kind"); 2331 assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) && 2332 "expected immediate operand kind"); 2333 2334 return expandLoadAddress(Inst.getOperand(0).getReg(), 2335 Inst.getOperand(1).getReg(), Inst.getOperand(2), 2336 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, 2337 Out, STI) 2338 ? MER_Fail 2339 : MER_Success; 2340 case Mips::B_MM_Pseudo: 2341 case Mips::B_MMR6_Pseudo: 2342 return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail 2343 : MER_Success; 2344 case Mips::SWM_MM: 2345 case Mips::LWM_MM: 2346 return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail 2347 : MER_Success; 2348 case Mips::JalOneReg: 2349 case Mips::JalTwoReg: 2350 return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2351 case Mips::BneImm: 2352 case Mips::BeqImm: 2353 case Mips::BEQLImmMacro: 2354 case Mips::BNELImmMacro: 2355 return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2356 case Mips::BLT: 2357 case Mips::BLE: 2358 case Mips::BGE: 2359 case Mips::BGT: 2360 case Mips::BLTU: 2361 case Mips::BLEU: 2362 case Mips::BGEU: 2363 case Mips::BGTU: 2364 case Mips::BLTL: 2365 case Mips::BLEL: 2366 case Mips::BGEL: 2367 case Mips::BGTL: 2368 case Mips::BLTUL: 2369 case Mips::BLEUL: 2370 case Mips::BGEUL: 2371 case Mips::BGTUL: 2372 case Mips::BLTImmMacro: 2373 case Mips::BLEImmMacro: 2374 case Mips::BGEImmMacro: 2375 case Mips::BGTImmMacro: 2376 case Mips::BLTUImmMacro: 2377 case Mips::BLEUImmMacro: 2378 case Mips::BGEUImmMacro: 2379 case Mips::BGTUImmMacro: 2380 case Mips::BLTLImmMacro: 2381 case Mips::BLELImmMacro: 2382 case Mips::BGELImmMacro: 2383 case Mips::BGTLImmMacro: 2384 case Mips::BLTULImmMacro: 2385 case Mips::BLEULImmMacro: 2386 case Mips::BGEULImmMacro: 2387 case Mips::BGTULImmMacro: 2388 return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2389 case Mips::SDivMacro: 2390 case Mips::SDivIMacro: 2391 case Mips::SRemMacro: 2392 case Mips::SRemIMacro: 2393 return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail 2394 : MER_Success; 2395 case Mips::DSDivMacro: 2396 case Mips::DSDivIMacro: 2397 case Mips::DSRemMacro: 2398 case Mips::DSRemIMacro: 2399 return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail 2400 : MER_Success; 2401 case Mips::UDivMacro: 2402 case Mips::UDivIMacro: 2403 case Mips::URemMacro: 2404 case Mips::URemIMacro: 2405 return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail 2406 : MER_Success; 2407 case Mips::DUDivMacro: 2408 case Mips::DUDivIMacro: 2409 case Mips::DURemMacro: 2410 case Mips::DURemIMacro: 2411 return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail 2412 : MER_Success; 2413 case Mips::PseudoTRUNC_W_S: 2414 return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail 2415 : MER_Success; 2416 case Mips::PseudoTRUNC_W_D32: 2417 return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail 2418 : MER_Success; 2419 case Mips::PseudoTRUNC_W_D: 2420 return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail 2421 : MER_Success; 2422 2423 case Mips::LoadImmSingleGPR: 2424 return expandLoadSingleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail 2425 : MER_Success; 2426 case Mips::LoadImmSingleFGR: 2427 return expandLoadSingleImmToFPR(Inst, IDLoc, Out, STI) ? MER_Fail 2428 : MER_Success; 2429 case Mips::LoadImmDoubleGPR: 2430 return expandLoadDoubleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail 2431 : MER_Success; 2432 case Mips::LoadImmDoubleFGR: 2433 return expandLoadDoubleImmToFPR(Inst, true, IDLoc, Out, STI) ? MER_Fail 2434 : MER_Success; 2435 case Mips::LoadImmDoubleFGR_32: 2436 return expandLoadDoubleImmToFPR(Inst, false, IDLoc, Out, STI) ? MER_Fail 2437 : MER_Success; 2438 2439 case Mips::Ulh: 2440 return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2441 case Mips::Ulhu: 2442 return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2443 case Mips::Ush: 2444 return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2445 case Mips::Ulw: 2446 case Mips::Usw: 2447 return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2448 case Mips::NORImm: 2449 case Mips::NORImm64: 2450 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2451 case Mips::SGE: 2452 case Mips::SGEU: 2453 return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2454 case Mips::SGEImm: 2455 case Mips::SGEUImm: 2456 case Mips::SGEImm64: 2457 case Mips::SGEUImm64: 2458 return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2459 case Mips::SGTImm: 2460 case Mips::SGTUImm: 2461 case Mips::SGTImm64: 2462 case Mips::SGTUImm64: 2463 return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2464 case Mips::SLTImm64: 2465 if (isInt<16>(Inst.getOperand(2).getImm())) { 2466 Inst.setOpcode(Mips::SLTi64); 2467 return MER_NotAMacro; 2468 } 2469 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2470 case Mips::SLTUImm64: 2471 if (isInt<16>(Inst.getOperand(2).getImm())) { 2472 Inst.setOpcode(Mips::SLTiu64); 2473 return MER_NotAMacro; 2474 } 2475 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2476 case Mips::ADDi: case Mips::ADDi_MM: 2477 case Mips::ADDiu: case Mips::ADDiu_MM: 2478 case Mips::SLTi: case Mips::SLTi_MM: 2479 case Mips::SLTiu: case Mips::SLTiu_MM: 2480 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2481 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2482 int64_t ImmValue = Inst.getOperand(2).getImm(); 2483 if (isInt<16>(ImmValue)) 2484 return MER_NotAMacro; 2485 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail 2486 : MER_Success; 2487 } 2488 return MER_NotAMacro; 2489 case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64: 2490 case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64: 2491 case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64: 2492 if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && 2493 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { 2494 int64_t ImmValue = Inst.getOperand(2).getImm(); 2495 if (isUInt<16>(ImmValue)) 2496 return MER_NotAMacro; 2497 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail 2498 : MER_Success; 2499 } 2500 return MER_NotAMacro; 2501 case Mips::ROL: 2502 case Mips::ROR: 2503 return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2504 case Mips::ROLImm: 2505 case Mips::RORImm: 2506 return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2507 case Mips::DROL: 2508 case Mips::DROR: 2509 return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2510 case Mips::DROLImm: 2511 case Mips::DRORImm: 2512 return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2513 case Mips::ABSMacro: 2514 return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2515 case Mips::MULImmMacro: 2516 case Mips::DMULImmMacro: 2517 return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2518 case Mips::MULOMacro: 2519 case Mips::DMULOMacro: 2520 return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2521 case Mips::MULOUMacro: 2522 case Mips::DMULOUMacro: 2523 return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2524 case Mips::DMULMacro: 2525 return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2526 case Mips::LDMacro: 2527 case Mips::SDMacro: 2528 return expandLoadStoreDMacro(Inst, IDLoc, Out, STI, 2529 Inst.getOpcode() == Mips::LDMacro) 2530 ? MER_Fail 2531 : MER_Success; 2532 case Mips::SDC1_M1: 2533 return expandStoreDM1Macro(Inst, IDLoc, Out, STI) 2534 ? MER_Fail 2535 : MER_Success; 2536 case Mips::SEQMacro: 2537 return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2538 case Mips::SEQIMacro: 2539 return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2540 case Mips::MFTC0: case Mips::MTTC0: 2541 case Mips::MFTGPR: case Mips::MTTGPR: 2542 case Mips::MFTLO: case Mips::MTTLO: 2543 case Mips::MFTHI: case Mips::MTTHI: 2544 case Mips::MFTACX: case Mips::MTTACX: 2545 case Mips::MFTDSP: case Mips::MTTDSP: 2546 case Mips::MFTC1: case Mips::MTTC1: 2547 case Mips::MFTHC1: case Mips::MTTHC1: 2548 case Mips::CFTC1: case Mips::CTTC1: 2549 return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2550 case Mips::SaaAddr: 2551 case Mips::SaadAddr: 2552 return expandSaaAddr(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; 2553 } 2554 } 2555 2556 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, 2557 MCStreamer &Out, 2558 const MCSubtargetInfo *STI) { 2559 MipsTargetStreamer &TOut = getTargetStreamer(); 2560 2561 // Create a JALR instruction which is going to replace the pseudo-JAL. 2562 MCInst JalrInst; 2563 JalrInst.setLoc(IDLoc); 2564 const MCOperand FirstRegOp = Inst.getOperand(0); 2565 const unsigned Opcode = Inst.getOpcode(); 2566 2567 if (Opcode == Mips::JalOneReg) { 2568 // jal $rs => jalr $rs 2569 if (IsCpRestoreSet && inMicroMipsMode()) { 2570 JalrInst.setOpcode(Mips::JALRS16_MM); 2571 JalrInst.addOperand(FirstRegOp); 2572 } else if (inMicroMipsMode()) { 2573 JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM); 2574 JalrInst.addOperand(FirstRegOp); 2575 } else { 2576 JalrInst.setOpcode(Mips::JALR); 2577 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); 2578 JalrInst.addOperand(FirstRegOp); 2579 } 2580 } else if (Opcode == Mips::JalTwoReg) { 2581 // jal $rd, $rs => jalr $rd, $rs 2582 if (IsCpRestoreSet && inMicroMipsMode()) 2583 JalrInst.setOpcode(Mips::JALRS_MM); 2584 else 2585 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); 2586 JalrInst.addOperand(FirstRegOp); 2587 const MCOperand SecondRegOp = Inst.getOperand(1); 2588 JalrInst.addOperand(SecondRegOp); 2589 } 2590 Out.EmitInstruction(JalrInst, *STI); 2591 2592 // If .set reorder is active and branch instruction has a delay slot, 2593 // emit a NOP after it. 2594 const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode()); 2595 if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) 2596 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc, 2597 STI); 2598 2599 return false; 2600 } 2601 2602 /// Can the value be represented by a unsigned N-bit value and a shift left? 2603 template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) { 2604 unsigned BitNum = findFirstSet(x); 2605 2606 return (x == x >> BitNum << BitNum) && isUInt<N>(x >> BitNum); 2607 } 2608 2609 /// Load (or add) an immediate into a register. 2610 /// 2611 /// @param ImmValue The immediate to load. 2612 /// @param DstReg The register that will hold the immediate. 2613 /// @param SrcReg A register to add to the immediate or Mips::NoRegister 2614 /// for a simple initialization. 2615 /// @param Is32BitImm Is ImmValue 32-bit or 64-bit? 2616 /// @param IsAddress True if the immediate represents an address. False if it 2617 /// is an integer. 2618 /// @param IDLoc Location of the immediate in the source file. 2619 bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, 2620 unsigned SrcReg, bool Is32BitImm, 2621 bool IsAddress, SMLoc IDLoc, MCStreamer &Out, 2622 const MCSubtargetInfo *STI) { 2623 MipsTargetStreamer &TOut = getTargetStreamer(); 2624 2625 if (!Is32BitImm && !isGP64bit()) { 2626 Error(IDLoc, "instruction requires a 64-bit architecture"); 2627 return true; 2628 } 2629 2630 if (Is32BitImm) { 2631 if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) { 2632 // Sign extend up to 64-bit so that the predicates match the hardware 2633 // behaviour. In particular, isInt<16>(0xffff8000) and similar should be 2634 // true. 2635 ImmValue = SignExtend64<32>(ImmValue); 2636 } else { 2637 Error(IDLoc, "instruction requires a 32-bit immediate"); 2638 return true; 2639 } 2640 } 2641 2642 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); 2643 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; 2644 2645 bool UseSrcReg = false; 2646 if (SrcReg != Mips::NoRegister) 2647 UseSrcReg = true; 2648 2649 unsigned TmpReg = DstReg; 2650 if (UseSrcReg && 2651 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { 2652 // At this point we need AT to perform the expansions and we exit if it is 2653 // not available. 2654 unsigned ATReg = getATReg(IDLoc); 2655 if (!ATReg) 2656 return true; 2657 TmpReg = ATReg; 2658 } 2659 2660 if (isInt<16>(ImmValue)) { 2661 if (!UseSrcReg) 2662 SrcReg = ZeroReg; 2663 2664 // This doesn't quite follow the usual ABI expectations for N32 but matches 2665 // traditional assembler behaviour. N32 would normally use addiu for both 2666 // integers and addresses. 2667 if (IsAddress && !Is32BitImm) { 2668 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); 2669 return false; 2670 } 2671 2672 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); 2673 return false; 2674 } 2675 2676 if (isUInt<16>(ImmValue)) { 2677 unsigned TmpReg = DstReg; 2678 if (SrcReg == DstReg) { 2679 TmpReg = getATReg(IDLoc); 2680 if (!TmpReg) 2681 return true; 2682 } 2683 2684 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); 2685 if (UseSrcReg) 2686 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); 2687 return false; 2688 } 2689 2690 if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) { 2691 warnIfNoMacro(IDLoc); 2692 2693 uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff; 2694 uint16_t Bits15To0 = ImmValue & 0xffff; 2695 if (!Is32BitImm && !isInt<32>(ImmValue)) { 2696 // Traditional behaviour seems to special case this particular value. It's 2697 // not clear why other masks are handled differently. 2698 if (ImmValue == 0xffffffff) { 2699 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); 2700 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); 2701 if (UseSrcReg) 2702 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); 2703 return false; 2704 } 2705 2706 // Expand to an ORi instead of a LUi to avoid sign-extending into the 2707 // upper 32 bits. 2708 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); 2709 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); 2710 if (Bits15To0) 2711 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); 2712 if (UseSrcReg) 2713 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); 2714 return false; 2715 } 2716 2717 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI); 2718 if (Bits15To0) 2719 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); 2720 if (UseSrcReg) 2721 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); 2722 return false; 2723 } 2724 2725 if (isShiftedUIntAtAnyPosition<16>(ImmValue)) { 2726 if (Is32BitImm) { 2727 Error(IDLoc, "instruction requires a 32-bit immediate"); 2728 return true; 2729 } 2730 2731 // Traditionally, these immediates are shifted as little as possible and as 2732 // such we align the most significant bit to bit 15 of our temporary. 2733 unsigned FirstSet = findFirstSet((uint64_t)ImmValue); 2734 unsigned LastSet = findLastSet((uint64_t)ImmValue); 2735 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); 2736 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff; 2737 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); 2738 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); 2739 2740 if (UseSrcReg) 2741 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); 2742 2743 return false; 2744 } 2745 2746 warnIfNoMacro(IDLoc); 2747 2748 // The remaining case is packed with a sequence of dsll and ori with zeros 2749 // being omitted and any neighbouring dsll's being coalesced. 2750 // The highest 32-bit's are equivalent to a 32-bit immediate load. 2751 2752 // Load bits 32-63 of ImmValue into bits 0-31 of the temporary register. 2753 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, 2754 IDLoc, Out, STI)) 2755 return false; 2756 2757 // Shift and accumulate into the register. If a 16-bit chunk is zero, then 2758 // skip it and defer the shift to the next chunk. 2759 unsigned ShiftCarriedForwards = 16; 2760 for (int BitNum = 16; BitNum >= 0; BitNum -= 16) { 2761 uint16_t ImmChunk = (ImmValue >> BitNum) & 0xffff; 2762 2763 if (ImmChunk != 0) { 2764 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); 2765 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI); 2766 ShiftCarriedForwards = 0; 2767 } 2768 2769 ShiftCarriedForwards += 16; 2770 } 2771 ShiftCarriedForwards -= 16; 2772 2773 // Finish any remaining shifts left by trailing zeros. 2774 if (ShiftCarriedForwards) 2775 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); 2776 2777 if (UseSrcReg) 2778 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); 2779 2780 return false; 2781 } 2782 2783 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, 2784 MCStreamer &Out, const MCSubtargetInfo *STI) { 2785 const MCOperand &ImmOp = Inst.getOperand(1); 2786 assert(ImmOp.isImm() && "expected immediate operand kind"); 2787 const MCOperand &DstRegOp = Inst.getOperand(0); 2788 assert(DstRegOp.isReg() && "expected register operand kind"); 2789 2790 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, 2791 Is32BitImm, false, IDLoc, Out, STI)) 2792 return true; 2793 2794 return false; 2795 } 2796 2797 bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, 2798 const MCOperand &Offset, 2799 bool Is32BitAddress, SMLoc IDLoc, 2800 MCStreamer &Out, 2801 const MCSubtargetInfo *STI) { 2802 // la can't produce a usable address when addresses are 64-bit. 2803 if (Is32BitAddress && ABI.ArePtrs64bit()) { 2804 // FIXME: Demote this to a warning and continue as if we had 'dla' instead. 2805 // We currently can't do this because we depend on the equality 2806 // operator and N64 can end up with a GPR32/GPR64 mismatch. 2807 Error(IDLoc, "la used to load 64-bit address"); 2808 // Continue as if we had 'dla' instead. 2809 Is32BitAddress = false; 2810 return true; 2811 } 2812 2813 // dla requires 64-bit addresses. 2814 if (!Is32BitAddress && !hasMips3()) { 2815 Error(IDLoc, "instruction requires a 64-bit architecture"); 2816 return true; 2817 } 2818 2819 if (!Offset.isImm()) 2820 return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg, 2821 Is32BitAddress, IDLoc, Out, STI); 2822 2823 if (!ABI.ArePtrs64bit()) { 2824 // Continue as if we had 'la' whether we had 'la' or 'dla'. 2825 Is32BitAddress = true; 2826 } 2827 2828 return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true, 2829 IDLoc, Out, STI); 2830 } 2831 2832 bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, 2833 unsigned DstReg, unsigned SrcReg, 2834 bool Is32BitSym, SMLoc IDLoc, 2835 MCStreamer &Out, 2836 const MCSubtargetInfo *STI) { 2837 MipsTargetStreamer &TOut = getTargetStreamer(); 2838 bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO && 2839 SrcReg != Mips::ZERO_64; 2840 warnIfNoMacro(IDLoc); 2841 2842 if (inPicMode()) { 2843 MCValue Res; 2844 if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) { 2845 Error(IDLoc, "expected relocatable expression"); 2846 return true; 2847 } 2848 if (Res.getSymB() != nullptr) { 2849 Error(IDLoc, "expected relocatable expression with only one symbol"); 2850 return true; 2851 } 2852 2853 bool IsPtr64 = ABI.ArePtrs64bit(); 2854 bool IsLocalSym = 2855 Res.getSymA()->getSymbol().isInSection() || 2856 Res.getSymA()->getSymbol().isTemporary() || 2857 (Res.getSymA()->getSymbol().isELF() && 2858 cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() == 2859 ELF::STB_LOCAL); 2860 bool UseXGOT = STI->getFeatureBits()[Mips::FeatureXGOT] && !IsLocalSym; 2861 2862 // The case where the result register is $25 is somewhat special. If the 2863 // symbol in the final relocation is external and not modified with a 2864 // constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT16 2865 // or R_MIPS_CALL16 instead of R_MIPS_GOT_DISP in 64-bit case. 2866 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && 2867 Res.getConstant() == 0 && !IsLocalSym) { 2868 if (UseXGOT) { 2869 const MCExpr *CallHiExpr = MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16, 2870 SymExpr, getContext()); 2871 const MCExpr *CallLoExpr = MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16, 2872 SymExpr, getContext()); 2873 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, 2874 STI); 2875 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, 2876 IDLoc, STI); 2877 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg, 2878 MCOperand::createExpr(CallLoExpr), IDLoc, STI); 2879 } else { 2880 const MCExpr *CallExpr = 2881 MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, SymExpr, getContext()); 2882 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg, 2883 MCOperand::createExpr(CallExpr), IDLoc, STI); 2884 } 2885 return false; 2886 } 2887 2888 unsigned TmpReg = DstReg; 2889 if (UseSrcReg && 2890 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, 2891 SrcReg)) { 2892 // If $rs is the same as $rd, we need to use AT. 2893 // If it is not available we exit. 2894 unsigned ATReg = getATReg(IDLoc); 2895 if (!ATReg) 2896 return true; 2897 TmpReg = ATReg; 2898 } 2899 2900 // FIXME: In case of N32 / N64 ABI and emabled XGOT, local addresses 2901 // loaded using R_MIPS_GOT_PAGE / R_MIPS_GOT_OFST pair of relocations. 2902 // FIXME: Implement XGOT for microMIPS. 2903 if (UseXGOT) { 2904 // Loading address from XGOT 2905 // External GOT: lui $tmp, %got_hi(symbol)($gp) 2906 // addu $tmp, $tmp, $gp 2907 // lw $tmp, %got_lo(symbol)($tmp) 2908 // >addiu $tmp, $tmp, offset 2909 // >addiu $rd, $tmp, $rs 2910 // The addiu's marked with a '>' may be omitted if they are redundant. If 2911 // this happens then the last instruction must use $rd as the result 2912 // register. 2913 const MCExpr *CallHiExpr = 2914 MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, SymExpr, getContext()); 2915 const MCExpr *CallLoExpr = MipsMCExpr::create( 2916 MipsMCExpr::MEK_GOT_LO16, Res.getSymA(), getContext()); 2917 2918 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc, 2919 STI); 2920 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg, 2921 IDLoc, STI); 2922 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg, 2923 MCOperand::createExpr(CallLoExpr), IDLoc, STI); 2924 2925 if (Res.getConstant() != 0) 2926 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, 2927 MCOperand::createExpr(MCConstantExpr::create( 2928 Res.getConstant(), getContext())), 2929 IDLoc, STI); 2930 2931 if (UseSrcReg) 2932 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, 2933 IDLoc, STI); 2934 return false; 2935 } 2936 2937 const MipsMCExpr *GotExpr = nullptr; 2938 const MCExpr *LoExpr = nullptr; 2939 if (ABI.IsN32() || ABI.IsN64()) { 2940 // The remaining cases are: 2941 // Small offset: ld $tmp, %got_disp(symbol)($gp) 2942 // >daddiu $tmp, $tmp, offset 2943 // >daddu $rd, $tmp, $rs 2944 // The daddiu's marked with a '>' may be omitted if they are redundant. If 2945 // this happens then the last instruction must use $rd as the result 2946 // register. 2947 GotExpr = MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, Res.getSymA(), 2948 getContext()); 2949 if (Res.getConstant() != 0) { 2950 // Symbols fully resolve with just the %got_disp(symbol) but we 2951 // must still account for any offset to the symbol for 2952 // expressions like symbol+8. 2953 LoExpr = MCConstantExpr::create(Res.getConstant(), getContext()); 2954 2955 // FIXME: Offsets greater than 16 bits are not yet implemented. 2956 // FIXME: The correct range is a 32-bit sign-extended number. 2957 if (Res.getConstant() < -0x8000 || Res.getConstant() > 0x7fff) { 2958 Error(IDLoc, "macro instruction uses large offset, which is not " 2959 "currently supported"); 2960 return true; 2961 } 2962 } 2963 } else { 2964 // The remaining cases are: 2965 // External GOT: lw $tmp, %got(symbol)($gp) 2966 // >addiu $tmp, $tmp, offset 2967 // >addiu $rd, $tmp, $rs 2968 // Local GOT: lw $tmp, %got(symbol+offset)($gp) 2969 // addiu $tmp, $tmp, %lo(symbol+offset)($gp) 2970 // >addiu $rd, $tmp, $rs 2971 // The addiu's marked with a '>' may be omitted if they are redundant. If 2972 // this happens then the last instruction must use $rd as the result 2973 // register. 2974 if (IsLocalSym) { 2975 GotExpr = 2976 MipsMCExpr::create(MipsMCExpr::MEK_GOT, SymExpr, getContext()); 2977 LoExpr = MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext()); 2978 } else { 2979 // External symbols fully resolve the symbol with just the %got(symbol) 2980 // but we must still account for any offset to the symbol for 2981 // expressions like symbol+8. 2982 GotExpr = MipsMCExpr::create(MipsMCExpr::MEK_GOT, Res.getSymA(), 2983 getContext()); 2984 if (Res.getConstant() != 0) 2985 LoExpr = MCConstantExpr::create(Res.getConstant(), getContext()); 2986 } 2987 } 2988 2989 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg, 2990 MCOperand::createExpr(GotExpr), IDLoc, STI); 2991 2992 if (LoExpr) 2993 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, 2994 MCOperand::createExpr(LoExpr), IDLoc, STI); 2995 2996 if (UseSrcReg) 2997 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, 2998 IDLoc, STI); 2999 3000 return false; 3001 } 3002 3003 const MipsMCExpr *HiExpr = 3004 MipsMCExpr::create(MipsMCExpr::MEK_HI, SymExpr, getContext()); 3005 const MipsMCExpr *LoExpr = 3006 MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext()); 3007 3008 // This is the 64-bit symbol address expansion. 3009 if (ABI.ArePtrs64bit() && isGP64bit()) { 3010 // We need AT for the 64-bit expansion in the cases where the optional 3011 // source register is the destination register and for the superscalar 3012 // scheduled form. 3013 // 3014 // If it is not available we exit if the destination is the same as the 3015 // source register. 3016 3017 const MipsMCExpr *HighestExpr = 3018 MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, SymExpr, getContext()); 3019 const MipsMCExpr *HigherExpr = 3020 MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, SymExpr, getContext()); 3021 3022 bool RdRegIsRsReg = 3023 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg); 3024 3025 if (canUseATReg() && UseSrcReg && RdRegIsRsReg) { 3026 unsigned ATReg = getATReg(IDLoc); 3027 3028 // If $rs is the same as $rd: 3029 // (d)la $rd, sym($rd) => lui $at, %highest(sym) 3030 // daddiu $at, $at, %higher(sym) 3031 // dsll $at, $at, 16 3032 // daddiu $at, $at, %hi(sym) 3033 // dsll $at, $at, 16 3034 // daddiu $at, $at, %lo(sym) 3035 // daddu $rd, $at, $rd 3036 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, 3037 STI); 3038 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, 3039 MCOperand::createExpr(HigherExpr), IDLoc, STI); 3040 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); 3041 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), 3042 IDLoc, STI); 3043 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); 3044 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), 3045 IDLoc, STI); 3046 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); 3047 3048 return false; 3049 } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) { 3050 unsigned ATReg = getATReg(IDLoc); 3051 3052 // If the $rs is different from $rd or if $rs isn't specified and we 3053 // have $at available: 3054 // (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym) 3055 // lui $at, %hi(sym) 3056 // daddiu $rd, $rd, %higher(sym) 3057 // daddiu $at, $at, %lo(sym) 3058 // dsll32 $rd, $rd, 0 3059 // daddu $rd, $rd, $at 3060 // (daddu $rd, $rd, $rs) 3061 // 3062 // Which is preferred for superscalar issue. 3063 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, 3064 STI); 3065 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); 3066 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, 3067 MCOperand::createExpr(HigherExpr), IDLoc, STI); 3068 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), 3069 IDLoc, STI); 3070 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); 3071 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); 3072 if (UseSrcReg) 3073 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); 3074 3075 return false; 3076 } else if ((!canUseATReg() && !RdRegIsRsReg) || 3077 (canUseATReg() && DstReg == getATReg(IDLoc))) { 3078 // Otherwise, synthesize the address in the destination register 3079 // serially: 3080 // (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym) 3081 // daddiu $rd, $rd, %higher(sym) 3082 // dsll $rd, $rd, 16 3083 // daddiu $rd, $rd, %hi(sym) 3084 // dsll $rd, $rd, 16 3085 // daddiu $rd, $rd, %lo(sym) 3086 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, 3087 STI); 3088 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, 3089 MCOperand::createExpr(HigherExpr), IDLoc, STI); 3090 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); 3091 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, 3092 MCOperand::createExpr(HiExpr), IDLoc, STI); 3093 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); 3094 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, 3095 MCOperand::createExpr(LoExpr), IDLoc, STI); 3096 if (UseSrcReg) 3097 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); 3098 3099 return false; 3100 } else { 3101 // We have a case where SrcReg == DstReg and we don't have $at 3102 // available. We can't expand this case, so error out appropriately. 3103 assert(SrcReg == DstReg && !canUseATReg() && 3104 "Could have expanded dla but didn't?"); 3105 reportParseError(IDLoc, 3106 "pseudo-instruction requires $at, which is not available"); 3107 return true; 3108 } 3109 } 3110 3111 // And now, the 32-bit symbol address expansion: 3112 // If $rs is the same as $rd: 3113 // (d)la $rd, sym($rd) => lui $at, %hi(sym) 3114 // ori $at, $at, %lo(sym) 3115 // addu $rd, $at, $rd 3116 // Otherwise, if the $rs is different from $rd or if $rs isn't specified: 3117 // (d)la $rd, sym/sym($rs) => lui $rd, %hi(sym) 3118 // ori $rd, $rd, %lo(sym) 3119 // (addu $rd, $rd, $rs) 3120 unsigned TmpReg = DstReg; 3121 if (UseSrcReg && 3122 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { 3123 // If $rs is the same as $rd, we need to use AT. 3124 // If it is not available we exit. 3125 unsigned ATReg = getATReg(IDLoc); 3126 if (!ATReg) 3127 return true; 3128 TmpReg = ATReg; 3129 } 3130 3131 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI); 3132 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), 3133 IDLoc, STI); 3134 3135 if (UseSrcReg) 3136 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); 3137 else 3138 assert( 3139 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg)); 3140 3141 return false; 3142 } 3143 3144 // Each double-precision register DO-D15 overlaps with two of the single 3145 // precision registers F0-F31. As an example, all of the following hold true: 3146 // D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context. 3147 static unsigned nextReg(unsigned Reg) { 3148 if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg)) 3149 return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1; 3150 switch (Reg) { 3151 default: llvm_unreachable("Unknown register in assembly macro expansion!"); 3152 case Mips::ZERO: return Mips::AT; 3153 case Mips::AT: return Mips::V0; 3154 case Mips::V0: return Mips::V1; 3155 case Mips::V1: return Mips::A0; 3156 case Mips::A0: return Mips::A1; 3157 case Mips::A1: return Mips::A2; 3158 case Mips::A2: return Mips::A3; 3159 case Mips::A3: return Mips::T0; 3160 case Mips::T0: return Mips::T1; 3161 case Mips::T1: return Mips::T2; 3162 case Mips::T2: return Mips::T3; 3163 case Mips::T3: return Mips::T4; 3164 case Mips::T4: return Mips::T5; 3165 case Mips::T5: return Mips::T6; 3166 case Mips::T6: return Mips::T7; 3167 case Mips::T7: return Mips::S0; 3168 case Mips::S0: return Mips::S1; 3169 case Mips::S1: return Mips::S2; 3170 case Mips::S2: return Mips::S3; 3171 case Mips::S3: return Mips::S4; 3172 case Mips::S4: return Mips::S5; 3173 case Mips::S5: return Mips::S6; 3174 case Mips::S6: return Mips::S7; 3175 case Mips::S7: return Mips::T8; 3176 case Mips::T8: return Mips::T9; 3177 case Mips::T9: return Mips::K0; 3178 case Mips::K0: return Mips::K1; 3179 case Mips::K1: return Mips::GP; 3180 case Mips::GP: return Mips::SP; 3181 case Mips::SP: return Mips::FP; 3182 case Mips::FP: return Mips::RA; 3183 case Mips::RA: return Mips::ZERO; 3184 case Mips::D0: return Mips::F1; 3185 case Mips::D1: return Mips::F3; 3186 case Mips::D2: return Mips::F5; 3187 case Mips::D3: return Mips::F7; 3188 case Mips::D4: return Mips::F9; 3189 case Mips::D5: return Mips::F11; 3190 case Mips::D6: return Mips::F13; 3191 case Mips::D7: return Mips::F15; 3192 case Mips::D8: return Mips::F17; 3193 case Mips::D9: return Mips::F19; 3194 case Mips::D10: return Mips::F21; 3195 case Mips::D11: return Mips::F23; 3196 case Mips::D12: return Mips::F25; 3197 case Mips::D13: return Mips::F27; 3198 case Mips::D14: return Mips::F29; 3199 case Mips::D15: return Mips::F31; 3200 } 3201 } 3202 3203 // FIXME: This method is too general. In principle we should compute the number 3204 // of instructions required to synthesize the immediate inline compared to 3205 // synthesizing the address inline and relying on non .text sections. 3206 // For static O32 and N32 this may yield a small benefit, for static N64 this is 3207 // likely to yield a much larger benefit as we have to synthesize a 64bit 3208 // address to load a 64 bit value. 3209 bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, 3210 MCSymbol *Sym) { 3211 unsigned ATReg = getATReg(IDLoc); 3212 if (!ATReg) 3213 return true; 3214 3215 if(IsPicEnabled) { 3216 const MCExpr *GotSym = 3217 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 3218 const MipsMCExpr *GotExpr = 3219 MipsMCExpr::create(MipsMCExpr::MEK_GOT, GotSym, getContext()); 3220 3221 if(isABI_O32() || isABI_N32()) { 3222 TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr), 3223 IDLoc, STI); 3224 } else { //isABI_N64() 3225 TOut.emitRRX(Mips::LD, ATReg, GPReg, MCOperand::createExpr(GotExpr), 3226 IDLoc, STI); 3227 } 3228 } else { //!IsPicEnabled 3229 const MCExpr *HiSym = 3230 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 3231 const MipsMCExpr *HiExpr = 3232 MipsMCExpr::create(MipsMCExpr::MEK_HI, HiSym, getContext()); 3233 3234 // FIXME: This is technically correct but gives a different result to gas, 3235 // but gas is incomplete there (it has a fixme noting it doesn't work with 3236 // 64-bit addresses). 3237 // FIXME: With -msym32 option, the address expansion for N64 should probably 3238 // use the O32 / N32 case. It's safe to use the 64 address expansion as the 3239 // symbol's value is considered sign extended. 3240 if(isABI_O32() || isABI_N32()) { 3241 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); 3242 } else { //isABI_N64() 3243 const MCExpr *HighestSym = 3244 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 3245 const MipsMCExpr *HighestExpr = 3246 MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, HighestSym, getContext()); 3247 const MCExpr *HigherSym = 3248 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 3249 const MipsMCExpr *HigherExpr = 3250 MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, HigherSym, getContext()); 3251 3252 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, 3253 STI); 3254 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, 3255 MCOperand::createExpr(HigherExpr), IDLoc, STI); 3256 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); 3257 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), 3258 IDLoc, STI); 3259 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); 3260 } 3261 } 3262 return false; 3263 } 3264 3265 static uint64_t convertIntToDoubleImm(uint64_t ImmOp64) { 3266 // If ImmOp64 is AsmToken::Integer type (all bits set to zero in the 3267 // exponent field), convert it to double (e.g. 1 to 1.0) 3268 if ((Hi_32(ImmOp64) & 0x7ff00000) == 0) { 3269 APFloat RealVal(APFloat::IEEEdouble(), ImmOp64); 3270 ImmOp64 = RealVal.bitcastToAPInt().getZExtValue(); 3271 } 3272 return ImmOp64; 3273 } 3274 3275 static uint32_t covertDoubleImmToSingleImm(uint64_t ImmOp64) { 3276 // Conversion of a double in an uint64_t to a float in a uint32_t, 3277 // retaining the bit pattern of a float. 3278 double DoubleImm = BitsToDouble(ImmOp64); 3279 float TmpFloat = static_cast<float>(DoubleImm); 3280 return FloatToBits(TmpFloat); 3281 } 3282 3283 bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, 3284 MCStreamer &Out, 3285 const MCSubtargetInfo *STI) { 3286 assert(Inst.getNumOperands() == 2 && "Invalid operand count"); 3287 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3288 "Invalid instruction operand."); 3289 3290 unsigned FirstReg = Inst.getOperand(0).getReg(); 3291 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3292 3293 uint32_t ImmOp32 = covertDoubleImmToSingleImm(convertIntToDoubleImm(ImmOp64)); 3294 3295 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, 3296 Out, STI); 3297 } 3298 3299 bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, 3300 MCStreamer &Out, 3301 const MCSubtargetInfo *STI) { 3302 MipsTargetStreamer &TOut = getTargetStreamer(); 3303 assert(Inst.getNumOperands() == 2 && "Invalid operand count"); 3304 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3305 "Invalid instruction operand."); 3306 3307 unsigned FirstReg = Inst.getOperand(0).getReg(); 3308 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3309 3310 ImmOp64 = convertIntToDoubleImm(ImmOp64); 3311 3312 uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64); 3313 3314 unsigned TmpReg = Mips::ZERO; 3315 if (ImmOp32 != 0) { 3316 TmpReg = getATReg(IDLoc); 3317 if (!TmpReg) 3318 return true; 3319 } 3320 3321 if (Lo_32(ImmOp64) == 0) { 3322 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, 3323 true, false, IDLoc, Out, STI)) 3324 return true; 3325 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); 3326 return false; 3327 } 3328 3329 MCSection *CS = getStreamer().getCurrentSectionOnly(); 3330 // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections 3331 // where appropriate. 3332 MCSection *ReadOnlySection = 3333 getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); 3334 3335 MCSymbol *Sym = getContext().createTempSymbol(); 3336 const MCExpr *LoSym = 3337 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 3338 const MipsMCExpr *LoExpr = 3339 MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); 3340 3341 getStreamer().SwitchSection(ReadOnlySection); 3342 getStreamer().EmitLabel(Sym, IDLoc); 3343 getStreamer().EmitIntValue(ImmOp32, 4); 3344 getStreamer().SwitchSection(CS); 3345 3346 if (emitPartialAddress(TOut, IDLoc, Sym)) 3347 return true; 3348 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), 3349 IDLoc, STI); 3350 return false; 3351 } 3352 3353 bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, 3354 MCStreamer &Out, 3355 const MCSubtargetInfo *STI) { 3356 MipsTargetStreamer &TOut = getTargetStreamer(); 3357 assert(Inst.getNumOperands() == 2 && "Invalid operand count"); 3358 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3359 "Invalid instruction operand."); 3360 3361 unsigned FirstReg = Inst.getOperand(0).getReg(); 3362 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3363 3364 ImmOp64 = convertIntToDoubleImm(ImmOp64); 3365 3366 if (Lo_32(ImmOp64) == 0) { 3367 if (isGP64bit()) { 3368 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, 3369 IDLoc, Out, STI)) 3370 return true; 3371 } else { 3372 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, 3373 IDLoc, Out, STI)) 3374 return true; 3375 3376 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, 3377 IDLoc, Out, STI)) 3378 return true; 3379 } 3380 return false; 3381 } 3382 3383 MCSection *CS = getStreamer().getCurrentSectionOnly(); 3384 MCSection *ReadOnlySection = 3385 getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); 3386 3387 MCSymbol *Sym = getContext().createTempSymbol(); 3388 const MCExpr *LoSym = 3389 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 3390 const MipsMCExpr *LoExpr = 3391 MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); 3392 3393 getStreamer().SwitchSection(ReadOnlySection); 3394 getStreamer().EmitLabel(Sym, IDLoc); 3395 getStreamer().EmitValueToAlignment(8); 3396 getStreamer().EmitIntValue(ImmOp64, 8); 3397 getStreamer().SwitchSection(CS); 3398 3399 unsigned TmpReg = getATReg(IDLoc); 3400 if (!TmpReg) 3401 return true; 3402 3403 if (emitPartialAddress(TOut, IDLoc, Sym)) 3404 return true; 3405 3406 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, 3407 MCOperand::createExpr(LoExpr), IDLoc, STI); 3408 3409 if (isGP64bit()) 3410 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); 3411 else { 3412 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI); 3413 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI); 3414 } 3415 return false; 3416 } 3417 3418 bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, 3419 SMLoc IDLoc, MCStreamer &Out, 3420 const MCSubtargetInfo *STI) { 3421 MipsTargetStreamer &TOut = getTargetStreamer(); 3422 assert(Inst.getNumOperands() == 2 && "Invalid operand count"); 3423 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && 3424 "Invalid instruction operand."); 3425 3426 unsigned FirstReg = Inst.getOperand(0).getReg(); 3427 uint64_t ImmOp64 = Inst.getOperand(1).getImm(); 3428 3429 ImmOp64 = convertIntToDoubleImm(ImmOp64); 3430 3431 unsigned TmpReg = Mips::ZERO; 3432 if (ImmOp64 != 0) { 3433 TmpReg = getATReg(IDLoc); 3434 if (!TmpReg) 3435 return true; 3436 } 3437 3438 if ((Lo_32(ImmOp64) == 0) && 3439 !((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) { 3440 if (isGP64bit()) { 3441 if (TmpReg != Mips::ZERO && 3442 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc, 3443 Out, STI)) 3444 return true; 3445 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI); 3446 return false; 3447 } 3448 3449 if (TmpReg != Mips::ZERO && 3450 loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false, 3451 IDLoc, Out, STI)) 3452 return true; 3453 3454 if (hasMips32r2()) { 3455 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); 3456 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI); 3457 } else { 3458 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); 3459 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); 3460 } 3461 return false; 3462 } 3463 3464 MCSection *CS = getStreamer().getCurrentSectionOnly(); 3465 // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections 3466 // where appropriate. 3467 MCSection *ReadOnlySection = 3468 getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); 3469 3470 MCSymbol *Sym = getContext().createTempSymbol(); 3471 const MCExpr *LoSym = 3472 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 3473 const MipsMCExpr *LoExpr = 3474 MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); 3475 3476 getStreamer().SwitchSection(ReadOnlySection); 3477 getStreamer().EmitLabel(Sym, IDLoc); 3478 getStreamer().EmitValueToAlignment(8); 3479 getStreamer().EmitIntValue(ImmOp64, 8); 3480 getStreamer().SwitchSection(CS); 3481 3482 if (emitPartialAddress(TOut, IDLoc, Sym)) 3483 return true; 3484 3485 TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg, 3486 MCOperand::createExpr(LoExpr), IDLoc, STI); 3487 3488 return false; 3489 } 3490 3491 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, 3492 MCStreamer &Out, 3493 const MCSubtargetInfo *STI) { 3494 MipsTargetStreamer &TOut = getTargetStreamer(); 3495 3496 assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 && 3497 "unexpected number of operands"); 3498 3499 MCOperand Offset = Inst.getOperand(0); 3500 if (Offset.isExpr()) { 3501 Inst.clear(); 3502 Inst.setOpcode(Mips::BEQ_MM); 3503 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 3504 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 3505 Inst.addOperand(MCOperand::createExpr(Offset.getExpr())); 3506 } else { 3507 assert(Offset.isImm() && "expected immediate operand kind"); 3508 if (isInt<11>(Offset.getImm())) { 3509 // If offset fits into 11 bits then this instruction becomes microMIPS 3510 // 16-bit unconditional branch instruction. 3511 if (inMicroMipsMode()) 3512 Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM); 3513 } else { 3514 if (!isInt<17>(Offset.getImm())) 3515 return Error(IDLoc, "branch target out of range"); 3516 if (offsetToAlignment(Offset.getImm(), Align(2))) 3517 return Error(IDLoc, "branch to misaligned address"); 3518 Inst.clear(); 3519 Inst.setOpcode(Mips::BEQ_MM); 3520 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 3521 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 3522 Inst.addOperand(MCOperand::createImm(Offset.getImm())); 3523 } 3524 } 3525 Out.EmitInstruction(Inst, *STI); 3526 3527 // If .set reorder is active and branch instruction has a delay slot, 3528 // emit a NOP after it. 3529 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 3530 if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) 3531 TOut.emitEmptyDelaySlot(true, IDLoc, STI); 3532 3533 return false; 3534 } 3535 3536 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 3537 const MCSubtargetInfo *STI) { 3538 MipsTargetStreamer &TOut = getTargetStreamer(); 3539 const MCOperand &DstRegOp = Inst.getOperand(0); 3540 assert(DstRegOp.isReg() && "expected register operand kind"); 3541 3542 const MCOperand &ImmOp = Inst.getOperand(1); 3543 assert(ImmOp.isImm() && "expected immediate operand kind"); 3544 3545 const MCOperand &MemOffsetOp = Inst.getOperand(2); 3546 assert((MemOffsetOp.isImm() || MemOffsetOp.isExpr()) && 3547 "expected immediate or expression operand"); 3548 3549 bool IsLikely = false; 3550 3551 unsigned OpCode = 0; 3552 switch(Inst.getOpcode()) { 3553 case Mips::BneImm: 3554 OpCode = Mips::BNE; 3555 break; 3556 case Mips::BeqImm: 3557 OpCode = Mips::BEQ; 3558 break; 3559 case Mips::BEQLImmMacro: 3560 OpCode = Mips::BEQL; 3561 IsLikely = true; 3562 break; 3563 case Mips::BNELImmMacro: 3564 OpCode = Mips::BNEL; 3565 IsLikely = true; 3566 break; 3567 default: 3568 llvm_unreachable("Unknown immediate branch pseudo-instruction."); 3569 break; 3570 } 3571 3572 int64_t ImmValue = ImmOp.getImm(); 3573 if (ImmValue == 0) { 3574 if (IsLikely) { 3575 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, 3576 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); 3577 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); 3578 } else 3579 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, 3580 STI); 3581 } else { 3582 warnIfNoMacro(IDLoc); 3583 3584 unsigned ATReg = getATReg(IDLoc); 3585 if (!ATReg) 3586 return true; 3587 3588 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, 3589 IDLoc, Out, STI)) 3590 return true; 3591 3592 if (IsLikely) { 3593 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, 3594 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); 3595 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); 3596 } else 3597 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI); 3598 } 3599 return false; 3600 } 3601 3602 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 3603 const MCSubtargetInfo *STI, bool IsLoad) { 3604 const MCOperand &DstRegOp = Inst.getOperand(0); 3605 assert(DstRegOp.isReg() && "expected register operand kind"); 3606 const MCOperand &BaseRegOp = Inst.getOperand(1); 3607 assert(BaseRegOp.isReg() && "expected register operand kind"); 3608 3609 MipsTargetStreamer &TOut = getTargetStreamer(); 3610 unsigned DstReg = DstRegOp.getReg(); 3611 unsigned BaseReg = BaseRegOp.getReg(); 3612 unsigned TmpReg = DstReg; 3613 3614 const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode()); 3615 int16_t DstRegClass = Desc.OpInfo[0].RegClass; 3616 unsigned DstRegClassID = 3617 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID(); 3618 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || 3619 (DstRegClassID == Mips::GPR64RegClassID); 3620 3621 if (!IsLoad || !IsGPR || (BaseReg == DstReg)) { 3622 // At this point we need AT to perform the expansions 3623 // and we exit if it is not available. 3624 TmpReg = getATReg(IDLoc); 3625 if (!TmpReg) 3626 return; 3627 } 3628 3629 if (Inst.getNumOperands() > 3) { 3630 const MCOperand &BaseRegOp = Inst.getOperand(2); 3631 assert(BaseRegOp.isReg() && "expected register operand kind"); 3632 const MCOperand &ExprOp = Inst.getOperand(3); 3633 assert(ExprOp.isExpr() && "expected expression oprand kind"); 3634 3635 unsigned BaseReg = BaseRegOp.getReg(); 3636 const MCExpr *ExprOffset = ExprOp.getExpr(); 3637 3638 MCOperand LoOperand = MCOperand::createExpr( 3639 MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext())); 3640 MCOperand HiOperand = MCOperand::createExpr( 3641 MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext())); 3642 TOut.emitSCWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand, 3643 LoOperand, TmpReg, IDLoc, STI); 3644 return; 3645 } 3646 3647 const MCOperand &OffsetOp = Inst.getOperand(2); 3648 3649 if (OffsetOp.isImm()) { 3650 int64_t LoOffset = OffsetOp.getImm() & 0xffff; 3651 int64_t HiOffset = OffsetOp.getImm() & ~0xffff; 3652 3653 // If msb of LoOffset is 1(negative number) we must increment 3654 // HiOffset to account for the sign-extension of the low part. 3655 if (LoOffset & 0x8000) 3656 HiOffset += 0x10000; 3657 3658 bool IsLargeOffset = HiOffset != 0; 3659 3660 if (IsLargeOffset) { 3661 bool Is32BitImm = (HiOffset >> 32) == 0; 3662 if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true, 3663 IDLoc, Out, STI)) 3664 return; 3665 } 3666 3667 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64) 3668 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, 3669 BaseReg, IDLoc, STI); 3670 TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, LoOffset, IDLoc, STI); 3671 return; 3672 } 3673 3674 if (OffsetOp.isExpr()) { 3675 if (inPicMode()) { 3676 // FIXME: 3677 // c) Check that immediates of R_MIPS_GOT16/R_MIPS_LO16 relocations 3678 // do not exceed 16-bit. 3679 // d) Use R_MIPS_GOT_PAGE/R_MIPS_GOT_OFST relocations instead 3680 // of R_MIPS_GOT_DISP in appropriate cases to reduce number 3681 // of GOT entries. 3682 MCValue Res; 3683 if (!OffsetOp.getExpr()->evaluateAsRelocatable(Res, nullptr, nullptr)) { 3684 Error(IDLoc, "expected relocatable expression"); 3685 return; 3686 } 3687 if (Res.getSymB() != nullptr) { 3688 Error(IDLoc, "expected relocatable expression with only one symbol"); 3689 return; 3690 } 3691 3692 loadAndAddSymbolAddress(Res.getSymA(), TmpReg, BaseReg, 3693 !ABI.ArePtrs64bit(), IDLoc, Out, STI); 3694 TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, Res.getConstant(), IDLoc, 3695 STI); 3696 } else { 3697 // FIXME: Implement 64-bit case. 3698 // 1) lw $8, sym => lui $8, %hi(sym) 3699 // lw $8, %lo(sym)($8) 3700 // 2) sw $8, sym => lui $at, %hi(sym) 3701 // sw $8, %lo(sym)($at) 3702 const MCExpr *ExprOffset = OffsetOp.getExpr(); 3703 MCOperand LoOperand = MCOperand::createExpr( 3704 MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext())); 3705 MCOperand HiOperand = MCOperand::createExpr( 3706 MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext())); 3707 3708 // Generate the base address in TmpReg. 3709 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); 3710 if (BaseReg != Mips::ZERO) 3711 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); 3712 // Emit the load or store with the adjusted base and offset. 3713 TOut.emitRRX(Inst.getOpcode(), DstReg, TmpReg, LoOperand, IDLoc, STI); 3714 } 3715 return; 3716 } 3717 3718 llvm_unreachable("unexpected operand type"); 3719 } 3720 3721 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, 3722 MCStreamer &Out, 3723 const MCSubtargetInfo *STI) { 3724 unsigned OpNum = Inst.getNumOperands(); 3725 unsigned Opcode = Inst.getOpcode(); 3726 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; 3727 3728 assert(Inst.getOperand(OpNum - 1).isImm() && 3729 Inst.getOperand(OpNum - 2).isReg() && 3730 Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand."); 3731 3732 if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 && 3733 Inst.getOperand(OpNum - 1).getImm() >= 0 && 3734 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP || 3735 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) && 3736 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA || 3737 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) { 3738 // It can be implemented as SWM16 or LWM16 instruction. 3739 if (inMicroMipsMode() && hasMips32r6()) 3740 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; 3741 else 3742 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; 3743 } 3744 3745 Inst.setOpcode(NewOpcode); 3746 Out.EmitInstruction(Inst, *STI); 3747 return false; 3748 } 3749 3750 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, 3751 MCStreamer &Out, 3752 const MCSubtargetInfo *STI) { 3753 MipsTargetStreamer &TOut = getTargetStreamer(); 3754 bool EmittedNoMacroWarning = false; 3755 unsigned PseudoOpcode = Inst.getOpcode(); 3756 unsigned SrcReg = Inst.getOperand(0).getReg(); 3757 const MCOperand &TrgOp = Inst.getOperand(1); 3758 const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr(); 3759 3760 unsigned ZeroSrcOpcode, ZeroTrgOpcode; 3761 bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality; 3762 3763 unsigned TrgReg; 3764 if (TrgOp.isReg()) 3765 TrgReg = TrgOp.getReg(); 3766 else if (TrgOp.isImm()) { 3767 warnIfNoMacro(IDLoc); 3768 EmittedNoMacroWarning = true; 3769 3770 TrgReg = getATReg(IDLoc); 3771 if (!TrgReg) 3772 return true; 3773 3774 switch(PseudoOpcode) { 3775 default: 3776 llvm_unreachable("unknown opcode for branch pseudo-instruction"); 3777 case Mips::BLTImmMacro: 3778 PseudoOpcode = Mips::BLT; 3779 break; 3780 case Mips::BLEImmMacro: 3781 PseudoOpcode = Mips::BLE; 3782 break; 3783 case Mips::BGEImmMacro: 3784 PseudoOpcode = Mips::BGE; 3785 break; 3786 case Mips::BGTImmMacro: 3787 PseudoOpcode = Mips::BGT; 3788 break; 3789 case Mips::BLTUImmMacro: 3790 PseudoOpcode = Mips::BLTU; 3791 break; 3792 case Mips::BLEUImmMacro: 3793 PseudoOpcode = Mips::BLEU; 3794 break; 3795 case Mips::BGEUImmMacro: 3796 PseudoOpcode = Mips::BGEU; 3797 break; 3798 case Mips::BGTUImmMacro: 3799 PseudoOpcode = Mips::BGTU; 3800 break; 3801 case Mips::BLTLImmMacro: 3802 PseudoOpcode = Mips::BLTL; 3803 break; 3804 case Mips::BLELImmMacro: 3805 PseudoOpcode = Mips::BLEL; 3806 break; 3807 case Mips::BGELImmMacro: 3808 PseudoOpcode = Mips::BGEL; 3809 break; 3810 case Mips::BGTLImmMacro: 3811 PseudoOpcode = Mips::BGTL; 3812 break; 3813 case Mips::BLTULImmMacro: 3814 PseudoOpcode = Mips::BLTUL; 3815 break; 3816 case Mips::BLEULImmMacro: 3817 PseudoOpcode = Mips::BLEUL; 3818 break; 3819 case Mips::BGEULImmMacro: 3820 PseudoOpcode = Mips::BGEUL; 3821 break; 3822 case Mips::BGTULImmMacro: 3823 PseudoOpcode = Mips::BGTUL; 3824 break; 3825 } 3826 3827 if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(), 3828 false, IDLoc, Out, STI)) 3829 return true; 3830 } 3831 3832 switch (PseudoOpcode) { 3833 case Mips::BLT: 3834 case Mips::BLTU: 3835 case Mips::BLTL: 3836 case Mips::BLTUL: 3837 AcceptsEquality = false; 3838 ReverseOrderSLT = false; 3839 IsUnsigned = 3840 ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); 3841 IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL)); 3842 ZeroSrcOpcode = Mips::BGTZ; 3843 ZeroTrgOpcode = Mips::BLTZ; 3844 break; 3845 case Mips::BLE: 3846 case Mips::BLEU: 3847 case Mips::BLEL: 3848 case Mips::BLEUL: 3849 AcceptsEquality = true; 3850 ReverseOrderSLT = true; 3851 IsUnsigned = 3852 ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL)); 3853 IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL)); 3854 ZeroSrcOpcode = Mips::BGEZ; 3855 ZeroTrgOpcode = Mips::BLEZ; 3856 break; 3857 case Mips::BGE: 3858 case Mips::BGEU: 3859 case Mips::BGEL: 3860 case Mips::BGEUL: 3861 AcceptsEquality = true; 3862 ReverseOrderSLT = false; 3863 IsUnsigned = 3864 ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL)); 3865 IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL)); 3866 ZeroSrcOpcode = Mips::BLEZ; 3867 ZeroTrgOpcode = Mips::BGEZ; 3868 break; 3869 case Mips::BGT: 3870 case Mips::BGTU: 3871 case Mips::BGTL: 3872 case Mips::BGTUL: 3873 AcceptsEquality = false; 3874 ReverseOrderSLT = true; 3875 IsUnsigned = 3876 ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL)); 3877 IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL)); 3878 ZeroSrcOpcode = Mips::BLTZ; 3879 ZeroTrgOpcode = Mips::BGTZ; 3880 break; 3881 default: 3882 llvm_unreachable("unknown opcode for branch pseudo-instruction"); 3883 } 3884 3885 bool IsTrgRegZero = (TrgReg == Mips::ZERO); 3886 bool IsSrcRegZero = (SrcReg == Mips::ZERO); 3887 if (IsSrcRegZero && IsTrgRegZero) { 3888 // FIXME: All of these Opcode-specific if's are needed for compatibility 3889 // with GAS' behaviour. However, they may not generate the most efficient 3890 // code in some circumstances. 3891 if (PseudoOpcode == Mips::BLT) { 3892 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), 3893 IDLoc, STI); 3894 return false; 3895 } 3896 if (PseudoOpcode == Mips::BLE) { 3897 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), 3898 IDLoc, STI); 3899 Warning(IDLoc, "branch is always taken"); 3900 return false; 3901 } 3902 if (PseudoOpcode == Mips::BGE) { 3903 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), 3904 IDLoc, STI); 3905 Warning(IDLoc, "branch is always taken"); 3906 return false; 3907 } 3908 if (PseudoOpcode == Mips::BGT) { 3909 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), 3910 IDLoc, STI); 3911 return false; 3912 } 3913 if (PseudoOpcode == Mips::BGTU) { 3914 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO, 3915 MCOperand::createExpr(OffsetExpr), IDLoc, STI); 3916 return false; 3917 } 3918 if (AcceptsEquality) { 3919 // If both registers are $0 and the pseudo-branch accepts equality, it 3920 // will always be taken, so we emit an unconditional branch. 3921 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, 3922 MCOperand::createExpr(OffsetExpr), IDLoc, STI); 3923 Warning(IDLoc, "branch is always taken"); 3924 return false; 3925 } 3926 // If both registers are $0 and the pseudo-branch does not accept 3927 // equality, it will never be taken, so we don't have to emit anything. 3928 return false; 3929 } 3930 if (IsSrcRegZero || IsTrgRegZero) { 3931 if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) || 3932 (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) { 3933 // If the $rs is $0 and the pseudo-branch is BGTU (0 > x) or 3934 // if the $rt is $0 and the pseudo-branch is BLTU (x < 0), 3935 // the pseudo-branch will never be taken, so we don't emit anything. 3936 // This only applies to unsigned pseudo-branches. 3937 return false; 3938 } 3939 if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) || 3940 (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) { 3941 // If the $rs is $0 and the pseudo-branch is BLEU (0 <= x) or 3942 // if the $rt is $0 and the pseudo-branch is BGEU (x >= 0), 3943 // the pseudo-branch will always be taken, so we emit an unconditional 3944 // branch. 3945 // This only applies to unsigned pseudo-branches. 3946 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, 3947 MCOperand::createExpr(OffsetExpr), IDLoc, STI); 3948 Warning(IDLoc, "branch is always taken"); 3949 return false; 3950 } 3951 if (IsUnsigned) { 3952 // If the $rs is $0 and the pseudo-branch is BLTU (0 < x) or 3953 // if the $rt is $0 and the pseudo-branch is BGTU (x > 0), 3954 // the pseudo-branch will be taken only when the non-zero register is 3955 // different from 0, so we emit a BNEZ. 3956 // 3957 // If the $rs is $0 and the pseudo-branch is BGEU (0 >= x) or 3958 // if the $rt is $0 and the pseudo-branch is BLEU (x <= 0), 3959 // the pseudo-branch will be taken only when the non-zero register is 3960 // equal to 0, so we emit a BEQZ. 3961 // 3962 // Because only BLEU and BGEU branch on equality, we can use the 3963 // AcceptsEquality variable to decide when to emit the BEQZ. 3964 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE, 3965 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO, 3966 MCOperand::createExpr(OffsetExpr), IDLoc, STI); 3967 return false; 3968 } 3969 // If we have a signed pseudo-branch and one of the registers is $0, 3970 // we can use an appropriate compare-to-zero branch. We select which one 3971 // to use in the switch statement above. 3972 TOut.emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode, 3973 IsSrcRegZero ? TrgReg : SrcReg, 3974 MCOperand::createExpr(OffsetExpr), IDLoc, STI); 3975 return false; 3976 } 3977 3978 // If neither the SrcReg nor the TrgReg are $0, we need AT to perform the 3979 // expansions. If it is not available, we return. 3980 unsigned ATRegNum = getATReg(IDLoc); 3981 if (!ATRegNum) 3982 return true; 3983 3984 if (!EmittedNoMacroWarning) 3985 warnIfNoMacro(IDLoc); 3986 3987 // SLT fits well with 2 of our 4 pseudo-branches: 3988 // BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and 3989 // BGT, where $rs > $rt, translates into "slt $at, $rt, $rs". 3990 // If the result of the SLT is 1, we branch, and if it's 0, we don't. 3991 // This is accomplished by using a BNEZ with the result of the SLT. 3992 // 3993 // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT 3994 // and BLE with BGT), so we change the BNEZ into a BEQZ. 3995 // Because only BGE and BLE branch on equality, we can use the 3996 // AcceptsEquality variable to decide when to emit the BEQZ. 3997 // Note that the order of the SLT arguments doesn't change between 3998 // opposites. 3999 // 4000 // The same applies to the unsigned variants, except that SLTu is used 4001 // instead of SLT. 4002 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, 4003 ReverseOrderSLT ? TrgReg : SrcReg, 4004 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI); 4005 4006 TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL) 4007 : (AcceptsEquality ? Mips::BEQ : Mips::BNE), 4008 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, 4009 STI); 4010 return false; 4011 } 4012 4013 // Expand a integer division macro. 4014 // 4015 // Notably we don't have to emit a warning when encountering $rt as the $zero 4016 // register, or 0 as an immediate. processInstruction() has already done that. 4017 // 4018 // The destination register can only be $zero when expanding (S)DivIMacro or 4019 // D(S)DivMacro. 4020 4021 bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4022 const MCSubtargetInfo *STI, 4023 const bool IsMips64, const bool Signed) { 4024 MipsTargetStreamer &TOut = getTargetStreamer(); 4025 4026 warnIfNoMacro(IDLoc); 4027 4028 const MCOperand &RdRegOp = Inst.getOperand(0); 4029 assert(RdRegOp.isReg() && "expected register operand kind"); 4030 unsigned RdReg = RdRegOp.getReg(); 4031 4032 const MCOperand &RsRegOp = Inst.getOperand(1); 4033 assert(RsRegOp.isReg() && "expected register operand kind"); 4034 unsigned RsReg = RsRegOp.getReg(); 4035 4036 unsigned RtReg; 4037 int64_t ImmValue; 4038 4039 const MCOperand &RtOp = Inst.getOperand(2); 4040 assert((RtOp.isReg() || RtOp.isImm()) && 4041 "expected register or immediate operand kind"); 4042 if (RtOp.isReg()) 4043 RtReg = RtOp.getReg(); 4044 else 4045 ImmValue = RtOp.getImm(); 4046 4047 unsigned DivOp; 4048 unsigned ZeroReg; 4049 unsigned SubOp; 4050 4051 if (IsMips64) { 4052 DivOp = Signed ? Mips::DSDIV : Mips::DUDIV; 4053 ZeroReg = Mips::ZERO_64; 4054 SubOp = Mips::DSUB; 4055 } else { 4056 DivOp = Signed ? Mips::SDIV : Mips::UDIV; 4057 ZeroReg = Mips::ZERO; 4058 SubOp = Mips::SUB; 4059 } 4060 4061 bool UseTraps = useTraps(); 4062 4063 unsigned Opcode = Inst.getOpcode(); 4064 bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro || 4065 Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro || 4066 Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro || 4067 Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro; 4068 4069 bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro || 4070 Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro || 4071 Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro || 4072 Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro; 4073 4074 if (RtOp.isImm()) { 4075 unsigned ATReg = getATReg(IDLoc); 4076 if (!ATReg) 4077 return true; 4078 4079 if (ImmValue == 0) { 4080 if (UseTraps) 4081 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); 4082 else 4083 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); 4084 return false; 4085 } 4086 4087 if (isRem && (ImmValue == 1 || (Signed && (ImmValue == -1)))) { 4088 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); 4089 return false; 4090 } else if (isDiv && ImmValue == 1) { 4091 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI); 4092 return false; 4093 } else if (isDiv && Signed && ImmValue == -1) { 4094 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); 4095 return false; 4096 } else { 4097 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), 4098 false, Inst.getLoc(), Out, STI)) 4099 return true; 4100 TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI); 4101 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); 4102 return false; 4103 } 4104 return true; 4105 } 4106 4107 // If the macro expansion of (d)div(u) or (d)rem(u) would always trap or 4108 // break, insert the trap/break and exit. This gives a different result to 4109 // GAS. GAS has an inconsistency/missed optimization in that not all cases 4110 // are handled equivalently. As the observed behaviour is the same, we're ok. 4111 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) { 4112 if (UseTraps) { 4113 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); 4114 return false; 4115 } 4116 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); 4117 return false; 4118 } 4119 4120 // (d)rem(u) $0, $X, $Y is a special case. Like div $zero, $X, $Y, it does 4121 // not expand to macro sequence. 4122 if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) { 4123 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); 4124 return false; 4125 } 4126 4127 // Temporary label for first branch traget 4128 MCContext &Context = TOut.getStreamer().getContext(); 4129 MCSymbol *BrTarget; 4130 MCOperand LabelOp; 4131 4132 if (UseTraps) { 4133 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); 4134 } else { 4135 // Branch to the li instruction. 4136 BrTarget = Context.createTempSymbol(); 4137 LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context)); 4138 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI); 4139 } 4140 4141 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); 4142 4143 if (!UseTraps) 4144 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); 4145 4146 if (!Signed) { 4147 if (!UseTraps) 4148 TOut.getStreamer().EmitLabel(BrTarget); 4149 4150 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); 4151 return false; 4152 } 4153 4154 unsigned ATReg = getATReg(IDLoc); 4155 if (!ATReg) 4156 return true; 4157 4158 if (!UseTraps) 4159 TOut.getStreamer().EmitLabel(BrTarget); 4160 4161 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); 4162 4163 // Temporary label for the second branch target. 4164 MCSymbol *BrTargetEnd = Context.createTempSymbol(); 4165 MCOperand LabelOpEnd = 4166 MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context)); 4167 4168 // Branch to the mflo instruction. 4169 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI); 4170 4171 if (IsMips64) { 4172 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); 4173 TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI); 4174 } else { 4175 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI); 4176 } 4177 4178 if (UseTraps) 4179 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); 4180 else { 4181 // Branch to the mflo instruction. 4182 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI); 4183 TOut.emitNop(IDLoc, STI); 4184 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); 4185 } 4186 4187 TOut.getStreamer().EmitLabel(BrTargetEnd); 4188 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); 4189 return false; 4190 } 4191 4192 bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, 4193 SMLoc IDLoc, MCStreamer &Out, 4194 const MCSubtargetInfo *STI) { 4195 MipsTargetStreamer &TOut = getTargetStreamer(); 4196 4197 assert(Inst.getNumOperands() == 3 && "Invalid operand count"); 4198 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && 4199 Inst.getOperand(2).isReg() && "Invalid instruction operand."); 4200 4201 unsigned FirstReg = Inst.getOperand(0).getReg(); 4202 unsigned SecondReg = Inst.getOperand(1).getReg(); 4203 unsigned ThirdReg = Inst.getOperand(2).getReg(); 4204 4205 if (hasMips1() && !hasMips2()) { 4206 unsigned ATReg = getATReg(IDLoc); 4207 if (!ATReg) 4208 return true; 4209 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); 4210 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); 4211 TOut.emitNop(IDLoc, STI); 4212 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI); 4213 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI); 4214 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); 4215 TOut.emitNop(IDLoc, STI); 4216 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32) 4217 : Mips::CVT_W_S, 4218 FirstReg, SecondReg, IDLoc, STI); 4219 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); 4220 TOut.emitNop(IDLoc, STI); 4221 return false; 4222 } 4223 4224 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32) 4225 : Mips::TRUNC_W_S, 4226 FirstReg, SecondReg, IDLoc, STI); 4227 4228 return false; 4229 } 4230 4231 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, 4232 MCStreamer &Out, const MCSubtargetInfo *STI) { 4233 if (hasMips32r6() || hasMips64r6()) { 4234 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); 4235 } 4236 4237 const MCOperand &DstRegOp = Inst.getOperand(0); 4238 assert(DstRegOp.isReg() && "expected register operand kind"); 4239 const MCOperand &SrcRegOp = Inst.getOperand(1); 4240 assert(SrcRegOp.isReg() && "expected register operand kind"); 4241 const MCOperand &OffsetImmOp = Inst.getOperand(2); 4242 assert(OffsetImmOp.isImm() && "expected immediate operand kind"); 4243 4244 MipsTargetStreamer &TOut = getTargetStreamer(); 4245 unsigned DstReg = DstRegOp.getReg(); 4246 unsigned SrcReg = SrcRegOp.getReg(); 4247 int64_t OffsetValue = OffsetImmOp.getImm(); 4248 4249 // NOTE: We always need AT for ULHU, as it is always used as the source 4250 // register for one of the LBu's. 4251 warnIfNoMacro(IDLoc); 4252 unsigned ATReg = getATReg(IDLoc); 4253 if (!ATReg) 4254 return true; 4255 4256 bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue)); 4257 if (IsLargeOffset) { 4258 if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true, 4259 IDLoc, Out, STI)) 4260 return true; 4261 } 4262 4263 int64_t FirstOffset = IsLargeOffset ? 0 : OffsetValue; 4264 int64_t SecondOffset = IsLargeOffset ? 1 : (OffsetValue + 1); 4265 if (isLittle()) 4266 std::swap(FirstOffset, SecondOffset); 4267 4268 unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg; 4269 unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg; 4270 4271 unsigned LbuSrcReg = IsLargeOffset ? ATReg : SrcReg; 4272 unsigned SllReg = IsLargeOffset ? DstReg : ATReg; 4273 4274 TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg, 4275 FirstOffset, IDLoc, STI); 4276 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI); 4277 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); 4278 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); 4279 4280 return false; 4281 } 4282 4283 bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4284 const MCSubtargetInfo *STI) { 4285 if (hasMips32r6() || hasMips64r6()) { 4286 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); 4287 } 4288 4289 const MCOperand &DstRegOp = Inst.getOperand(0); 4290 assert(DstRegOp.isReg() && "expected register operand kind"); 4291 const MCOperand &SrcRegOp = Inst.getOperand(1); 4292 assert(SrcRegOp.isReg() && "expected register operand kind"); 4293 const MCOperand &OffsetImmOp = Inst.getOperand(2); 4294 assert(OffsetImmOp.isImm() && "expected immediate operand kind"); 4295 4296 MipsTargetStreamer &TOut = getTargetStreamer(); 4297 unsigned DstReg = DstRegOp.getReg(); 4298 unsigned SrcReg = SrcRegOp.getReg(); 4299 int64_t OffsetValue = OffsetImmOp.getImm(); 4300 4301 warnIfNoMacro(IDLoc); 4302 unsigned ATReg = getATReg(IDLoc); 4303 if (!ATReg) 4304 return true; 4305 4306 bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue)); 4307 if (IsLargeOffset) { 4308 if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true, 4309 IDLoc, Out, STI)) 4310 return true; 4311 } 4312 4313 int64_t FirstOffset = IsLargeOffset ? 1 : (OffsetValue + 1); 4314 int64_t SecondOffset = IsLargeOffset ? 0 : OffsetValue; 4315 if (isLittle()) 4316 std::swap(FirstOffset, SecondOffset); 4317 4318 if (IsLargeOffset) { 4319 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); 4320 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); 4321 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); 4322 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI); 4323 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); 4324 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); 4325 } else { 4326 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); 4327 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); 4328 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI); 4329 } 4330 4331 return false; 4332 } 4333 4334 bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4335 const MCSubtargetInfo *STI) { 4336 if (hasMips32r6() || hasMips64r6()) { 4337 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); 4338 } 4339 4340 const MCOperand &DstRegOp = Inst.getOperand(0); 4341 assert(DstRegOp.isReg() && "expected register operand kind"); 4342 const MCOperand &SrcRegOp = Inst.getOperand(1); 4343 assert(SrcRegOp.isReg() && "expected register operand kind"); 4344 const MCOperand &OffsetImmOp = Inst.getOperand(2); 4345 assert(OffsetImmOp.isImm() && "expected immediate operand kind"); 4346 4347 MipsTargetStreamer &TOut = getTargetStreamer(); 4348 unsigned DstReg = DstRegOp.getReg(); 4349 unsigned SrcReg = SrcRegOp.getReg(); 4350 int64_t OffsetValue = OffsetImmOp.getImm(); 4351 4352 // Compute left/right load/store offsets. 4353 bool IsLargeOffset = !(isInt<16>(OffsetValue + 3) && isInt<16>(OffsetValue)); 4354 int64_t LxlOffset = IsLargeOffset ? 0 : OffsetValue; 4355 int64_t LxrOffset = IsLargeOffset ? 3 : (OffsetValue + 3); 4356 if (isLittle()) 4357 std::swap(LxlOffset, LxrOffset); 4358 4359 bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw); 4360 bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset; 4361 unsigned TmpReg = SrcReg; 4362 if (IsLargeOffset || DoMove) { 4363 warnIfNoMacro(IDLoc); 4364 TmpReg = getATReg(IDLoc); 4365 if (!TmpReg) 4366 return true; 4367 } 4368 4369 if (IsLargeOffset) { 4370 if (loadImmediate(OffsetValue, TmpReg, SrcReg, !ABI.ArePtrs64bit(), true, 4371 IDLoc, Out, STI)) 4372 return true; 4373 } 4374 4375 if (DoMove) 4376 std::swap(DstReg, TmpReg); 4377 4378 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; 4379 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; 4380 TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI); 4381 TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI); 4382 4383 if (DoMove) 4384 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); 4385 4386 return false; 4387 } 4388 4389 bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4390 const MCSubtargetInfo *STI) { 4391 MipsTargetStreamer &TOut = getTargetStreamer(); 4392 4393 assert(Inst.getNumOperands() == 3 && "Invalid operand count"); 4394 assert(Inst.getOperand(0).isReg() && 4395 Inst.getOperand(1).isReg() && 4396 Inst.getOperand(2).isReg() && "Invalid instruction operand."); 4397 4398 unsigned DstReg = Inst.getOperand(0).getReg(); 4399 unsigned SrcReg = Inst.getOperand(1).getReg(); 4400 unsigned OpReg = Inst.getOperand(2).getReg(); 4401 unsigned OpCode; 4402 4403 warnIfNoMacro(IDLoc); 4404 4405 switch (Inst.getOpcode()) { 4406 case Mips::SGE: 4407 OpCode = Mips::SLT; 4408 break; 4409 case Mips::SGEU: 4410 OpCode = Mips::SLTu; 4411 break; 4412 default: 4413 llvm_unreachable("unexpected 'sge' opcode"); 4414 } 4415 4416 // $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg)) 4417 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); 4418 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); 4419 4420 return false; 4421 } 4422 4423 bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4424 const MCSubtargetInfo *STI) { 4425 MipsTargetStreamer &TOut = getTargetStreamer(); 4426 4427 assert(Inst.getNumOperands() == 3 && "Invalid operand count"); 4428 assert(Inst.getOperand(0).isReg() && 4429 Inst.getOperand(1).isReg() && 4430 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 4431 4432 unsigned DstReg = Inst.getOperand(0).getReg(); 4433 unsigned SrcReg = Inst.getOperand(1).getReg(); 4434 int64_t ImmValue = Inst.getOperand(2).getImm(); 4435 unsigned OpRegCode, OpImmCode; 4436 4437 warnIfNoMacro(IDLoc); 4438 4439 switch (Inst.getOpcode()) { 4440 case Mips::SGEImm: 4441 case Mips::SGEImm64: 4442 OpRegCode = Mips::SLT; 4443 OpImmCode = Mips::SLTi; 4444 break; 4445 case Mips::SGEUImm: 4446 case Mips::SGEUImm64: 4447 OpRegCode = Mips::SLTu; 4448 OpImmCode = Mips::SLTiu; 4449 break; 4450 default: 4451 llvm_unreachable("unexpected 'sge' opcode with immediate"); 4452 } 4453 4454 // $SrcReg >= Imm is equal to (not ($SrcReg < Imm)) 4455 if (isInt<16>(ImmValue)) { 4456 // Use immediate version of STL. 4457 TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI); 4458 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); 4459 } else { 4460 unsigned ImmReg = DstReg; 4461 if (DstReg == SrcReg) { 4462 unsigned ATReg = getATReg(Inst.getLoc()); 4463 if (!ATReg) 4464 return true; 4465 ImmReg = ATReg; 4466 } 4467 4468 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), 4469 false, IDLoc, Out, STI)) 4470 return true; 4471 4472 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI); 4473 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); 4474 } 4475 4476 return false; 4477 } 4478 4479 bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4480 const MCSubtargetInfo *STI) { 4481 MipsTargetStreamer &TOut = getTargetStreamer(); 4482 4483 assert(Inst.getNumOperands() == 3 && "Invalid operand count"); 4484 assert(Inst.getOperand(0).isReg() && 4485 Inst.getOperand(1).isReg() && 4486 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 4487 4488 unsigned DstReg = Inst.getOperand(0).getReg(); 4489 unsigned SrcReg = Inst.getOperand(1).getReg(); 4490 unsigned ImmReg = DstReg; 4491 int64_t ImmValue = Inst.getOperand(2).getImm(); 4492 unsigned OpCode; 4493 4494 warnIfNoMacro(IDLoc); 4495 4496 switch (Inst.getOpcode()) { 4497 case Mips::SGTImm: 4498 case Mips::SGTImm64: 4499 OpCode = Mips::SLT; 4500 break; 4501 case Mips::SGTUImm: 4502 case Mips::SGTUImm64: 4503 OpCode = Mips::SLTu; 4504 break; 4505 default: 4506 llvm_unreachable("unexpected 'sgt' opcode with immediate"); 4507 } 4508 4509 if (DstReg == SrcReg) { 4510 unsigned ATReg = getATReg(Inst.getLoc()); 4511 if (!ATReg) 4512 return true; 4513 ImmReg = ATReg; 4514 } 4515 4516 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), 4517 false, IDLoc, Out, STI)) 4518 return true; 4519 4520 // $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg 4521 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI); 4522 4523 return false; 4524 } 4525 4526 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, 4527 MCStreamer &Out, 4528 const MCSubtargetInfo *STI) { 4529 MipsTargetStreamer &TOut = getTargetStreamer(); 4530 4531 assert(Inst.getNumOperands() == 3 && "Invalid operand count"); 4532 assert(Inst.getOperand(0).isReg() && 4533 Inst.getOperand(1).isReg() && 4534 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 4535 4536 unsigned ATReg = Mips::NoRegister; 4537 unsigned FinalDstReg = Mips::NoRegister; 4538 unsigned DstReg = Inst.getOperand(0).getReg(); 4539 unsigned SrcReg = Inst.getOperand(1).getReg(); 4540 int64_t ImmValue = Inst.getOperand(2).getImm(); 4541 4542 bool Is32Bit = isInt<32>(ImmValue) || (!isGP64bit() && isUInt<32>(ImmValue)); 4543 4544 unsigned FinalOpcode = Inst.getOpcode(); 4545 4546 if (DstReg == SrcReg) { 4547 ATReg = getATReg(Inst.getLoc()); 4548 if (!ATReg) 4549 return true; 4550 FinalDstReg = DstReg; 4551 DstReg = ATReg; 4552 } 4553 4554 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, 4555 Inst.getLoc(), Out, STI)) { 4556 switch (FinalOpcode) { 4557 default: 4558 llvm_unreachable("unimplemented expansion"); 4559 case Mips::ADDi: 4560 FinalOpcode = Mips::ADD; 4561 break; 4562 case Mips::ADDiu: 4563 FinalOpcode = Mips::ADDu; 4564 break; 4565 case Mips::ANDi: 4566 FinalOpcode = Mips::AND; 4567 break; 4568 case Mips::NORImm: 4569 FinalOpcode = Mips::NOR; 4570 break; 4571 case Mips::ORi: 4572 FinalOpcode = Mips::OR; 4573 break; 4574 case Mips::SLTi: 4575 FinalOpcode = Mips::SLT; 4576 break; 4577 case Mips::SLTiu: 4578 FinalOpcode = Mips::SLTu; 4579 break; 4580 case Mips::XORi: 4581 FinalOpcode = Mips::XOR; 4582 break; 4583 case Mips::ADDi_MM: 4584 FinalOpcode = Mips::ADD_MM; 4585 break; 4586 case Mips::ADDiu_MM: 4587 FinalOpcode = Mips::ADDu_MM; 4588 break; 4589 case Mips::ANDi_MM: 4590 FinalOpcode = Mips::AND_MM; 4591 break; 4592 case Mips::ORi_MM: 4593 FinalOpcode = Mips::OR_MM; 4594 break; 4595 case Mips::SLTi_MM: 4596 FinalOpcode = Mips::SLT_MM; 4597 break; 4598 case Mips::SLTiu_MM: 4599 FinalOpcode = Mips::SLTu_MM; 4600 break; 4601 case Mips::XORi_MM: 4602 FinalOpcode = Mips::XOR_MM; 4603 break; 4604 case Mips::ANDi64: 4605 FinalOpcode = Mips::AND64; 4606 break; 4607 case Mips::NORImm64: 4608 FinalOpcode = Mips::NOR64; 4609 break; 4610 case Mips::ORi64: 4611 FinalOpcode = Mips::OR64; 4612 break; 4613 case Mips::SLTImm64: 4614 FinalOpcode = Mips::SLT64; 4615 break; 4616 case Mips::SLTUImm64: 4617 FinalOpcode = Mips::SLTu64; 4618 break; 4619 case Mips::XORi64: 4620 FinalOpcode = Mips::XOR64; 4621 break; 4622 } 4623 4624 if (FinalDstReg == Mips::NoRegister) 4625 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); 4626 else 4627 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); 4628 return false; 4629 } 4630 return true; 4631 } 4632 4633 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4634 const MCSubtargetInfo *STI) { 4635 MipsTargetStreamer &TOut = getTargetStreamer(); 4636 unsigned ATReg = Mips::NoRegister; 4637 unsigned DReg = Inst.getOperand(0).getReg(); 4638 unsigned SReg = Inst.getOperand(1).getReg(); 4639 unsigned TReg = Inst.getOperand(2).getReg(); 4640 unsigned TmpReg = DReg; 4641 4642 unsigned FirstShift = Mips::NOP; 4643 unsigned SecondShift = Mips::NOP; 4644 4645 if (hasMips32r2()) { 4646 if (DReg == SReg) { 4647 TmpReg = getATReg(Inst.getLoc()); 4648 if (!TmpReg) 4649 return true; 4650 } 4651 4652 if (Inst.getOpcode() == Mips::ROL) { 4653 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); 4654 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); 4655 return false; 4656 } 4657 4658 if (Inst.getOpcode() == Mips::ROR) { 4659 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); 4660 return false; 4661 } 4662 4663 return true; 4664 } 4665 4666 if (hasMips32()) { 4667 switch (Inst.getOpcode()) { 4668 default: 4669 llvm_unreachable("unexpected instruction opcode"); 4670 case Mips::ROL: 4671 FirstShift = Mips::SRLV; 4672 SecondShift = Mips::SLLV; 4673 break; 4674 case Mips::ROR: 4675 FirstShift = Mips::SLLV; 4676 SecondShift = Mips::SRLV; 4677 break; 4678 } 4679 4680 ATReg = getATReg(Inst.getLoc()); 4681 if (!ATReg) 4682 return true; 4683 4684 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); 4685 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); 4686 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); 4687 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); 4688 4689 return false; 4690 } 4691 4692 return true; 4693 } 4694 4695 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, 4696 MCStreamer &Out, 4697 const MCSubtargetInfo *STI) { 4698 MipsTargetStreamer &TOut = getTargetStreamer(); 4699 unsigned ATReg = Mips::NoRegister; 4700 unsigned DReg = Inst.getOperand(0).getReg(); 4701 unsigned SReg = Inst.getOperand(1).getReg(); 4702 int64_t ImmValue = Inst.getOperand(2).getImm(); 4703 4704 unsigned FirstShift = Mips::NOP; 4705 unsigned SecondShift = Mips::NOP; 4706 4707 if (hasMips32r2()) { 4708 if (Inst.getOpcode() == Mips::ROLImm) { 4709 uint64_t MaxShift = 32; 4710 uint64_t ShiftValue = ImmValue; 4711 if (ImmValue != 0) 4712 ShiftValue = MaxShift - ImmValue; 4713 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); 4714 return false; 4715 } 4716 4717 if (Inst.getOpcode() == Mips::RORImm) { 4718 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); 4719 return false; 4720 } 4721 4722 return true; 4723 } 4724 4725 if (hasMips32()) { 4726 if (ImmValue == 0) { 4727 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); 4728 return false; 4729 } 4730 4731 switch (Inst.getOpcode()) { 4732 default: 4733 llvm_unreachable("unexpected instruction opcode"); 4734 case Mips::ROLImm: 4735 FirstShift = Mips::SLL; 4736 SecondShift = Mips::SRL; 4737 break; 4738 case Mips::RORImm: 4739 FirstShift = Mips::SRL; 4740 SecondShift = Mips::SLL; 4741 break; 4742 } 4743 4744 ATReg = getATReg(Inst.getLoc()); 4745 if (!ATReg) 4746 return true; 4747 4748 TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), STI); 4749 TOut.emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), STI); 4750 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); 4751 4752 return false; 4753 } 4754 4755 return true; 4756 } 4757 4758 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4759 const MCSubtargetInfo *STI) { 4760 MipsTargetStreamer &TOut = getTargetStreamer(); 4761 unsigned ATReg = Mips::NoRegister; 4762 unsigned DReg = Inst.getOperand(0).getReg(); 4763 unsigned SReg = Inst.getOperand(1).getReg(); 4764 unsigned TReg = Inst.getOperand(2).getReg(); 4765 unsigned TmpReg = DReg; 4766 4767 unsigned FirstShift = Mips::NOP; 4768 unsigned SecondShift = Mips::NOP; 4769 4770 if (hasMips64r2()) { 4771 if (TmpReg == SReg) { 4772 TmpReg = getATReg(Inst.getLoc()); 4773 if (!TmpReg) 4774 return true; 4775 } 4776 4777 if (Inst.getOpcode() == Mips::DROL) { 4778 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); 4779 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); 4780 return false; 4781 } 4782 4783 if (Inst.getOpcode() == Mips::DROR) { 4784 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); 4785 return false; 4786 } 4787 4788 return true; 4789 } 4790 4791 if (hasMips64()) { 4792 switch (Inst.getOpcode()) { 4793 default: 4794 llvm_unreachable("unexpected instruction opcode"); 4795 case Mips::DROL: 4796 FirstShift = Mips::DSRLV; 4797 SecondShift = Mips::DSLLV; 4798 break; 4799 case Mips::DROR: 4800 FirstShift = Mips::DSLLV; 4801 SecondShift = Mips::DSRLV; 4802 break; 4803 } 4804 4805 ATReg = getATReg(Inst.getLoc()); 4806 if (!ATReg) 4807 return true; 4808 4809 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); 4810 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); 4811 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); 4812 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); 4813 4814 return false; 4815 } 4816 4817 return true; 4818 } 4819 4820 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, 4821 MCStreamer &Out, 4822 const MCSubtargetInfo *STI) { 4823 MipsTargetStreamer &TOut = getTargetStreamer(); 4824 unsigned ATReg = Mips::NoRegister; 4825 unsigned DReg = Inst.getOperand(0).getReg(); 4826 unsigned SReg = Inst.getOperand(1).getReg(); 4827 int64_t ImmValue = Inst.getOperand(2).getImm() % 64; 4828 4829 unsigned FirstShift = Mips::NOP; 4830 unsigned SecondShift = Mips::NOP; 4831 4832 MCInst TmpInst; 4833 4834 if (hasMips64r2()) { 4835 unsigned FinalOpcode = Mips::NOP; 4836 if (ImmValue == 0) 4837 FinalOpcode = Mips::DROTR; 4838 else if (ImmValue % 32 == 0) 4839 FinalOpcode = Mips::DROTR32; 4840 else if ((ImmValue >= 1) && (ImmValue <= 32)) { 4841 if (Inst.getOpcode() == Mips::DROLImm) 4842 FinalOpcode = Mips::DROTR32; 4843 else 4844 FinalOpcode = Mips::DROTR; 4845 } else if (ImmValue >= 33) { 4846 if (Inst.getOpcode() == Mips::DROLImm) 4847 FinalOpcode = Mips::DROTR; 4848 else 4849 FinalOpcode = Mips::DROTR32; 4850 } 4851 4852 uint64_t ShiftValue = ImmValue % 32; 4853 if (Inst.getOpcode() == Mips::DROLImm) 4854 ShiftValue = (32 - ImmValue % 32) % 32; 4855 4856 TOut.emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), STI); 4857 4858 return false; 4859 } 4860 4861 if (hasMips64()) { 4862 if (ImmValue == 0) { 4863 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); 4864 return false; 4865 } 4866 4867 switch (Inst.getOpcode()) { 4868 default: 4869 llvm_unreachable("unexpected instruction opcode"); 4870 case Mips::DROLImm: 4871 if ((ImmValue >= 1) && (ImmValue <= 31)) { 4872 FirstShift = Mips::DSLL; 4873 SecondShift = Mips::DSRL32; 4874 } 4875 if (ImmValue == 32) { 4876 FirstShift = Mips::DSLL32; 4877 SecondShift = Mips::DSRL32; 4878 } 4879 if ((ImmValue >= 33) && (ImmValue <= 63)) { 4880 FirstShift = Mips::DSLL32; 4881 SecondShift = Mips::DSRL; 4882 } 4883 break; 4884 case Mips::DRORImm: 4885 if ((ImmValue >= 1) && (ImmValue <= 31)) { 4886 FirstShift = Mips::DSRL; 4887 SecondShift = Mips::DSLL32; 4888 } 4889 if (ImmValue == 32) { 4890 FirstShift = Mips::DSRL32; 4891 SecondShift = Mips::DSLL32; 4892 } 4893 if ((ImmValue >= 33) && (ImmValue <= 63)) { 4894 FirstShift = Mips::DSRL32; 4895 SecondShift = Mips::DSLL; 4896 } 4897 break; 4898 } 4899 4900 ATReg = getATReg(Inst.getLoc()); 4901 if (!ATReg) 4902 return true; 4903 4904 TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), STI); 4905 TOut.emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32, 4906 Inst.getLoc(), STI); 4907 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); 4908 4909 return false; 4910 } 4911 4912 return true; 4913 } 4914 4915 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4916 const MCSubtargetInfo *STI) { 4917 MipsTargetStreamer &TOut = getTargetStreamer(); 4918 unsigned FirstRegOp = Inst.getOperand(0).getReg(); 4919 unsigned SecondRegOp = Inst.getOperand(1).getReg(); 4920 4921 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); 4922 if (FirstRegOp != SecondRegOp) 4923 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); 4924 else 4925 TOut.emitEmptyDelaySlot(false, IDLoc, STI); 4926 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI); 4927 4928 return false; 4929 } 4930 4931 bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4932 const MCSubtargetInfo *STI) { 4933 MipsTargetStreamer &TOut = getTargetStreamer(); 4934 unsigned ATReg = Mips::NoRegister; 4935 unsigned DstReg = Inst.getOperand(0).getReg(); 4936 unsigned SrcReg = Inst.getOperand(1).getReg(); 4937 int32_t ImmValue = Inst.getOperand(2).getImm(); 4938 4939 ATReg = getATReg(IDLoc); 4940 if (!ATReg) 4941 return true; 4942 4943 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, 4944 STI); 4945 4946 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, 4947 SrcReg, ATReg, IDLoc, STI); 4948 4949 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); 4950 4951 return false; 4952 } 4953 4954 bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4955 const MCSubtargetInfo *STI) { 4956 MipsTargetStreamer &TOut = getTargetStreamer(); 4957 unsigned ATReg = Mips::NoRegister; 4958 unsigned DstReg = Inst.getOperand(0).getReg(); 4959 unsigned SrcReg = Inst.getOperand(1).getReg(); 4960 unsigned TmpReg = Inst.getOperand(2).getReg(); 4961 4962 ATReg = getATReg(Inst.getLoc()); 4963 if (!ATReg) 4964 return true; 4965 4966 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT, 4967 SrcReg, TmpReg, IDLoc, STI); 4968 4969 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); 4970 4971 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, 4972 DstReg, DstReg, 0x1F, IDLoc, STI); 4973 4974 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); 4975 4976 if (useTraps()) { 4977 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); 4978 } else { 4979 MCContext & Context = TOut.getStreamer().getContext(); 4980 MCSymbol * BrTarget = Context.createTempSymbol(); 4981 MCOperand LabelOp = 4982 MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context)); 4983 4984 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); 4985 if (AssemblerOptions.back()->isReorder()) 4986 TOut.emitNop(IDLoc, STI); 4987 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); 4988 4989 TOut.getStreamer().EmitLabel(BrTarget); 4990 } 4991 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); 4992 4993 return false; 4994 } 4995 4996 bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 4997 const MCSubtargetInfo *STI) { 4998 MipsTargetStreamer &TOut = getTargetStreamer(); 4999 unsigned ATReg = Mips::NoRegister; 5000 unsigned DstReg = Inst.getOperand(0).getReg(); 5001 unsigned SrcReg = Inst.getOperand(1).getReg(); 5002 unsigned TmpReg = Inst.getOperand(2).getReg(); 5003 5004 ATReg = getATReg(IDLoc); 5005 if (!ATReg) 5006 return true; 5007 5008 TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu, 5009 SrcReg, TmpReg, IDLoc, STI); 5010 5011 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); 5012 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); 5013 if (useTraps()) { 5014 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); 5015 } else { 5016 MCContext & Context = TOut.getStreamer().getContext(); 5017 MCSymbol * BrTarget = Context.createTempSymbol(); 5018 MCOperand LabelOp = 5019 MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context)); 5020 5021 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI); 5022 if (AssemblerOptions.back()->isReorder()) 5023 TOut.emitNop(IDLoc, STI); 5024 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); 5025 5026 TOut.getStreamer().EmitLabel(BrTarget); 5027 } 5028 5029 return false; 5030 } 5031 5032 bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 5033 const MCSubtargetInfo *STI) { 5034 MipsTargetStreamer &TOut = getTargetStreamer(); 5035 unsigned DstReg = Inst.getOperand(0).getReg(); 5036 unsigned SrcReg = Inst.getOperand(1).getReg(); 5037 unsigned TmpReg = Inst.getOperand(2).getReg(); 5038 5039 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); 5040 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); 5041 5042 return false; 5043 } 5044 5045 // Expand 'ld $<reg> offset($reg2)' to 'lw $<reg>, offset($reg2); 5046 // lw $<reg+1>>, offset+4($reg2)' 5047 // or expand 'sd $<reg> offset($reg2)' to 'sw $<reg>, offset($reg2); 5048 // sw $<reg+1>>, offset+4($reg2)' 5049 // for O32. 5050 bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, 5051 MCStreamer &Out, 5052 const MCSubtargetInfo *STI, 5053 bool IsLoad) { 5054 if (!isABI_O32()) 5055 return true; 5056 5057 warnIfNoMacro(IDLoc); 5058 5059 MipsTargetStreamer &TOut = getTargetStreamer(); 5060 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW; 5061 unsigned FirstReg = Inst.getOperand(0).getReg(); 5062 unsigned SecondReg = nextReg(FirstReg); 5063 unsigned BaseReg = Inst.getOperand(1).getReg(); 5064 if (!SecondReg) 5065 return true; 5066 5067 warnIfRegIndexIsAT(FirstReg, IDLoc); 5068 5069 assert(Inst.getOperand(2).isImm() && 5070 "Offset for load macro is not immediate!"); 5071 5072 MCOperand &FirstOffset = Inst.getOperand(2); 5073 signed NextOffset = FirstOffset.getImm() + 4; 5074 MCOperand SecondOffset = MCOperand::createImm(NextOffset); 5075 5076 if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset)) 5077 return true; 5078 5079 // For loads, clobber the base register with the second load instead of the 5080 // first if the BaseReg == FirstReg. 5081 if (FirstReg != BaseReg || !IsLoad) { 5082 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); 5083 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); 5084 } else { 5085 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); 5086 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); 5087 } 5088 5089 return false; 5090 } 5091 5092 5093 // Expand 's.d $<reg> offset($reg2)' to 'swc1 $<reg+1>, offset($reg2); 5094 // swc1 $<reg>, offset+4($reg2)' 5095 // or if little endian to 'swc1 $<reg>, offset($reg2); 5096 // swc1 $<reg+1>, offset+4($reg2)' 5097 // for Mips1. 5098 bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, 5099 MCStreamer &Out, 5100 const MCSubtargetInfo *STI) { 5101 if (!isABI_O32()) 5102 return true; 5103 5104 warnIfNoMacro(IDLoc); 5105 5106 MipsTargetStreamer &TOut = getTargetStreamer(); 5107 unsigned Opcode = Mips::SWC1; 5108 unsigned FirstReg = Inst.getOperand(0).getReg(); 5109 unsigned SecondReg = nextReg(FirstReg); 5110 unsigned BaseReg = Inst.getOperand(1).getReg(); 5111 if (!SecondReg) 5112 return true; 5113 5114 warnIfRegIndexIsAT(FirstReg, IDLoc); 5115 5116 assert(Inst.getOperand(2).isImm() && 5117 "Offset for macro is not immediate!"); 5118 5119 MCOperand &FirstOffset = Inst.getOperand(2); 5120 signed NextOffset = FirstOffset.getImm() + 4; 5121 MCOperand SecondOffset = MCOperand::createImm(NextOffset); 5122 5123 if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset)) 5124 return true; 5125 5126 if (!IsLittleEndian) 5127 std::swap(FirstReg, SecondReg); 5128 5129 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); 5130 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); 5131 5132 return false; 5133 } 5134 5135 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 5136 const MCSubtargetInfo *STI) { 5137 MipsTargetStreamer &TOut = getTargetStreamer(); 5138 5139 assert(Inst.getNumOperands() == 3 && "Invalid operand count"); 5140 assert(Inst.getOperand(0).isReg() && 5141 Inst.getOperand(1).isReg() && 5142 Inst.getOperand(2).isReg() && "Invalid instruction operand."); 5143 5144 unsigned DstReg = Inst.getOperand(0).getReg(); 5145 unsigned SrcReg = Inst.getOperand(1).getReg(); 5146 unsigned OpReg = Inst.getOperand(2).getReg(); 5147 5148 warnIfNoMacro(IDLoc); 5149 5150 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { 5151 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); 5152 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); 5153 return false; 5154 } 5155 5156 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; 5157 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); 5158 return false; 5159 } 5160 5161 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 5162 const MCSubtargetInfo *STI) { 5163 MipsTargetStreamer &TOut = getTargetStreamer(); 5164 5165 assert(Inst.getNumOperands() == 3 && "Invalid operand count"); 5166 assert(Inst.getOperand(0).isReg() && 5167 Inst.getOperand(1).isReg() && 5168 Inst.getOperand(2).isImm() && "Invalid instruction operand."); 5169 5170 unsigned DstReg = Inst.getOperand(0).getReg(); 5171 unsigned SrcReg = Inst.getOperand(1).getReg(); 5172 int64_t Imm = Inst.getOperand(2).getImm(); 5173 5174 warnIfNoMacro(IDLoc); 5175 5176 if (Imm == 0) { 5177 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI); 5178 return false; 5179 } 5180 5181 if (SrcReg == Mips::ZERO) { 5182 Warning(IDLoc, "comparison is always false"); 5183 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, 5184 DstReg, SrcReg, SrcReg, IDLoc, STI); 5185 return false; 5186 } 5187 5188 unsigned Opc; 5189 if (Imm > -0x8000 && Imm < 0) { 5190 Imm = -Imm; 5191 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; 5192 } else { 5193 Opc = Mips::XORi; 5194 } 5195 5196 if (!isUInt<16>(Imm)) { 5197 unsigned ATReg = getATReg(IDLoc); 5198 if (!ATReg) 5199 return true; 5200 5201 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, 5202 Out, STI)) 5203 return true; 5204 5205 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); 5206 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); 5207 return false; 5208 } 5209 5210 TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI); 5211 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); 5212 return false; 5213 } 5214 5215 // Map the DSP accumulator and control register to the corresponding gpr 5216 // operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions 5217 // do not map the DSP registers contigously to gpr registers. 5218 static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) { 5219 switch (Inst.getOpcode()) { 5220 case Mips::MFTLO: 5221 case Mips::MTTLO: 5222 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { 5223 case Mips::AC0: 5224 return Mips::ZERO; 5225 case Mips::AC1: 5226 return Mips::A0; 5227 case Mips::AC2: 5228 return Mips::T0; 5229 case Mips::AC3: 5230 return Mips::T4; 5231 default: 5232 llvm_unreachable("Unknown register for 'mttr' alias!"); 5233 } 5234 case Mips::MFTHI: 5235 case Mips::MTTHI: 5236 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { 5237 case Mips::AC0: 5238 return Mips::AT; 5239 case Mips::AC1: 5240 return Mips::A1; 5241 case Mips::AC2: 5242 return Mips::T1; 5243 case Mips::AC3: 5244 return Mips::T5; 5245 default: 5246 llvm_unreachable("Unknown register for 'mttr' alias!"); 5247 } 5248 case Mips::MFTACX: 5249 case Mips::MTTACX: 5250 switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { 5251 case Mips::AC0: 5252 return Mips::V0; 5253 case Mips::AC1: 5254 return Mips::A2; 5255 case Mips::AC2: 5256 return Mips::T2; 5257 case Mips::AC3: 5258 return Mips::T6; 5259 default: 5260 llvm_unreachable("Unknown register for 'mttr' alias!"); 5261 } 5262 case Mips::MFTDSP: 5263 case Mips::MTTDSP: 5264 return Mips::S0; 5265 default: 5266 llvm_unreachable("Unknown instruction for 'mttr' dsp alias!"); 5267 } 5268 } 5269 5270 // Map the floating point register operand to the corresponding register 5271 // operand. 5272 static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) { 5273 switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) { 5274 case Mips::F0: return Mips::ZERO; 5275 case Mips::F1: return Mips::AT; 5276 case Mips::F2: return Mips::V0; 5277 case Mips::F3: return Mips::V1; 5278 case Mips::F4: return Mips::A0; 5279 case Mips::F5: return Mips::A1; 5280 case Mips::F6: return Mips::A2; 5281 case Mips::F7: return Mips::A3; 5282 case Mips::F8: return Mips::T0; 5283 case Mips::F9: return Mips::T1; 5284 case Mips::F10: return Mips::T2; 5285 case Mips::F11: return Mips::T3; 5286 case Mips::F12: return Mips::T4; 5287 case Mips::F13: return Mips::T5; 5288 case Mips::F14: return Mips::T6; 5289 case Mips::F15: return Mips::T7; 5290 case Mips::F16: return Mips::S0; 5291 case Mips::F17: return Mips::S1; 5292 case Mips::F18: return Mips::S2; 5293 case Mips::F19: return Mips::S3; 5294 case Mips::F20: return Mips::S4; 5295 case Mips::F21: return Mips::S5; 5296 case Mips::F22: return Mips::S6; 5297 case Mips::F23: return Mips::S7; 5298 case Mips::F24: return Mips::T8; 5299 case Mips::F25: return Mips::T9; 5300 case Mips::F26: return Mips::K0; 5301 case Mips::F27: return Mips::K1; 5302 case Mips::F28: return Mips::GP; 5303 case Mips::F29: return Mips::SP; 5304 case Mips::F30: return Mips::FP; 5305 case Mips::F31: return Mips::RA; 5306 default: llvm_unreachable("Unknown register for mttc1 alias!"); 5307 } 5308 } 5309 5310 // Map the coprocessor operand the corresponding gpr register operand. 5311 static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) { 5312 switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) { 5313 case Mips::COP00: return Mips::ZERO; 5314 case Mips::COP01: return Mips::AT; 5315 case Mips::COP02: return Mips::V0; 5316 case Mips::COP03: return Mips::V1; 5317 case Mips::COP04: return Mips::A0; 5318 case Mips::COP05: return Mips::A1; 5319 case Mips::COP06: return Mips::A2; 5320 case Mips::COP07: return Mips::A3; 5321 case Mips::COP08: return Mips::T0; 5322 case Mips::COP09: return Mips::T1; 5323 case Mips::COP010: return Mips::T2; 5324 case Mips::COP011: return Mips::T3; 5325 case Mips::COP012: return Mips::T4; 5326 case Mips::COP013: return Mips::T5; 5327 case Mips::COP014: return Mips::T6; 5328 case Mips::COP015: return Mips::T7; 5329 case Mips::COP016: return Mips::S0; 5330 case Mips::COP017: return Mips::S1; 5331 case Mips::COP018: return Mips::S2; 5332 case Mips::COP019: return Mips::S3; 5333 case Mips::COP020: return Mips::S4; 5334 case Mips::COP021: return Mips::S5; 5335 case Mips::COP022: return Mips::S6; 5336 case Mips::COP023: return Mips::S7; 5337 case Mips::COP024: return Mips::T8; 5338 case Mips::COP025: return Mips::T9; 5339 case Mips::COP026: return Mips::K0; 5340 case Mips::COP027: return Mips::K1; 5341 case Mips::COP028: return Mips::GP; 5342 case Mips::COP029: return Mips::SP; 5343 case Mips::COP030: return Mips::FP; 5344 case Mips::COP031: return Mips::RA; 5345 default: llvm_unreachable("Unknown register for mttc0 alias!"); 5346 } 5347 } 5348 5349 /// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing 5350 /// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits. 5351 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 5352 const MCSubtargetInfo *STI) { 5353 MipsTargetStreamer &TOut = getTargetStreamer(); 5354 unsigned rd = 0; 5355 unsigned u = 1; 5356 unsigned sel = 0; 5357 unsigned h = 0; 5358 bool IsMFTR = false; 5359 switch (Inst.getOpcode()) { 5360 case Mips::MFTC0: 5361 IsMFTR = true; 5362 LLVM_FALLTHROUGH; 5363 case Mips::MTTC0: 5364 u = 0; 5365 rd = getRegisterForMxtrC0(Inst, IsMFTR); 5366 sel = Inst.getOperand(2).getImm(); 5367 break; 5368 case Mips::MFTGPR: 5369 IsMFTR = true; 5370 LLVM_FALLTHROUGH; 5371 case Mips::MTTGPR: 5372 rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg(); 5373 break; 5374 case Mips::MFTLO: 5375 case Mips::MFTHI: 5376 case Mips::MFTACX: 5377 case Mips::MFTDSP: 5378 IsMFTR = true; 5379 LLVM_FALLTHROUGH; 5380 case Mips::MTTLO: 5381 case Mips::MTTHI: 5382 case Mips::MTTACX: 5383 case Mips::MTTDSP: 5384 rd = getRegisterForMxtrDSP(Inst, IsMFTR); 5385 sel = 1; 5386 break; 5387 case Mips::MFTHC1: 5388 h = 1; 5389 LLVM_FALLTHROUGH; 5390 case Mips::MFTC1: 5391 IsMFTR = true; 5392 rd = getRegisterForMxtrFP(Inst, IsMFTR); 5393 sel = 2; 5394 break; 5395 case Mips::MTTHC1: 5396 h = 1; 5397 LLVM_FALLTHROUGH; 5398 case Mips::MTTC1: 5399 rd = getRegisterForMxtrFP(Inst, IsMFTR); 5400 sel = 2; 5401 break; 5402 case Mips::CFTC1: 5403 IsMFTR = true; 5404 LLVM_FALLTHROUGH; 5405 case Mips::CTTC1: 5406 rd = getRegisterForMxtrFP(Inst, IsMFTR); 5407 sel = 3; 5408 break; 5409 } 5410 unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd; 5411 unsigned Op1 = 5412 IsMFTR ? rd 5413 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg() 5414 : Inst.getOperand(0).getReg()); 5415 5416 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc, 5417 STI); 5418 return false; 5419 } 5420 5421 bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, 5422 const MCSubtargetInfo *STI) { 5423 assert(Inst.getNumOperands() == 3 && "expected three operands"); 5424 assert(Inst.getOperand(0).isReg() && "expected register operand kind"); 5425 assert(Inst.getOperand(1).isReg() && "expected register operand kind"); 5426 5427 warnIfNoMacro(IDLoc); 5428 5429 MipsTargetStreamer &TOut = getTargetStreamer(); 5430 unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD; 5431 unsigned RtReg = Inst.getOperand(0).getReg(); 5432 unsigned BaseReg = Inst.getOperand(1).getReg(); 5433 const MCOperand &BaseOp = Inst.getOperand(2); 5434 5435 if (BaseOp.isImm()) { 5436 int64_t ImmValue = BaseOp.getImm(); 5437 if (ImmValue == 0) { 5438 TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI); 5439 return false; 5440 } 5441 } 5442 5443 unsigned ATReg = getATReg(IDLoc); 5444 if (!ATReg) 5445 return true; 5446 5447 if (expandLoadAddress(ATReg, BaseReg, BaseOp, !isGP64bit(), IDLoc, Out, STI)) 5448 return true; 5449 5450 TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI); 5451 return false; 5452 } 5453 5454 unsigned 5455 MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst, 5456 const OperandVector &Operands) { 5457 switch (Inst.getOpcode()) { 5458 default: 5459 return Match_Success; 5460 case Mips::DATI: 5461 case Mips::DAHI: 5462 if (static_cast<MipsOperand &>(*Operands[1]) 5463 .isValidForTie(static_cast<MipsOperand &>(*Operands[2]))) 5464 return Match_Success; 5465 return Match_RequiresSameSrcAndDst; 5466 } 5467 } 5468 5469 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 5470 switch (Inst.getOpcode()) { 5471 // As described by the MIPSR6 spec, daui must not use the zero operand for 5472 // its source operand. 5473 case Mips::DAUI: 5474 if (Inst.getOperand(1).getReg() == Mips::ZERO || 5475 Inst.getOperand(1).getReg() == Mips::ZERO_64) 5476 return Match_RequiresNoZeroRegister; 5477 return Match_Success; 5478 // As described by the Mips32r2 spec, the registers Rd and Rs for 5479 // jalr.hb must be different. 5480 // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction 5481 // and registers Rd and Base for microMIPS lwp instruction 5482 case Mips::JALR_HB: 5483 case Mips::JALR_HB64: 5484 case Mips::JALRC_HB_MMR6: 5485 case Mips::JALRC_MMR6: 5486 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) 5487 return Match_RequiresDifferentSrcAndDst; 5488 return Match_Success; 5489 case Mips::LWP_MM: 5490 if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) 5491 return Match_RequiresDifferentSrcAndDst; 5492 return Match_Success; 5493 case Mips::SYNC: 5494 if (Inst.getOperand(0).getImm() != 0 && !hasMips32()) 5495 return Match_NonZeroOperandForSync; 5496 return Match_Success; 5497 case Mips::MFC0: 5498 case Mips::MTC0: 5499 case Mips::MTC2: 5500 case Mips::MFC2: 5501 if (Inst.getOperand(2).getImm() != 0 && !hasMips32()) 5502 return Match_NonZeroOperandForMTCX; 5503 return Match_Success; 5504 // As described the MIPSR6 spec, the compact branches that compare registers 5505 // must: 5506 // a) Not use the zero register. 5507 // b) Not use the same register twice. 5508 // c) rs < rt for bnec, beqc. 5509 // NB: For this case, the encoding will swap the operands as their 5510 // ordering doesn't matter. GAS performs this transformation too. 5511 // Hence, that constraint does not have to be enforced. 5512 // 5513 // The compact branches that branch iff the signed addition of two registers 5514 // would overflow must have rs >= rt. That can be handled like beqc/bnec with 5515 // operand swapping. They do not have restriction of using the zero register. 5516 case Mips::BLEZC: case Mips::BLEZC_MMR6: 5517 case Mips::BGEZC: case Mips::BGEZC_MMR6: 5518 case Mips::BGTZC: case Mips::BGTZC_MMR6: 5519 case Mips::BLTZC: case Mips::BLTZC_MMR6: 5520 case Mips::BEQZC: case Mips::BEQZC_MMR6: 5521 case Mips::BNEZC: case Mips::BNEZC_MMR6: 5522 case Mips::BLEZC64: 5523 case Mips::BGEZC64: 5524 case Mips::BGTZC64: 5525 case Mips::BLTZC64: 5526 case Mips::BEQZC64: 5527 case Mips::BNEZC64: 5528 if (Inst.getOperand(0).getReg() == Mips::ZERO || 5529 Inst.getOperand(0).getReg() == Mips::ZERO_64) 5530 return Match_RequiresNoZeroRegister; 5531 return Match_Success; 5532 case Mips::BGEC: case Mips::BGEC_MMR6: 5533 case Mips::BLTC: case Mips::BLTC_MMR6: 5534 case Mips::BGEUC: case Mips::BGEUC_MMR6: 5535 case Mips::BLTUC: case Mips::BLTUC_MMR6: 5536 case Mips::BEQC: case Mips::BEQC_MMR6: 5537 case Mips::BNEC: case Mips::BNEC_MMR6: 5538 case Mips::BGEC64: 5539 case Mips::BLTC64: 5540 case Mips::BGEUC64: 5541 case Mips::BLTUC64: 5542 case Mips::BEQC64: 5543 case Mips::BNEC64: 5544 if (Inst.getOperand(0).getReg() == Mips::ZERO || 5545 Inst.getOperand(0).getReg() == Mips::ZERO_64) 5546 return Match_RequiresNoZeroRegister; 5547 if (Inst.getOperand(1).getReg() == Mips::ZERO || 5548 Inst.getOperand(1).getReg() == Mips::ZERO_64) 5549 return Match_RequiresNoZeroRegister; 5550 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) 5551 return Match_RequiresDifferentOperands; 5552 return Match_Success; 5553 case Mips::DINS: { 5554 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5555 "Operands must be immediates for dins!"); 5556 const signed Pos = Inst.getOperand(2).getImm(); 5557 const signed Size = Inst.getOperand(3).getImm(); 5558 if ((0 > (Pos + Size)) || ((Pos + Size) > 32)) 5559 return Match_RequiresPosSizeRange0_32; 5560 return Match_Success; 5561 } 5562 case Mips::DINSM: 5563 case Mips::DINSU: { 5564 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5565 "Operands must be immediates for dinsm/dinsu!"); 5566 const signed Pos = Inst.getOperand(2).getImm(); 5567 const signed Size = Inst.getOperand(3).getImm(); 5568 if ((32 >= (Pos + Size)) || ((Pos + Size) > 64)) 5569 return Match_RequiresPosSizeRange33_64; 5570 return Match_Success; 5571 } 5572 case Mips::DEXT: { 5573 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5574 "Operands must be immediates for DEXTM!"); 5575 const signed Pos = Inst.getOperand(2).getImm(); 5576 const signed Size = Inst.getOperand(3).getImm(); 5577 if ((1 > (Pos + Size)) || ((Pos + Size) > 63)) 5578 return Match_RequiresPosSizeUImm6; 5579 return Match_Success; 5580 } 5581 case Mips::DEXTM: 5582 case Mips::DEXTU: { 5583 assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && 5584 "Operands must be immediates for dextm/dextu!"); 5585 const signed Pos = Inst.getOperand(2).getImm(); 5586 const signed Size = Inst.getOperand(3).getImm(); 5587 if ((32 > (Pos + Size)) || ((Pos + Size) > 64)) 5588 return Match_RequiresPosSizeRange33_64; 5589 return Match_Success; 5590 } 5591 case Mips::CRC32B: case Mips::CRC32CB: 5592 case Mips::CRC32H: case Mips::CRC32CH: 5593 case Mips::CRC32W: case Mips::CRC32CW: 5594 case Mips::CRC32D: case Mips::CRC32CD: 5595 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) 5596 return Match_RequiresSameSrcAndDst; 5597 return Match_Success; 5598 } 5599 5600 uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags; 5601 if ((TSFlags & MipsII::HasFCCRegOperand) && 5602 (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) 5603 return Match_NoFCCRegisterForCurrentISA; 5604 5605 return Match_Success; 5606 5607 } 5608 5609 static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, 5610 uint64_t ErrorInfo) { 5611 if (ErrorInfo != ~0ULL && ErrorInfo < Operands.size()) { 5612 SMLoc ErrorLoc = Operands[ErrorInfo]->getStartLoc(); 5613 if (ErrorLoc == SMLoc()) 5614 return Loc; 5615 return ErrorLoc; 5616 } 5617 return Loc; 5618 } 5619 5620 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 5621 OperandVector &Operands, 5622 MCStreamer &Out, 5623 uint64_t &ErrorInfo, 5624 bool MatchingInlineAsm) { 5625 MCInst Inst; 5626 unsigned MatchResult = 5627 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); 5628 5629 switch (MatchResult) { 5630 case Match_Success: 5631 if (processInstruction(Inst, IDLoc, Out, STI)) 5632 return true; 5633 return false; 5634 case Match_MissingFeature: 5635 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 5636 return true; 5637 case Match_InvalidOperand: { 5638 SMLoc ErrorLoc = IDLoc; 5639 if (ErrorInfo != ~0ULL) { 5640 if (ErrorInfo >= Operands.size()) 5641 return Error(IDLoc, "too few operands for instruction"); 5642 5643 ErrorLoc = Operands[ErrorInfo]->getStartLoc(); 5644 if (ErrorLoc == SMLoc()) 5645 ErrorLoc = IDLoc; 5646 } 5647 5648 return Error(ErrorLoc, "invalid operand for instruction"); 5649 } 5650 case Match_NonZeroOperandForSync: 5651 return Error(IDLoc, 5652 "s-type must be zero or unspecified for pre-MIPS32 ISAs"); 5653 case Match_NonZeroOperandForMTCX: 5654 return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs"); 5655 case Match_MnemonicFail: 5656 return Error(IDLoc, "invalid instruction"); 5657 case Match_RequiresDifferentSrcAndDst: 5658 return Error(IDLoc, "source and destination must be different"); 5659 case Match_RequiresDifferentOperands: 5660 return Error(IDLoc, "registers must be different"); 5661 case Match_RequiresNoZeroRegister: 5662 return Error(IDLoc, "invalid operand ($zero) for instruction"); 5663 case Match_RequiresSameSrcAndDst: 5664 return Error(IDLoc, "source and destination must match"); 5665 case Match_NoFCCRegisterForCurrentISA: 5666 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5667 "non-zero fcc register doesn't exist in current ISA level"); 5668 case Match_Immz: 5669 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); 5670 case Match_UImm1_0: 5671 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5672 "expected 1-bit unsigned immediate"); 5673 case Match_UImm2_0: 5674 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5675 "expected 2-bit unsigned immediate"); 5676 case Match_UImm2_1: 5677 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5678 "expected immediate in range 1 .. 4"); 5679 case Match_UImm3_0: 5680 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5681 "expected 3-bit unsigned immediate"); 5682 case Match_UImm4_0: 5683 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5684 "expected 4-bit unsigned immediate"); 5685 case Match_SImm4_0: 5686 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5687 "expected 4-bit signed immediate"); 5688 case Match_UImm5_0: 5689 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5690 "expected 5-bit unsigned immediate"); 5691 case Match_SImm5_0: 5692 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5693 "expected 5-bit signed immediate"); 5694 case Match_UImm5_1: 5695 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5696 "expected immediate in range 1 .. 32"); 5697 case Match_UImm5_32: 5698 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5699 "expected immediate in range 32 .. 63"); 5700 case Match_UImm5_33: 5701 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5702 "expected immediate in range 33 .. 64"); 5703 case Match_UImm5_0_Report_UImm6: 5704 // This is used on UImm5 operands that have a corresponding UImm5_32 5705 // operand to avoid confusing the user. 5706 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5707 "expected 6-bit unsigned immediate"); 5708 case Match_UImm5_Lsl2: 5709 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5710 "expected both 7-bit unsigned immediate and multiple of 4"); 5711 case Match_UImmRange2_64: 5712 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5713 "expected immediate in range 2 .. 64"); 5714 case Match_UImm6_0: 5715 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5716 "expected 6-bit unsigned immediate"); 5717 case Match_UImm6_Lsl2: 5718 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5719 "expected both 8-bit unsigned immediate and multiple of 4"); 5720 case Match_SImm6_0: 5721 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5722 "expected 6-bit signed immediate"); 5723 case Match_UImm7_0: 5724 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5725 "expected 7-bit unsigned immediate"); 5726 case Match_UImm7_N1: 5727 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5728 "expected immediate in range -1 .. 126"); 5729 case Match_SImm7_Lsl2: 5730 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5731 "expected both 9-bit signed immediate and multiple of 4"); 5732 case Match_UImm8_0: 5733 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5734 "expected 8-bit unsigned immediate"); 5735 case Match_UImm10_0: 5736 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5737 "expected 10-bit unsigned immediate"); 5738 case Match_SImm10_0: 5739 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5740 "expected 10-bit signed immediate"); 5741 case Match_SImm11_0: 5742 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5743 "expected 11-bit signed immediate"); 5744 case Match_UImm16: 5745 case Match_UImm16_Relaxed: 5746 case Match_UImm16_AltRelaxed: 5747 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5748 "expected 16-bit unsigned immediate"); 5749 case Match_SImm16: 5750 case Match_SImm16_Relaxed: 5751 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5752 "expected 16-bit signed immediate"); 5753 case Match_SImm19_Lsl2: 5754 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5755 "expected both 19-bit signed immediate and multiple of 4"); 5756 case Match_UImm20_0: 5757 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5758 "expected 20-bit unsigned immediate"); 5759 case Match_UImm26_0: 5760 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5761 "expected 26-bit unsigned immediate"); 5762 case Match_SImm32: 5763 case Match_SImm32_Relaxed: 5764 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5765 "expected 32-bit signed immediate"); 5766 case Match_UImm32_Coerced: 5767 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5768 "expected 32-bit immediate"); 5769 case Match_MemSImm9: 5770 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5771 "expected memory with 9-bit signed offset"); 5772 case Match_MemSImm10: 5773 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5774 "expected memory with 10-bit signed offset"); 5775 case Match_MemSImm10Lsl1: 5776 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5777 "expected memory with 11-bit signed offset and multiple of 2"); 5778 case Match_MemSImm10Lsl2: 5779 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5780 "expected memory with 12-bit signed offset and multiple of 4"); 5781 case Match_MemSImm10Lsl3: 5782 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5783 "expected memory with 13-bit signed offset and multiple of 8"); 5784 case Match_MemSImm11: 5785 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5786 "expected memory with 11-bit signed offset"); 5787 case Match_MemSImm12: 5788 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5789 "expected memory with 12-bit signed offset"); 5790 case Match_MemSImm16: 5791 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5792 "expected memory with 16-bit signed offset"); 5793 case Match_MemSImmPtr: 5794 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), 5795 "expected memory with 32-bit signed offset"); 5796 case Match_RequiresPosSizeRange0_32: { 5797 SMLoc ErrorStart = Operands[3]->getStartLoc(); 5798 SMLoc ErrorEnd = Operands[4]->getEndLoc(); 5799 return Error(ErrorStart, "size plus position are not in the range 0 .. 32", 5800 SMRange(ErrorStart, ErrorEnd)); 5801 } 5802 case Match_RequiresPosSizeUImm6: { 5803 SMLoc ErrorStart = Operands[3]->getStartLoc(); 5804 SMLoc ErrorEnd = Operands[4]->getEndLoc(); 5805 return Error(ErrorStart, "size plus position are not in the range 1 .. 63", 5806 SMRange(ErrorStart, ErrorEnd)); 5807 } 5808 case Match_RequiresPosSizeRange33_64: { 5809 SMLoc ErrorStart = Operands[3]->getStartLoc(); 5810 SMLoc ErrorEnd = Operands[4]->getEndLoc(); 5811 return Error(ErrorStart, "size plus position are not in the range 33 .. 64", 5812 SMRange(ErrorStart, ErrorEnd)); 5813 } 5814 } 5815 5816 llvm_unreachable("Implement any new match types added!"); 5817 } 5818 5819 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { 5820 if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex) 5821 Warning(Loc, "used $at (currently $" + Twine(RegIndex) + 5822 ") without \".set noat\""); 5823 } 5824 5825 void MipsAsmParser::warnIfNoMacro(SMLoc Loc) { 5826 if (!AssemblerOptions.back()->isMacro()) 5827 Warning(Loc, "macro instruction expanded into multiple instructions"); 5828 } 5829 5830 void MipsAsmParser::ConvertXWPOperands(MCInst &Inst, 5831 const OperandVector &Operands) { 5832 assert( 5833 (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) && 5834 "Unexpected instruction!"); 5835 ((MipsOperand &)*Operands[1]).addGPR32ZeroAsmRegOperands(Inst, 1); 5836 int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); 5837 Inst.addOperand(MCOperand::createReg(NextReg)); 5838 ((MipsOperand &)*Operands[2]).addMemOperands(Inst, 2); 5839 } 5840 5841 void 5842 MipsAsmParser::printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg, 5843 SMRange Range, bool ShowColors) { 5844 getSourceManager().PrintMessage(Range.Start, SourceMgr::DK_Warning, Msg, 5845 Range, SMFixIt(Range, FixMsg), 5846 ShowColors); 5847 } 5848 5849 int MipsAsmParser::matchCPURegisterName(StringRef Name) { 5850 int CC; 5851 5852 CC = StringSwitch<unsigned>(Name) 5853 .Case("zero", 0) 5854 .Cases("at", "AT", 1) 5855 .Case("a0", 4) 5856 .Case("a1", 5) 5857 .Case("a2", 6) 5858 .Case("a3", 7) 5859 .Case("v0", 2) 5860 .Case("v1", 3) 5861 .Case("s0", 16) 5862 .Case("s1", 17) 5863 .Case("s2", 18) 5864 .Case("s3", 19) 5865 .Case("s4", 20) 5866 .Case("s5", 21) 5867 .Case("s6", 22) 5868 .Case("s7", 23) 5869 .Case("k0", 26) 5870 .Case("k1", 27) 5871 .Case("gp", 28) 5872 .Case("sp", 29) 5873 .Case("fp", 30) 5874 .Case("s8", 30) 5875 .Case("ra", 31) 5876 .Case("t0", 8) 5877 .Case("t1", 9) 5878 .Case("t2", 10) 5879 .Case("t3", 11) 5880 .Case("t4", 12) 5881 .Case("t5", 13) 5882 .Case("t6", 14) 5883 .Case("t7", 15) 5884 .Case("t8", 24) 5885 .Case("t9", 25) 5886 .Default(-1); 5887 5888 if (!(isABI_N32() || isABI_N64())) 5889 return CC; 5890 5891 if (12 <= CC && CC <= 15) { 5892 // Name is one of t4-t7 5893 AsmToken RegTok = getLexer().peekTok(); 5894 SMRange RegRange = RegTok.getLocRange(); 5895 5896 StringRef FixedName = StringSwitch<StringRef>(Name) 5897 .Case("t4", "t0") 5898 .Case("t5", "t1") 5899 .Case("t6", "t2") 5900 .Case("t7", "t3") 5901 .Default(""); 5902 assert(FixedName != "" && "Register name is not one of t4-t7."); 5903 5904 printWarningWithFixIt("register names $t4-$t7 are only available in O32.", 5905 "Did you mean $" + FixedName + "?", RegRange); 5906 } 5907 5908 // Although SGI documentation just cuts out t0-t3 for n32/n64, 5909 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7 5910 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7. 5911 if (8 <= CC && CC <= 11) 5912 CC += 4; 5913 5914 if (CC == -1) 5915 CC = StringSwitch<unsigned>(Name) 5916 .Case("a4", 8) 5917 .Case("a5", 9) 5918 .Case("a6", 10) 5919 .Case("a7", 11) 5920 .Case("kt0", 26) 5921 .Case("kt1", 27) 5922 .Default(-1); 5923 5924 return CC; 5925 } 5926 5927 int MipsAsmParser::matchHWRegsRegisterName(StringRef Name) { 5928 int CC; 5929 5930 CC = StringSwitch<unsigned>(Name) 5931 .Case("hwr_cpunum", 0) 5932 .Case("hwr_synci_step", 1) 5933 .Case("hwr_cc", 2) 5934 .Case("hwr_ccres", 3) 5935 .Case("hwr_ulr", 29) 5936 .Default(-1); 5937 5938 return CC; 5939 } 5940 5941 int MipsAsmParser::matchFPURegisterName(StringRef Name) { 5942 if (Name[0] == 'f') { 5943 StringRef NumString = Name.substr(1); 5944 unsigned IntVal; 5945 if (NumString.getAsInteger(10, IntVal)) 5946 return -1; // This is not an integer. 5947 if (IntVal > 31) // Maximum index for fpu register. 5948 return -1; 5949 return IntVal; 5950 } 5951 return -1; 5952 } 5953 5954 int MipsAsmParser::matchFCCRegisterName(StringRef Name) { 5955 if (Name.startswith("fcc")) { 5956 StringRef NumString = Name.substr(3); 5957 unsigned IntVal; 5958 if (NumString.getAsInteger(10, IntVal)) 5959 return -1; // This is not an integer. 5960 if (IntVal > 7) // There are only 8 fcc registers. 5961 return -1; 5962 return IntVal; 5963 } 5964 return -1; 5965 } 5966 5967 int MipsAsmParser::matchACRegisterName(StringRef Name) { 5968 if (Name.startswith("ac")) { 5969 StringRef NumString = Name.substr(2); 5970 unsigned IntVal; 5971 if (NumString.getAsInteger(10, IntVal)) 5972 return -1; // This is not an integer. 5973 if (IntVal > 3) // There are only 3 acc registers. 5974 return -1; 5975 return IntVal; 5976 } 5977 return -1; 5978 } 5979 5980 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) { 5981 unsigned IntVal; 5982 5983 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal)) 5984 return -1; 5985 5986 if (IntVal > 31) 5987 return -1; 5988 5989 return IntVal; 5990 } 5991 5992 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) { 5993 int CC; 5994 5995 CC = StringSwitch<unsigned>(Name) 5996 .Case("msair", 0) 5997 .Case("msacsr", 1) 5998 .Case("msaaccess", 2) 5999 .Case("msasave", 3) 6000 .Case("msamodify", 4) 6001 .Case("msarequest", 5) 6002 .Case("msamap", 6) 6003 .Case("msaunmap", 7) 6004 .Default(-1); 6005 6006 return CC; 6007 } 6008 6009 bool MipsAsmParser::canUseATReg() { 6010 return AssemblerOptions.back()->getATRegIndex() != 0; 6011 } 6012 6013 unsigned MipsAsmParser::getATReg(SMLoc Loc) { 6014 unsigned ATIndex = AssemblerOptions.back()->getATRegIndex(); 6015 if (ATIndex == 0) { 6016 reportParseError(Loc, 6017 "pseudo-instruction requires $at, which is not available"); 6018 return 0; 6019 } 6020 unsigned AT = getReg( 6021 (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex); 6022 return AT; 6023 } 6024 6025 unsigned MipsAsmParser::getReg(int RC, int RegNo) { 6026 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo); 6027 } 6028 6029 bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { 6030 MCAsmParser &Parser = getParser(); 6031 LLVM_DEBUG(dbgs() << "parseOperand\n"); 6032 6033 // Check if the current operand has a custom associated parser, if so, try to 6034 // custom parse the operand, or fallback to the general approach. 6035 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 6036 if (ResTy == MatchOperand_Success) 6037 return false; 6038 // If there wasn't a custom match, try the generic matcher below. Otherwise, 6039 // there was a match, but an error occurred, in which case, just return that 6040 // the operand parsing failed. 6041 if (ResTy == MatchOperand_ParseFail) 6042 return true; 6043 6044 LLVM_DEBUG(dbgs() << ".. Generic Parser\n"); 6045 6046 switch (getLexer().getKind()) { 6047 case AsmToken::Dollar: { 6048 // Parse the register. 6049 SMLoc S = Parser.getTok().getLoc(); 6050 6051 // Almost all registers have been parsed by custom parsers. There is only 6052 // one exception to this. $zero (and it's alias $0) will reach this point 6053 // for div, divu, and similar instructions because it is not an operand 6054 // to the instruction definition but an explicit register. Special case 6055 // this situation for now. 6056 if (parseAnyRegister(Operands) != MatchOperand_NoMatch) 6057 return false; 6058 6059 // Maybe it is a symbol reference. 6060 StringRef Identifier; 6061 if (Parser.parseIdentifier(Identifier)) 6062 return true; 6063 6064 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6065 MCSymbol *Sym = getContext().getOrCreateSymbol("$" + Identifier); 6066 // Otherwise create a symbol reference. 6067 const MCExpr *Res = 6068 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); 6069 6070 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this)); 6071 return false; 6072 } 6073 default: { 6074 LLVM_DEBUG(dbgs() << ".. generic integer expression\n"); 6075 6076 const MCExpr *Expr; 6077 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand. 6078 if (getParser().parseExpression(Expr)) 6079 return true; 6080 6081 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6082 6083 Operands.push_back(MipsOperand::CreateImm(Expr, S, E, *this)); 6084 return false; 6085 } 6086 } // switch(getLexer().getKind()) 6087 return true; 6088 } 6089 6090 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) { 6091 switch (Expr->getKind()) { 6092 case MCExpr::Constant: 6093 return true; 6094 case MCExpr::SymbolRef: 6095 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None); 6096 case MCExpr::Binary: { 6097 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr); 6098 if (!isEvaluated(BE->getLHS())) 6099 return false; 6100 return isEvaluated(BE->getRHS()); 6101 } 6102 case MCExpr::Unary: 6103 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr()); 6104 case MCExpr::Target: 6105 return true; 6106 } 6107 return false; 6108 } 6109 6110 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 6111 SMLoc &EndLoc) { 6112 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; 6113 OperandMatchResultTy ResTy = parseAnyRegister(Operands); 6114 if (ResTy == MatchOperand_Success) { 6115 assert(Operands.size() == 1); 6116 MipsOperand &Operand = static_cast<MipsOperand &>(*Operands.front()); 6117 StartLoc = Operand.getStartLoc(); 6118 EndLoc = Operand.getEndLoc(); 6119 6120 // AFAIK, we only support numeric registers and named GPR's in CFI 6121 // directives. 6122 // Don't worry about eating tokens before failing. Using an unrecognised 6123 // register is a parse error. 6124 if (Operand.isGPRAsmReg()) { 6125 // Resolve to GPR32 or GPR64 appropriately. 6126 RegNo = isGP64bit() ? Operand.getGPR64Reg() : Operand.getGPR32Reg(); 6127 } 6128 6129 return (RegNo == (unsigned)-1); 6130 } 6131 6132 assert(Operands.size() == 0); 6133 return (RegNo == (unsigned)-1); 6134 } 6135 6136 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { 6137 SMLoc S; 6138 6139 if (isParenExpr) 6140 return getParser().parseParenExprOfDepth(0, Res, S); 6141 return getParser().parseExpression(Res); 6142 } 6143 6144 OperandMatchResultTy 6145 MipsAsmParser::parseMemOperand(OperandVector &Operands) { 6146 MCAsmParser &Parser = getParser(); 6147 LLVM_DEBUG(dbgs() << "parseMemOperand\n"); 6148 const MCExpr *IdVal = nullptr; 6149 SMLoc S; 6150 bool isParenExpr = false; 6151 OperandMatchResultTy Res = MatchOperand_NoMatch; 6152 // First operand is the offset. 6153 S = Parser.getTok().getLoc(); 6154 6155 if (getLexer().getKind() == AsmToken::LParen) { 6156 Parser.Lex(); 6157 isParenExpr = true; 6158 } 6159 6160 if (getLexer().getKind() != AsmToken::Dollar) { 6161 if (parseMemOffset(IdVal, isParenExpr)) 6162 return MatchOperand_ParseFail; 6163 6164 const AsmToken &Tok = Parser.getTok(); // Get the next token. 6165 if (Tok.isNot(AsmToken::LParen)) { 6166 MipsOperand &Mnemonic = static_cast<MipsOperand &>(*Operands[0]); 6167 if (Mnemonic.getToken() == "la" || Mnemonic.getToken() == "dla") { 6168 SMLoc E = 6169 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6170 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this)); 6171 return MatchOperand_Success; 6172 } 6173 if (Tok.is(AsmToken::EndOfStatement)) { 6174 SMLoc E = 6175 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6176 6177 // Zero register assumed, add a memory operand with ZERO as its base. 6178 // "Base" will be managed by k_Memory. 6179 auto Base = MipsOperand::createGPRReg( 6180 0, "0", getContext().getRegisterInfo(), S, E, *this); 6181 Operands.push_back( 6182 MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this)); 6183 return MatchOperand_Success; 6184 } 6185 MCBinaryExpr::Opcode Opcode; 6186 // GAS and LLVM treat comparison operators different. GAS will generate -1 6187 // or 0, while LLVM will generate 0 or 1. Since a comparsion operator is 6188 // highly unlikely to be found in a memory offset expression, we don't 6189 // handle them. 6190 switch (Tok.getKind()) { 6191 case AsmToken::Plus: 6192 Opcode = MCBinaryExpr::Add; 6193 Parser.Lex(); 6194 break; 6195 case AsmToken::Minus: 6196 Opcode = MCBinaryExpr::Sub; 6197 Parser.Lex(); 6198 break; 6199 case AsmToken::Star: 6200 Opcode = MCBinaryExpr::Mul; 6201 Parser.Lex(); 6202 break; 6203 case AsmToken::Pipe: 6204 Opcode = MCBinaryExpr::Or; 6205 Parser.Lex(); 6206 break; 6207 case AsmToken::Amp: 6208 Opcode = MCBinaryExpr::And; 6209 Parser.Lex(); 6210 break; 6211 case AsmToken::LessLess: 6212 Opcode = MCBinaryExpr::Shl; 6213 Parser.Lex(); 6214 break; 6215 case AsmToken::GreaterGreater: 6216 Opcode = MCBinaryExpr::LShr; 6217 Parser.Lex(); 6218 break; 6219 case AsmToken::Caret: 6220 Opcode = MCBinaryExpr::Xor; 6221 Parser.Lex(); 6222 break; 6223 case AsmToken::Slash: 6224 Opcode = MCBinaryExpr::Div; 6225 Parser.Lex(); 6226 break; 6227 case AsmToken::Percent: 6228 Opcode = MCBinaryExpr::Mod; 6229 Parser.Lex(); 6230 break; 6231 default: 6232 Error(Parser.getTok().getLoc(), "'(' or expression expected"); 6233 return MatchOperand_ParseFail; 6234 } 6235 const MCExpr * NextExpr; 6236 if (getParser().parseExpression(NextExpr)) 6237 return MatchOperand_ParseFail; 6238 IdVal = MCBinaryExpr::create(Opcode, IdVal, NextExpr, getContext()); 6239 } 6240 6241 Parser.Lex(); // Eat the '(' token. 6242 } 6243 6244 Res = parseAnyRegister(Operands); 6245 if (Res != MatchOperand_Success) 6246 return Res; 6247 6248 if (Parser.getTok().isNot(AsmToken::RParen)) { 6249 Error(Parser.getTok().getLoc(), "')' expected"); 6250 return MatchOperand_ParseFail; 6251 } 6252 6253 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6254 6255 Parser.Lex(); // Eat the ')' token. 6256 6257 if (!IdVal) 6258 IdVal = MCConstantExpr::create(0, getContext()); 6259 6260 // Replace the register operand with the memory operand. 6261 std::unique_ptr<MipsOperand> op( 6262 static_cast<MipsOperand *>(Operands.back().release())); 6263 // Remove the register from the operands. 6264 // "op" will be managed by k_Memory. 6265 Operands.pop_back(); 6266 // Add the memory operand. 6267 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) { 6268 int64_t Imm; 6269 if (IdVal->evaluateAsAbsolute(Imm)) 6270 IdVal = MCConstantExpr::create(Imm, getContext()); 6271 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef) 6272 IdVal = MCBinaryExpr::create(BE->getOpcode(), BE->getRHS(), BE->getLHS(), 6273 getContext()); 6274 } 6275 6276 Operands.push_back(MipsOperand::CreateMem(std::move(op), IdVal, S, E, *this)); 6277 return MatchOperand_Success; 6278 } 6279 6280 bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) { 6281 MCAsmParser &Parser = getParser(); 6282 MCSymbol *Sym = getContext().lookupSymbol(Parser.getTok().getIdentifier()); 6283 if (!Sym) 6284 return false; 6285 6286 SMLoc S = Parser.getTok().getLoc(); 6287 if (Sym->isVariable()) { 6288 const MCExpr *Expr = Sym->getVariableValue(); 6289 if (Expr->getKind() == MCExpr::SymbolRef) { 6290 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr); 6291 StringRef DefSymbol = Ref->getSymbol().getName(); 6292 if (DefSymbol.startswith("$")) { 6293 OperandMatchResultTy ResTy = 6294 matchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S); 6295 if (ResTy == MatchOperand_Success) { 6296 Parser.Lex(); 6297 return true; 6298 } 6299 if (ResTy == MatchOperand_ParseFail) 6300 llvm_unreachable("Should never ParseFail"); 6301 } 6302 } 6303 } else if (Sym->isUnset()) { 6304 // If symbol is unset, it might be created in the `parseSetAssignment` 6305 // routine as an alias for a numeric register name. 6306 // Lookup in the aliases list. 6307 auto Entry = RegisterSets.find(Sym->getName()); 6308 if (Entry != RegisterSets.end()) { 6309 OperandMatchResultTy ResTy = 6310 matchAnyRegisterWithoutDollar(Operands, Entry->getValue(), S); 6311 if (ResTy == MatchOperand_Success) { 6312 Parser.Lex(); 6313 return true; 6314 } 6315 } 6316 } 6317 6318 return false; 6319 } 6320 6321 OperandMatchResultTy 6322 MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands, 6323 StringRef Identifier, 6324 SMLoc S) { 6325 int Index = matchCPURegisterName(Identifier); 6326 if (Index != -1) { 6327 Operands.push_back(MipsOperand::createGPRReg( 6328 Index, Identifier, getContext().getRegisterInfo(), S, 6329 getLexer().getLoc(), *this)); 6330 return MatchOperand_Success; 6331 } 6332 6333 Index = matchHWRegsRegisterName(Identifier); 6334 if (Index != -1) { 6335 Operands.push_back(MipsOperand::createHWRegsReg( 6336 Index, Identifier, getContext().getRegisterInfo(), S, 6337 getLexer().getLoc(), *this)); 6338 return MatchOperand_Success; 6339 } 6340 6341 Index = matchFPURegisterName(Identifier); 6342 if (Index != -1) { 6343 Operands.push_back(MipsOperand::createFGRReg( 6344 Index, Identifier, getContext().getRegisterInfo(), S, 6345 getLexer().getLoc(), *this)); 6346 return MatchOperand_Success; 6347 } 6348 6349 Index = matchFCCRegisterName(Identifier); 6350 if (Index != -1) { 6351 Operands.push_back(MipsOperand::createFCCReg( 6352 Index, Identifier, getContext().getRegisterInfo(), S, 6353 getLexer().getLoc(), *this)); 6354 return MatchOperand_Success; 6355 } 6356 6357 Index = matchACRegisterName(Identifier); 6358 if (Index != -1) { 6359 Operands.push_back(MipsOperand::createACCReg( 6360 Index, Identifier, getContext().getRegisterInfo(), S, 6361 getLexer().getLoc(), *this)); 6362 return MatchOperand_Success; 6363 } 6364 6365 Index = matchMSA128RegisterName(Identifier); 6366 if (Index != -1) { 6367 Operands.push_back(MipsOperand::createMSA128Reg( 6368 Index, Identifier, getContext().getRegisterInfo(), S, 6369 getLexer().getLoc(), *this)); 6370 return MatchOperand_Success; 6371 } 6372 6373 Index = matchMSA128CtrlRegisterName(Identifier); 6374 if (Index != -1) { 6375 Operands.push_back(MipsOperand::createMSACtrlReg( 6376 Index, Identifier, getContext().getRegisterInfo(), S, 6377 getLexer().getLoc(), *this)); 6378 return MatchOperand_Success; 6379 } 6380 6381 return MatchOperand_NoMatch; 6382 } 6383 6384 OperandMatchResultTy 6385 MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, 6386 const AsmToken &Token, SMLoc S) { 6387 if (Token.is(AsmToken::Identifier)) { 6388 LLVM_DEBUG(dbgs() << ".. identifier\n"); 6389 StringRef Identifier = Token.getIdentifier(); 6390 OperandMatchResultTy ResTy = 6391 matchAnyRegisterNameWithoutDollar(Operands, Identifier, S); 6392 return ResTy; 6393 } else if (Token.is(AsmToken::Integer)) { 6394 LLVM_DEBUG(dbgs() << ".. integer\n"); 6395 int64_t RegNum = Token.getIntVal(); 6396 if (RegNum < 0 || RegNum > 31) { 6397 // Show the error, but treat invalid register 6398 // number as a normal one to continue parsing 6399 // and catch other possible errors. 6400 Error(getLexer().getLoc(), "invalid register number"); 6401 } 6402 Operands.push_back(MipsOperand::createNumericReg( 6403 RegNum, Token.getString(), getContext().getRegisterInfo(), S, 6404 Token.getLoc(), *this)); 6405 return MatchOperand_Success; 6406 } 6407 6408 LLVM_DEBUG(dbgs() << Token.getKind() << "\n"); 6409 6410 return MatchOperand_NoMatch; 6411 } 6412 6413 OperandMatchResultTy 6414 MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { 6415 auto Token = getLexer().peekTok(false); 6416 return matchAnyRegisterWithoutDollar(Operands, Token, S); 6417 } 6418 6419 OperandMatchResultTy 6420 MipsAsmParser::parseAnyRegister(OperandVector &Operands) { 6421 MCAsmParser &Parser = getParser(); 6422 LLVM_DEBUG(dbgs() << "parseAnyRegister\n"); 6423 6424 auto Token = Parser.getTok(); 6425 6426 SMLoc S = Token.getLoc(); 6427 6428 if (Token.isNot(AsmToken::Dollar)) { 6429 LLVM_DEBUG(dbgs() << ".. !$ -> try sym aliasing\n"); 6430 if (Token.is(AsmToken::Identifier)) { 6431 if (searchSymbolAlias(Operands)) 6432 return MatchOperand_Success; 6433 } 6434 LLVM_DEBUG(dbgs() << ".. !symalias -> NoMatch\n"); 6435 return MatchOperand_NoMatch; 6436 } 6437 LLVM_DEBUG(dbgs() << ".. $\n"); 6438 6439 OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar(Operands, S); 6440 if (ResTy == MatchOperand_Success) { 6441 Parser.Lex(); // $ 6442 Parser.Lex(); // identifier 6443 } 6444 return ResTy; 6445 } 6446 6447 OperandMatchResultTy 6448 MipsAsmParser::parseJumpTarget(OperandVector &Operands) { 6449 MCAsmParser &Parser = getParser(); 6450 LLVM_DEBUG(dbgs() << "parseJumpTarget\n"); 6451 6452 SMLoc S = getLexer().getLoc(); 6453 6454 // Registers are a valid target and have priority over symbols. 6455 OperandMatchResultTy ResTy = parseAnyRegister(Operands); 6456 if (ResTy != MatchOperand_NoMatch) 6457 return ResTy; 6458 6459 // Integers and expressions are acceptable 6460 const MCExpr *Expr = nullptr; 6461 if (Parser.parseExpression(Expr)) { 6462 // We have no way of knowing if a symbol was consumed so we must ParseFail 6463 return MatchOperand_ParseFail; 6464 } 6465 Operands.push_back( 6466 MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this)); 6467 return MatchOperand_Success; 6468 } 6469 6470 OperandMatchResultTy 6471 MipsAsmParser::parseInvNum(OperandVector &Operands) { 6472 MCAsmParser &Parser = getParser(); 6473 const MCExpr *IdVal; 6474 // If the first token is '$' we may have register operand. We have to reject 6475 // cases where it is not a register. Complicating the matter is that 6476 // register names are not reserved across all ABIs. 6477 // Peek past the dollar to see if it's a register name for this ABI. 6478 SMLoc S = Parser.getTok().getLoc(); 6479 if (Parser.getTok().is(AsmToken::Dollar)) { 6480 return matchCPURegisterName(Parser.getLexer().peekTok().getString()) == -1 6481 ? MatchOperand_ParseFail 6482 : MatchOperand_NoMatch; 6483 } 6484 if (getParser().parseExpression(IdVal)) 6485 return MatchOperand_ParseFail; 6486 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal); 6487 if (!MCE) 6488 return MatchOperand_NoMatch; 6489 int64_t Val = MCE->getValue(); 6490 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6491 Operands.push_back(MipsOperand::CreateImm( 6492 MCConstantExpr::create(0 - Val, getContext()), S, E, *this)); 6493 return MatchOperand_Success; 6494 } 6495 6496 OperandMatchResultTy 6497 MipsAsmParser::parseRegisterList(OperandVector &Operands) { 6498 MCAsmParser &Parser = getParser(); 6499 SmallVector<unsigned, 10> Regs; 6500 unsigned RegNo; 6501 unsigned PrevReg = Mips::NoRegister; 6502 bool RegRange = false; 6503 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands; 6504 6505 if (Parser.getTok().isNot(AsmToken::Dollar)) 6506 return MatchOperand_ParseFail; 6507 6508 SMLoc S = Parser.getTok().getLoc(); 6509 while (parseAnyRegister(TmpOperands) == MatchOperand_Success) { 6510 SMLoc E = getLexer().getLoc(); 6511 MipsOperand &Reg = static_cast<MipsOperand &>(*TmpOperands.back()); 6512 RegNo = isGP64bit() ? Reg.getGPR64Reg() : Reg.getGPR32Reg(); 6513 if (RegRange) { 6514 // Remove last register operand because registers from register range 6515 // should be inserted first. 6516 if ((isGP64bit() && RegNo == Mips::RA_64) || 6517 (!isGP64bit() && RegNo == Mips::RA)) { 6518 Regs.push_back(RegNo); 6519 } else { 6520 unsigned TmpReg = PrevReg + 1; 6521 while (TmpReg <= RegNo) { 6522 if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) || 6523 (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) && 6524 isGP64bit())) { 6525 Error(E, "invalid register operand"); 6526 return MatchOperand_ParseFail; 6527 } 6528 6529 PrevReg = TmpReg; 6530 Regs.push_back(TmpReg++); 6531 } 6532 } 6533 6534 RegRange = false; 6535 } else { 6536 if ((PrevReg == Mips::NoRegister) && 6537 ((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) || 6538 (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA)))) { 6539 Error(E, "$16 or $31 expected"); 6540 return MatchOperand_ParseFail; 6541 } else if (!(((RegNo == Mips::FP || RegNo == Mips::RA || 6542 (RegNo >= Mips::S0 && RegNo <= Mips::S7)) && 6543 !isGP64bit()) || 6544 ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 || 6545 (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) && 6546 isGP64bit()))) { 6547 Error(E, "invalid register operand"); 6548 return MatchOperand_ParseFail; 6549 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && 6550 ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) || 6551 (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && 6552 isGP64bit()))) { 6553 Error(E, "consecutive register numbers expected"); 6554 return MatchOperand_ParseFail; 6555 } 6556 6557 Regs.push_back(RegNo); 6558 } 6559 6560 if (Parser.getTok().is(AsmToken::Minus)) 6561 RegRange = true; 6562 6563 if (!Parser.getTok().isNot(AsmToken::Minus) && 6564 !Parser.getTok().isNot(AsmToken::Comma)) { 6565 Error(E, "',' or '-' expected"); 6566 return MatchOperand_ParseFail; 6567 } 6568 6569 Lex(); // Consume comma or minus 6570 if (Parser.getTok().isNot(AsmToken::Dollar)) 6571 break; 6572 6573 PrevReg = RegNo; 6574 } 6575 6576 SMLoc E = Parser.getTok().getLoc(); 6577 Operands.push_back(MipsOperand::CreateRegList(Regs, S, E, *this)); 6578 parseMemOperand(Operands); 6579 return MatchOperand_Success; 6580 } 6581 6582 /// Sometimes (i.e. load/stores) the operand may be followed immediately by 6583 /// either this. 6584 /// ::= '(', register, ')' 6585 /// handle it before we iterate so we don't get tripped up by the lack of 6586 /// a comma. 6587 bool MipsAsmParser::parseParenSuffix(StringRef Name, OperandVector &Operands) { 6588 MCAsmParser &Parser = getParser(); 6589 if (getLexer().is(AsmToken::LParen)) { 6590 Operands.push_back( 6591 MipsOperand::CreateToken("(", getLexer().getLoc(), *this)); 6592 Parser.Lex(); 6593 if (parseOperand(Operands, Name)) { 6594 SMLoc Loc = getLexer().getLoc(); 6595 return Error(Loc, "unexpected token in argument list"); 6596 } 6597 if (Parser.getTok().isNot(AsmToken::RParen)) { 6598 SMLoc Loc = getLexer().getLoc(); 6599 return Error(Loc, "unexpected token, expected ')'"); 6600 } 6601 Operands.push_back( 6602 MipsOperand::CreateToken(")", getLexer().getLoc(), *this)); 6603 Parser.Lex(); 6604 } 6605 return false; 6606 } 6607 6608 /// Sometimes (i.e. in MSA) the operand may be followed immediately by 6609 /// either one of these. 6610 /// ::= '[', register, ']' 6611 /// ::= '[', integer, ']' 6612 /// handle it before we iterate so we don't get tripped up by the lack of 6613 /// a comma. 6614 bool MipsAsmParser::parseBracketSuffix(StringRef Name, 6615 OperandVector &Operands) { 6616 MCAsmParser &Parser = getParser(); 6617 if (getLexer().is(AsmToken::LBrac)) { 6618 Operands.push_back( 6619 MipsOperand::CreateToken("[", getLexer().getLoc(), *this)); 6620 Parser.Lex(); 6621 if (parseOperand(Operands, Name)) { 6622 SMLoc Loc = getLexer().getLoc(); 6623 return Error(Loc, "unexpected token in argument list"); 6624 } 6625 if (Parser.getTok().isNot(AsmToken::RBrac)) { 6626 SMLoc Loc = getLexer().getLoc(); 6627 return Error(Loc, "unexpected token, expected ']'"); 6628 } 6629 Operands.push_back( 6630 MipsOperand::CreateToken("]", getLexer().getLoc(), *this)); 6631 Parser.Lex(); 6632 } 6633 return false; 6634 } 6635 6636 static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 6637 unsigned VariantID = 0); 6638 6639 bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 6640 SMLoc NameLoc, OperandVector &Operands) { 6641 MCAsmParser &Parser = getParser(); 6642 LLVM_DEBUG(dbgs() << "ParseInstruction\n"); 6643 6644 // We have reached first instruction, module directive are now forbidden. 6645 getTargetStreamer().forbidModuleDirective(); 6646 6647 // Check if we have valid mnemonic 6648 if (!mnemonicIsValid(Name, 0)) { 6649 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 6650 std::string Suggestion = MipsMnemonicSpellCheck(Name, FBS); 6651 return Error(NameLoc, "unknown instruction" + Suggestion); 6652 } 6653 // First operand in MCInst is instruction mnemonic. 6654 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this)); 6655 6656 // Read the remaining operands. 6657 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6658 // Read the first operand. 6659 if (parseOperand(Operands, Name)) { 6660 SMLoc Loc = getLexer().getLoc(); 6661 return Error(Loc, "unexpected token in argument list"); 6662 } 6663 if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands)) 6664 return true; 6665 // AFAIK, parenthesis suffixes are never on the first operand 6666 6667 while (getLexer().is(AsmToken::Comma)) { 6668 Parser.Lex(); // Eat the comma. 6669 // Parse and remember the operand. 6670 if (parseOperand(Operands, Name)) { 6671 SMLoc Loc = getLexer().getLoc(); 6672 return Error(Loc, "unexpected token in argument list"); 6673 } 6674 // Parse bracket and parenthesis suffixes before we iterate 6675 if (getLexer().is(AsmToken::LBrac)) { 6676 if (parseBracketSuffix(Name, Operands)) 6677 return true; 6678 } else if (getLexer().is(AsmToken::LParen) && 6679 parseParenSuffix(Name, Operands)) 6680 return true; 6681 } 6682 } 6683 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6684 SMLoc Loc = getLexer().getLoc(); 6685 return Error(Loc, "unexpected token in argument list"); 6686 } 6687 Parser.Lex(); // Consume the EndOfStatement. 6688 return false; 6689 } 6690 6691 // FIXME: Given that these have the same name, these should both be 6692 // consistent on affecting the Parser. 6693 bool MipsAsmParser::reportParseError(Twine ErrorMsg) { 6694 SMLoc Loc = getLexer().getLoc(); 6695 return Error(Loc, ErrorMsg); 6696 } 6697 6698 bool MipsAsmParser::reportParseError(SMLoc Loc, Twine ErrorMsg) { 6699 return Error(Loc, ErrorMsg); 6700 } 6701 6702 bool MipsAsmParser::parseSetNoAtDirective() { 6703 MCAsmParser &Parser = getParser(); 6704 // Line should look like: ".set noat". 6705 6706 // Set the $at register to $0. 6707 AssemblerOptions.back()->setATRegIndex(0); 6708 6709 Parser.Lex(); // Eat "noat". 6710 6711 // If this is not the end of the statement, report an error. 6712 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6713 reportParseError("unexpected token, expected end of statement"); 6714 return false; 6715 } 6716 6717 getTargetStreamer().emitDirectiveSetNoAt(); 6718 Parser.Lex(); // Consume the EndOfStatement. 6719 return false; 6720 } 6721 6722 bool MipsAsmParser::parseSetAtDirective() { 6723 // Line can be: ".set at", which sets $at to $1 6724 // or ".set at=$reg", which sets $at to $reg. 6725 MCAsmParser &Parser = getParser(); 6726 Parser.Lex(); // Eat "at". 6727 6728 if (getLexer().is(AsmToken::EndOfStatement)) { 6729 // No register was specified, so we set $at to $1. 6730 AssemblerOptions.back()->setATRegIndex(1); 6731 6732 getTargetStreamer().emitDirectiveSetAt(); 6733 Parser.Lex(); // Consume the EndOfStatement. 6734 return false; 6735 } 6736 6737 if (getLexer().isNot(AsmToken::Equal)) { 6738 reportParseError("unexpected token, expected equals sign"); 6739 return false; 6740 } 6741 Parser.Lex(); // Eat "=". 6742 6743 if (getLexer().isNot(AsmToken::Dollar)) { 6744 if (getLexer().is(AsmToken::EndOfStatement)) { 6745 reportParseError("no register specified"); 6746 return false; 6747 } else { 6748 reportParseError("unexpected token, expected dollar sign '$'"); 6749 return false; 6750 } 6751 } 6752 Parser.Lex(); // Eat "$". 6753 6754 // Find out what "reg" is. 6755 unsigned AtRegNo; 6756 const AsmToken &Reg = Parser.getTok(); 6757 if (Reg.is(AsmToken::Identifier)) { 6758 AtRegNo = matchCPURegisterName(Reg.getIdentifier()); 6759 } else if (Reg.is(AsmToken::Integer)) { 6760 AtRegNo = Reg.getIntVal(); 6761 } else { 6762 reportParseError("unexpected token, expected identifier or integer"); 6763 return false; 6764 } 6765 6766 // Check if $reg is a valid register. If it is, set $at to $reg. 6767 if (!AssemblerOptions.back()->setATRegIndex(AtRegNo)) { 6768 reportParseError("invalid register"); 6769 return false; 6770 } 6771 Parser.Lex(); // Eat "reg". 6772 6773 // If this is not the end of the statement, report an error. 6774 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6775 reportParseError("unexpected token, expected end of statement"); 6776 return false; 6777 } 6778 6779 getTargetStreamer().emitDirectiveSetAtWithArg(AtRegNo); 6780 6781 Parser.Lex(); // Consume the EndOfStatement. 6782 return false; 6783 } 6784 6785 bool MipsAsmParser::parseSetReorderDirective() { 6786 MCAsmParser &Parser = getParser(); 6787 Parser.Lex(); 6788 // If this is not the end of the statement, report an error. 6789 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6790 reportParseError("unexpected token, expected end of statement"); 6791 return false; 6792 } 6793 AssemblerOptions.back()->setReorder(); 6794 getTargetStreamer().emitDirectiveSetReorder(); 6795 Parser.Lex(); // Consume the EndOfStatement. 6796 return false; 6797 } 6798 6799 bool MipsAsmParser::parseSetNoReorderDirective() { 6800 MCAsmParser &Parser = getParser(); 6801 Parser.Lex(); 6802 // If this is not the end of the statement, report an error. 6803 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6804 reportParseError("unexpected token, expected end of statement"); 6805 return false; 6806 } 6807 AssemblerOptions.back()->setNoReorder(); 6808 getTargetStreamer().emitDirectiveSetNoReorder(); 6809 Parser.Lex(); // Consume the EndOfStatement. 6810 return false; 6811 } 6812 6813 bool MipsAsmParser::parseSetMacroDirective() { 6814 MCAsmParser &Parser = getParser(); 6815 Parser.Lex(); 6816 // If this is not the end of the statement, report an error. 6817 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6818 reportParseError("unexpected token, expected end of statement"); 6819 return false; 6820 } 6821 AssemblerOptions.back()->setMacro(); 6822 getTargetStreamer().emitDirectiveSetMacro(); 6823 Parser.Lex(); // Consume the EndOfStatement. 6824 return false; 6825 } 6826 6827 bool MipsAsmParser::parseSetNoMacroDirective() { 6828 MCAsmParser &Parser = getParser(); 6829 Parser.Lex(); 6830 // If this is not the end of the statement, report an error. 6831 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6832 reportParseError("unexpected token, expected end of statement"); 6833 return false; 6834 } 6835 if (AssemblerOptions.back()->isReorder()) { 6836 reportParseError("`noreorder' must be set before `nomacro'"); 6837 return false; 6838 } 6839 AssemblerOptions.back()->setNoMacro(); 6840 getTargetStreamer().emitDirectiveSetNoMacro(); 6841 Parser.Lex(); // Consume the EndOfStatement. 6842 return false; 6843 } 6844 6845 bool MipsAsmParser::parseSetMsaDirective() { 6846 MCAsmParser &Parser = getParser(); 6847 Parser.Lex(); 6848 6849 // If this is not the end of the statement, report an error. 6850 if (getLexer().isNot(AsmToken::EndOfStatement)) 6851 return reportParseError("unexpected token, expected end of statement"); 6852 6853 setFeatureBits(Mips::FeatureMSA, "msa"); 6854 getTargetStreamer().emitDirectiveSetMsa(); 6855 return false; 6856 } 6857 6858 bool MipsAsmParser::parseSetNoMsaDirective() { 6859 MCAsmParser &Parser = getParser(); 6860 Parser.Lex(); 6861 6862 // If this is not the end of the statement, report an error. 6863 if (getLexer().isNot(AsmToken::EndOfStatement)) 6864 return reportParseError("unexpected token, expected end of statement"); 6865 6866 clearFeatureBits(Mips::FeatureMSA, "msa"); 6867 getTargetStreamer().emitDirectiveSetNoMsa(); 6868 return false; 6869 } 6870 6871 bool MipsAsmParser::parseSetNoDspDirective() { 6872 MCAsmParser &Parser = getParser(); 6873 Parser.Lex(); // Eat "nodsp". 6874 6875 // If this is not the end of the statement, report an error. 6876 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6877 reportParseError("unexpected token, expected end of statement"); 6878 return false; 6879 } 6880 6881 clearFeatureBits(Mips::FeatureDSP, "dsp"); 6882 getTargetStreamer().emitDirectiveSetNoDsp(); 6883 return false; 6884 } 6885 6886 bool MipsAsmParser::parseSetMips16Directive() { 6887 MCAsmParser &Parser = getParser(); 6888 Parser.Lex(); // Eat "mips16". 6889 6890 // If this is not the end of the statement, report an error. 6891 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6892 reportParseError("unexpected token, expected end of statement"); 6893 return false; 6894 } 6895 6896 setFeatureBits(Mips::FeatureMips16, "mips16"); 6897 getTargetStreamer().emitDirectiveSetMips16(); 6898 Parser.Lex(); // Consume the EndOfStatement. 6899 return false; 6900 } 6901 6902 bool MipsAsmParser::parseSetNoMips16Directive() { 6903 MCAsmParser &Parser = getParser(); 6904 Parser.Lex(); // Eat "nomips16". 6905 6906 // If this is not the end of the statement, report an error. 6907 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6908 reportParseError("unexpected token, expected end of statement"); 6909 return false; 6910 } 6911 6912 clearFeatureBits(Mips::FeatureMips16, "mips16"); 6913 getTargetStreamer().emitDirectiveSetNoMips16(); 6914 Parser.Lex(); // Consume the EndOfStatement. 6915 return false; 6916 } 6917 6918 bool MipsAsmParser::parseSetFpDirective() { 6919 MCAsmParser &Parser = getParser(); 6920 MipsABIFlagsSection::FpABIKind FpAbiVal; 6921 // Line can be: .set fp=32 6922 // .set fp=xx 6923 // .set fp=64 6924 Parser.Lex(); // Eat fp token 6925 AsmToken Tok = Parser.getTok(); 6926 if (Tok.isNot(AsmToken::Equal)) { 6927 reportParseError("unexpected token, expected equals sign '='"); 6928 return false; 6929 } 6930 Parser.Lex(); // Eat '=' token. 6931 Tok = Parser.getTok(); 6932 6933 if (!parseFpABIValue(FpAbiVal, ".set")) 6934 return false; 6935 6936 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6937 reportParseError("unexpected token, expected end of statement"); 6938 return false; 6939 } 6940 getTargetStreamer().emitDirectiveSetFp(FpAbiVal); 6941 Parser.Lex(); // Consume the EndOfStatement. 6942 return false; 6943 } 6944 6945 bool MipsAsmParser::parseSetOddSPRegDirective() { 6946 MCAsmParser &Parser = getParser(); 6947 6948 Parser.Lex(); // Eat "oddspreg". 6949 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6950 reportParseError("unexpected token, expected end of statement"); 6951 return false; 6952 } 6953 6954 clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); 6955 getTargetStreamer().emitDirectiveSetOddSPReg(); 6956 return false; 6957 } 6958 6959 bool MipsAsmParser::parseSetNoOddSPRegDirective() { 6960 MCAsmParser &Parser = getParser(); 6961 6962 Parser.Lex(); // Eat "nooddspreg". 6963 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6964 reportParseError("unexpected token, expected end of statement"); 6965 return false; 6966 } 6967 6968 setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); 6969 getTargetStreamer().emitDirectiveSetNoOddSPReg(); 6970 return false; 6971 } 6972 6973 bool MipsAsmParser::parseSetMtDirective() { 6974 MCAsmParser &Parser = getParser(); 6975 Parser.Lex(); // Eat "mt". 6976 6977 // If this is not the end of the statement, report an error. 6978 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6979 reportParseError("unexpected token, expected end of statement"); 6980 return false; 6981 } 6982 6983 setFeatureBits(Mips::FeatureMT, "mt"); 6984 getTargetStreamer().emitDirectiveSetMt(); 6985 Parser.Lex(); // Consume the EndOfStatement. 6986 return false; 6987 } 6988 6989 bool MipsAsmParser::parseSetNoMtDirective() { 6990 MCAsmParser &Parser = getParser(); 6991 Parser.Lex(); // Eat "nomt". 6992 6993 // If this is not the end of the statement, report an error. 6994 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6995 reportParseError("unexpected token, expected end of statement"); 6996 return false; 6997 } 6998 6999 clearFeatureBits(Mips::FeatureMT, "mt"); 7000 7001 getTargetStreamer().emitDirectiveSetNoMt(); 7002 Parser.Lex(); // Consume the EndOfStatement. 7003 return false; 7004 } 7005 7006 bool MipsAsmParser::parseSetNoCRCDirective() { 7007 MCAsmParser &Parser = getParser(); 7008 Parser.Lex(); // Eat "nocrc". 7009 7010 // If this is not the end of the statement, report an error. 7011 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7012 reportParseError("unexpected token, expected end of statement"); 7013 return false; 7014 } 7015 7016 clearFeatureBits(Mips::FeatureCRC, "crc"); 7017 7018 getTargetStreamer().emitDirectiveSetNoCRC(); 7019 Parser.Lex(); // Consume the EndOfStatement. 7020 return false; 7021 } 7022 7023 bool MipsAsmParser::parseSetNoVirtDirective() { 7024 MCAsmParser &Parser = getParser(); 7025 Parser.Lex(); // Eat "novirt". 7026 7027 // If this is not the end of the statement, report an error. 7028 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7029 reportParseError("unexpected token, expected end of statement"); 7030 return false; 7031 } 7032 7033 clearFeatureBits(Mips::FeatureVirt, "virt"); 7034 7035 getTargetStreamer().emitDirectiveSetNoVirt(); 7036 Parser.Lex(); // Consume the EndOfStatement. 7037 return false; 7038 } 7039 7040 bool MipsAsmParser::parseSetNoGINVDirective() { 7041 MCAsmParser &Parser = getParser(); 7042 Parser.Lex(); // Eat "noginv". 7043 7044 // If this is not the end of the statement, report an error. 7045 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7046 reportParseError("unexpected token, expected end of statement"); 7047 return false; 7048 } 7049 7050 clearFeatureBits(Mips::FeatureGINV, "ginv"); 7051 7052 getTargetStreamer().emitDirectiveSetNoGINV(); 7053 Parser.Lex(); // Consume the EndOfStatement. 7054 return false; 7055 } 7056 7057 bool MipsAsmParser::parseSetPopDirective() { 7058 MCAsmParser &Parser = getParser(); 7059 SMLoc Loc = getLexer().getLoc(); 7060 7061 Parser.Lex(); 7062 if (getLexer().isNot(AsmToken::EndOfStatement)) 7063 return reportParseError("unexpected token, expected end of statement"); 7064 7065 // Always keep an element on the options "stack" to prevent the user 7066 // from changing the initial options. This is how we remember them. 7067 if (AssemblerOptions.size() == 2) 7068 return reportParseError(Loc, ".set pop with no .set push"); 7069 7070 MCSubtargetInfo &STI = copySTI(); 7071 AssemblerOptions.pop_back(); 7072 setAvailableFeatures( 7073 ComputeAvailableFeatures(AssemblerOptions.back()->getFeatures())); 7074 STI.setFeatureBits(AssemblerOptions.back()->getFeatures()); 7075 7076 getTargetStreamer().emitDirectiveSetPop(); 7077 return false; 7078 } 7079 7080 bool MipsAsmParser::parseSetPushDirective() { 7081 MCAsmParser &Parser = getParser(); 7082 Parser.Lex(); 7083 if (getLexer().isNot(AsmToken::EndOfStatement)) 7084 return reportParseError("unexpected token, expected end of statement"); 7085 7086 // Create a copy of the current assembler options environment and push it. 7087 AssemblerOptions.push_back( 7088 std::make_unique<MipsAssemblerOptions>(AssemblerOptions.back().get())); 7089 7090 getTargetStreamer().emitDirectiveSetPush(); 7091 return false; 7092 } 7093 7094 bool MipsAsmParser::parseSetSoftFloatDirective() { 7095 MCAsmParser &Parser = getParser(); 7096 Parser.Lex(); 7097 if (getLexer().isNot(AsmToken::EndOfStatement)) 7098 return reportParseError("unexpected token, expected end of statement"); 7099 7100 setFeatureBits(Mips::FeatureSoftFloat, "soft-float"); 7101 getTargetStreamer().emitDirectiveSetSoftFloat(); 7102 return false; 7103 } 7104 7105 bool MipsAsmParser::parseSetHardFloatDirective() { 7106 MCAsmParser &Parser = getParser(); 7107 Parser.Lex(); 7108 if (getLexer().isNot(AsmToken::EndOfStatement)) 7109 return reportParseError("unexpected token, expected end of statement"); 7110 7111 clearFeatureBits(Mips::FeatureSoftFloat, "soft-float"); 7112 getTargetStreamer().emitDirectiveSetHardFloat(); 7113 return false; 7114 } 7115 7116 bool MipsAsmParser::parseSetAssignment() { 7117 StringRef Name; 7118 MCAsmParser &Parser = getParser(); 7119 7120 if (Parser.parseIdentifier(Name)) 7121 return reportParseError("expected identifier after .set"); 7122 7123 if (getLexer().isNot(AsmToken::Comma)) 7124 return reportParseError("unexpected token, expected comma"); 7125 Lex(); // Eat comma 7126 7127 if (getLexer().is(AsmToken::Dollar) && 7128 getLexer().peekTok().is(AsmToken::Integer)) { 7129 // Parse assignment of a numeric register: 7130 // .set r1,$1 7131 Parser.Lex(); // Eat $. 7132 RegisterSets[Name] = Parser.getTok(); 7133 Parser.Lex(); // Eat identifier. 7134 getContext().getOrCreateSymbol(Name); 7135 return false; 7136 } 7137 7138 MCSymbol *Sym; 7139 const MCExpr *Value; 7140 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true, 7141 Parser, Sym, Value)) 7142 return true; 7143 Sym->setVariableValue(Value); 7144 7145 return false; 7146 } 7147 7148 bool MipsAsmParser::parseSetMips0Directive() { 7149 MCAsmParser &Parser = getParser(); 7150 Parser.Lex(); 7151 if (getLexer().isNot(AsmToken::EndOfStatement)) 7152 return reportParseError("unexpected token, expected end of statement"); 7153 7154 // Reset assembler options to their initial values. 7155 MCSubtargetInfo &STI = copySTI(); 7156 setAvailableFeatures( 7157 ComputeAvailableFeatures(AssemblerOptions.front()->getFeatures())); 7158 STI.setFeatureBits(AssemblerOptions.front()->getFeatures()); 7159 AssemblerOptions.back()->setFeatures(AssemblerOptions.front()->getFeatures()); 7160 7161 getTargetStreamer().emitDirectiveSetMips0(); 7162 return false; 7163 } 7164 7165 bool MipsAsmParser::parseSetArchDirective() { 7166 MCAsmParser &Parser = getParser(); 7167 Parser.Lex(); 7168 if (getLexer().isNot(AsmToken::Equal)) 7169 return reportParseError("unexpected token, expected equals sign"); 7170 7171 Parser.Lex(); 7172 StringRef Arch = getParser().parseStringToEndOfStatement().trim(); 7173 if (Arch.empty()) 7174 return reportParseError("expected arch identifier"); 7175 7176 StringRef ArchFeatureName = 7177 StringSwitch<StringRef>(Arch) 7178 .Case("mips1", "mips1") 7179 .Case("mips2", "mips2") 7180 .Case("mips3", "mips3") 7181 .Case("mips4", "mips4") 7182 .Case("mips5", "mips5") 7183 .Case("mips32", "mips32") 7184 .Case("mips32r2", "mips32r2") 7185 .Case("mips32r3", "mips32r3") 7186 .Case("mips32r5", "mips32r5") 7187 .Case("mips32r6", "mips32r6") 7188 .Case("mips64", "mips64") 7189 .Case("mips64r2", "mips64r2") 7190 .Case("mips64r3", "mips64r3") 7191 .Case("mips64r5", "mips64r5") 7192 .Case("mips64r6", "mips64r6") 7193 .Case("octeon", "cnmips") 7194 .Case("octeon+", "cnmipsp") 7195 .Case("r4000", "mips3") // This is an implementation of Mips3. 7196 .Default(""); 7197 7198 if (ArchFeatureName.empty()) 7199 return reportParseError("unsupported architecture"); 7200 7201 if (ArchFeatureName == "mips64r6" && inMicroMipsMode()) 7202 return reportParseError("mips64r6 does not support microMIPS"); 7203 7204 selectArch(ArchFeatureName); 7205 getTargetStreamer().emitDirectiveSetArch(Arch); 7206 return false; 7207 } 7208 7209 bool MipsAsmParser::parseSetFeature(uint64_t Feature) { 7210 MCAsmParser &Parser = getParser(); 7211 Parser.Lex(); 7212 if (getLexer().isNot(AsmToken::EndOfStatement)) 7213 return reportParseError("unexpected token, expected end of statement"); 7214 7215 switch (Feature) { 7216 default: 7217 llvm_unreachable("Unimplemented feature"); 7218 case Mips::FeatureDSP: 7219 setFeatureBits(Mips::FeatureDSP, "dsp"); 7220 getTargetStreamer().emitDirectiveSetDsp(); 7221 break; 7222 case Mips::FeatureDSPR2: 7223 setFeatureBits(Mips::FeatureDSPR2, "dspr2"); 7224 getTargetStreamer().emitDirectiveSetDspr2(); 7225 break; 7226 case Mips::FeatureMicroMips: 7227 setFeatureBits(Mips::FeatureMicroMips, "micromips"); 7228 getTargetStreamer().emitDirectiveSetMicroMips(); 7229 break; 7230 case Mips::FeatureMips1: 7231 selectArch("mips1"); 7232 getTargetStreamer().emitDirectiveSetMips1(); 7233 break; 7234 case Mips::FeatureMips2: 7235 selectArch("mips2"); 7236 getTargetStreamer().emitDirectiveSetMips2(); 7237 break; 7238 case Mips::FeatureMips3: 7239 selectArch("mips3"); 7240 getTargetStreamer().emitDirectiveSetMips3(); 7241 break; 7242 case Mips::FeatureMips4: 7243 selectArch("mips4"); 7244 getTargetStreamer().emitDirectiveSetMips4(); 7245 break; 7246 case Mips::FeatureMips5: 7247 selectArch("mips5"); 7248 getTargetStreamer().emitDirectiveSetMips5(); 7249 break; 7250 case Mips::FeatureMips32: 7251 selectArch("mips32"); 7252 getTargetStreamer().emitDirectiveSetMips32(); 7253 break; 7254 case Mips::FeatureMips32r2: 7255 selectArch("mips32r2"); 7256 getTargetStreamer().emitDirectiveSetMips32R2(); 7257 break; 7258 case Mips::FeatureMips32r3: 7259 selectArch("mips32r3"); 7260 getTargetStreamer().emitDirectiveSetMips32R3(); 7261 break; 7262 case Mips::FeatureMips32r5: 7263 selectArch("mips32r5"); 7264 getTargetStreamer().emitDirectiveSetMips32R5(); 7265 break; 7266 case Mips::FeatureMips32r6: 7267 selectArch("mips32r6"); 7268 getTargetStreamer().emitDirectiveSetMips32R6(); 7269 break; 7270 case Mips::FeatureMips64: 7271 selectArch("mips64"); 7272 getTargetStreamer().emitDirectiveSetMips64(); 7273 break; 7274 case Mips::FeatureMips64r2: 7275 selectArch("mips64r2"); 7276 getTargetStreamer().emitDirectiveSetMips64R2(); 7277 break; 7278 case Mips::FeatureMips64r3: 7279 selectArch("mips64r3"); 7280 getTargetStreamer().emitDirectiveSetMips64R3(); 7281 break; 7282 case Mips::FeatureMips64r5: 7283 selectArch("mips64r5"); 7284 getTargetStreamer().emitDirectiveSetMips64R5(); 7285 break; 7286 case Mips::FeatureMips64r6: 7287 selectArch("mips64r6"); 7288 getTargetStreamer().emitDirectiveSetMips64R6(); 7289 break; 7290 case Mips::FeatureCRC: 7291 setFeatureBits(Mips::FeatureCRC, "crc"); 7292 getTargetStreamer().emitDirectiveSetCRC(); 7293 break; 7294 case Mips::FeatureVirt: 7295 setFeatureBits(Mips::FeatureVirt, "virt"); 7296 getTargetStreamer().emitDirectiveSetVirt(); 7297 break; 7298 case Mips::FeatureGINV: 7299 setFeatureBits(Mips::FeatureGINV, "ginv"); 7300 getTargetStreamer().emitDirectiveSetGINV(); 7301 break; 7302 } 7303 return false; 7304 } 7305 7306 bool MipsAsmParser::eatComma(StringRef ErrorStr) { 7307 MCAsmParser &Parser = getParser(); 7308 if (getLexer().isNot(AsmToken::Comma)) { 7309 SMLoc Loc = getLexer().getLoc(); 7310 return Error(Loc, ErrorStr); 7311 } 7312 7313 Parser.Lex(); // Eat the comma. 7314 return true; 7315 } 7316 7317 // Used to determine if .cpload, .cprestore, and .cpsetup have any effect. 7318 // In this class, it is only used for .cprestore. 7319 // FIXME: Only keep track of IsPicEnabled in one place, instead of in both 7320 // MipsTargetELFStreamer and MipsAsmParser. 7321 bool MipsAsmParser::isPicAndNotNxxAbi() { 7322 return inPicMode() && !(isABI_N32() || isABI_N64()); 7323 } 7324 7325 bool MipsAsmParser::parseDirectiveCpLoad(SMLoc Loc) { 7326 if (AssemblerOptions.back()->isReorder()) 7327 Warning(Loc, ".cpload should be inside a noreorder section"); 7328 7329 if (inMips16Mode()) { 7330 reportParseError(".cpload is not supported in Mips16 mode"); 7331 return false; 7332 } 7333 7334 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg; 7335 OperandMatchResultTy ResTy = parseAnyRegister(Reg); 7336 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { 7337 reportParseError("expected register containing function address"); 7338 return false; 7339 } 7340 7341 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); 7342 if (!RegOpnd.isGPRAsmReg()) { 7343 reportParseError(RegOpnd.getStartLoc(), "invalid register"); 7344 return false; 7345 } 7346 7347 // If this is not the end of the statement, report an error. 7348 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7349 reportParseError("unexpected token, expected end of statement"); 7350 return false; 7351 } 7352 7353 getTargetStreamer().emitDirectiveCpLoad(RegOpnd.getGPR32Reg()); 7354 return false; 7355 } 7356 7357 bool MipsAsmParser::parseDirectiveCpLocal(SMLoc Loc) { 7358 if (!isABI_N32() && !isABI_N64()) { 7359 reportParseError(".cplocal is allowed only in N32 or N64 mode"); 7360 return false; 7361 } 7362 7363 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg; 7364 OperandMatchResultTy ResTy = parseAnyRegister(Reg); 7365 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { 7366 reportParseError("expected register containing global pointer"); 7367 return false; 7368 } 7369 7370 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); 7371 if (!RegOpnd.isGPRAsmReg()) { 7372 reportParseError(RegOpnd.getStartLoc(), "invalid register"); 7373 return false; 7374 } 7375 7376 // If this is not the end of the statement, report an error. 7377 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7378 reportParseError("unexpected token, expected end of statement"); 7379 return false; 7380 } 7381 getParser().Lex(); // Consume the EndOfStatement. 7382 7383 unsigned NewReg = RegOpnd.getGPR32Reg(); 7384 if (IsPicEnabled) 7385 GPReg = NewReg; 7386 7387 getTargetStreamer().emitDirectiveCpLocal(NewReg); 7388 return false; 7389 } 7390 7391 bool MipsAsmParser::parseDirectiveCpRestore(SMLoc Loc) { 7392 MCAsmParser &Parser = getParser(); 7393 7394 // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it 7395 // is used in non-PIC mode. 7396 7397 if (inMips16Mode()) { 7398 reportParseError(".cprestore is not supported in Mips16 mode"); 7399 return false; 7400 } 7401 7402 // Get the stack offset value. 7403 const MCExpr *StackOffset; 7404 int64_t StackOffsetVal; 7405 if (Parser.parseExpression(StackOffset)) { 7406 reportParseError("expected stack offset value"); 7407 return false; 7408 } 7409 7410 if (!StackOffset->evaluateAsAbsolute(StackOffsetVal)) { 7411 reportParseError("stack offset is not an absolute expression"); 7412 return false; 7413 } 7414 7415 if (StackOffsetVal < 0) { 7416 Warning(Loc, ".cprestore with negative stack offset has no effect"); 7417 IsCpRestoreSet = false; 7418 } else { 7419 IsCpRestoreSet = true; 7420 CpRestoreOffset = StackOffsetVal; 7421 } 7422 7423 // If this is not the end of the statement, report an error. 7424 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7425 reportParseError("unexpected token, expected end of statement"); 7426 return false; 7427 } 7428 7429 if (!getTargetStreamer().emitDirectiveCpRestore( 7430 CpRestoreOffset, [&]() { return getATReg(Loc); }, Loc, STI)) 7431 return true; 7432 Parser.Lex(); // Consume the EndOfStatement. 7433 return false; 7434 } 7435 7436 bool MipsAsmParser::parseDirectiveCPSetup() { 7437 MCAsmParser &Parser = getParser(); 7438 unsigned FuncReg; 7439 unsigned Save; 7440 bool SaveIsReg = true; 7441 7442 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; 7443 OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); 7444 if (ResTy == MatchOperand_NoMatch) { 7445 reportParseError("expected register containing function address"); 7446 return false; 7447 } 7448 7449 MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]); 7450 if (!FuncRegOpnd.isGPRAsmReg()) { 7451 reportParseError(FuncRegOpnd.getStartLoc(), "invalid register"); 7452 return false; 7453 } 7454 7455 FuncReg = FuncRegOpnd.getGPR32Reg(); 7456 TmpReg.clear(); 7457 7458 if (!eatComma("unexpected token, expected comma")) 7459 return true; 7460 7461 ResTy = parseAnyRegister(TmpReg); 7462 if (ResTy == MatchOperand_NoMatch) { 7463 const MCExpr *OffsetExpr; 7464 int64_t OffsetVal; 7465 SMLoc ExprLoc = getLexer().getLoc(); 7466 7467 if (Parser.parseExpression(OffsetExpr) || 7468 !OffsetExpr->evaluateAsAbsolute(OffsetVal)) { 7469 reportParseError(ExprLoc, "expected save register or stack offset"); 7470 return false; 7471 } 7472 7473 Save = OffsetVal; 7474 SaveIsReg = false; 7475 } else { 7476 MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]); 7477 if (!SaveOpnd.isGPRAsmReg()) { 7478 reportParseError(SaveOpnd.getStartLoc(), "invalid register"); 7479 return false; 7480 } 7481 Save = SaveOpnd.getGPR32Reg(); 7482 } 7483 7484 if (!eatComma("unexpected token, expected comma")) 7485 return true; 7486 7487 const MCExpr *Expr; 7488 if (Parser.parseExpression(Expr)) { 7489 reportParseError("expected expression"); 7490 return false; 7491 } 7492 7493 if (Expr->getKind() != MCExpr::SymbolRef) { 7494 reportParseError("expected symbol"); 7495 return false; 7496 } 7497 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr); 7498 7499 CpSaveLocation = Save; 7500 CpSaveLocationIsRegister = SaveIsReg; 7501 7502 getTargetStreamer().emitDirectiveCpsetup(FuncReg, Save, Ref->getSymbol(), 7503 SaveIsReg); 7504 return false; 7505 } 7506 7507 bool MipsAsmParser::parseDirectiveCPReturn() { 7508 getTargetStreamer().emitDirectiveCpreturn(CpSaveLocation, 7509 CpSaveLocationIsRegister); 7510 return false; 7511 } 7512 7513 bool MipsAsmParser::parseDirectiveNaN() { 7514 MCAsmParser &Parser = getParser(); 7515 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7516 const AsmToken &Tok = Parser.getTok(); 7517 7518 if (Tok.getString() == "2008") { 7519 Parser.Lex(); 7520 getTargetStreamer().emitDirectiveNaN2008(); 7521 return false; 7522 } else if (Tok.getString() == "legacy") { 7523 Parser.Lex(); 7524 getTargetStreamer().emitDirectiveNaNLegacy(); 7525 return false; 7526 } 7527 } 7528 // If we don't recognize the option passed to the .nan 7529 // directive (e.g. no option or unknown option), emit an error. 7530 reportParseError("invalid option in .nan directive"); 7531 return false; 7532 } 7533 7534 bool MipsAsmParser::parseDirectiveSet() { 7535 const AsmToken &Tok = getParser().getTok(); 7536 StringRef IdVal = Tok.getString(); 7537 SMLoc Loc = Tok.getLoc(); 7538 7539 if (IdVal == "noat") 7540 return parseSetNoAtDirective(); 7541 if (IdVal == "at") 7542 return parseSetAtDirective(); 7543 if (IdVal == "arch") 7544 return parseSetArchDirective(); 7545 if (IdVal == "bopt") { 7546 Warning(Loc, "'bopt' feature is unsupported"); 7547 getParser().Lex(); 7548 return false; 7549 } 7550 if (IdVal == "nobopt") { 7551 // We're already running in nobopt mode, so nothing to do. 7552 getParser().Lex(); 7553 return false; 7554 } 7555 if (IdVal == "fp") 7556 return parseSetFpDirective(); 7557 if (IdVal == "oddspreg") 7558 return parseSetOddSPRegDirective(); 7559 if (IdVal == "nooddspreg") 7560 return parseSetNoOddSPRegDirective(); 7561 if (IdVal == "pop") 7562 return parseSetPopDirective(); 7563 if (IdVal == "push") 7564 return parseSetPushDirective(); 7565 if (IdVal == "reorder") 7566 return parseSetReorderDirective(); 7567 if (IdVal == "noreorder") 7568 return parseSetNoReorderDirective(); 7569 if (IdVal == "macro") 7570 return parseSetMacroDirective(); 7571 if (IdVal == "nomacro") 7572 return parseSetNoMacroDirective(); 7573 if (IdVal == "mips16") 7574 return parseSetMips16Directive(); 7575 if (IdVal == "nomips16") 7576 return parseSetNoMips16Directive(); 7577 if (IdVal == "nomicromips") { 7578 clearFeatureBits(Mips::FeatureMicroMips, "micromips"); 7579 getTargetStreamer().emitDirectiveSetNoMicroMips(); 7580 getParser().eatToEndOfStatement(); 7581 return false; 7582 } 7583 if (IdVal == "micromips") { 7584 if (hasMips64r6()) { 7585 Error(Loc, ".set micromips directive is not supported with MIPS64R6"); 7586 return false; 7587 } 7588 return parseSetFeature(Mips::FeatureMicroMips); 7589 } 7590 if (IdVal == "mips0") 7591 return parseSetMips0Directive(); 7592 if (IdVal == "mips1") 7593 return parseSetFeature(Mips::FeatureMips1); 7594 if (IdVal == "mips2") 7595 return parseSetFeature(Mips::FeatureMips2); 7596 if (IdVal == "mips3") 7597 return parseSetFeature(Mips::FeatureMips3); 7598 if (IdVal == "mips4") 7599 return parseSetFeature(Mips::FeatureMips4); 7600 if (IdVal == "mips5") 7601 return parseSetFeature(Mips::FeatureMips5); 7602 if (IdVal == "mips32") 7603 return parseSetFeature(Mips::FeatureMips32); 7604 if (IdVal == "mips32r2") 7605 return parseSetFeature(Mips::FeatureMips32r2); 7606 if (IdVal == "mips32r3") 7607 return parseSetFeature(Mips::FeatureMips32r3); 7608 if (IdVal == "mips32r5") 7609 return parseSetFeature(Mips::FeatureMips32r5); 7610 if (IdVal == "mips32r6") 7611 return parseSetFeature(Mips::FeatureMips32r6); 7612 if (IdVal == "mips64") 7613 return parseSetFeature(Mips::FeatureMips64); 7614 if (IdVal == "mips64r2") 7615 return parseSetFeature(Mips::FeatureMips64r2); 7616 if (IdVal == "mips64r3") 7617 return parseSetFeature(Mips::FeatureMips64r3); 7618 if (IdVal == "mips64r5") 7619 return parseSetFeature(Mips::FeatureMips64r5); 7620 if (IdVal == "mips64r6") { 7621 if (inMicroMipsMode()) { 7622 Error(Loc, "MIPS64R6 is not supported with microMIPS"); 7623 return false; 7624 } 7625 return parseSetFeature(Mips::FeatureMips64r6); 7626 } 7627 if (IdVal == "dsp") 7628 return parseSetFeature(Mips::FeatureDSP); 7629 if (IdVal == "dspr2") 7630 return parseSetFeature(Mips::FeatureDSPR2); 7631 if (IdVal == "nodsp") 7632 return parseSetNoDspDirective(); 7633 if (IdVal == "msa") 7634 return parseSetMsaDirective(); 7635 if (IdVal == "nomsa") 7636 return parseSetNoMsaDirective(); 7637 if (IdVal == "mt") 7638 return parseSetMtDirective(); 7639 if (IdVal == "nomt") 7640 return parseSetNoMtDirective(); 7641 if (IdVal == "softfloat") 7642 return parseSetSoftFloatDirective(); 7643 if (IdVal == "hardfloat") 7644 return parseSetHardFloatDirective(); 7645 if (IdVal == "crc") 7646 return parseSetFeature(Mips::FeatureCRC); 7647 if (IdVal == "nocrc") 7648 return parseSetNoCRCDirective(); 7649 if (IdVal == "virt") 7650 return parseSetFeature(Mips::FeatureVirt); 7651 if (IdVal == "novirt") 7652 return parseSetNoVirtDirective(); 7653 if (IdVal == "ginv") 7654 return parseSetFeature(Mips::FeatureGINV); 7655 if (IdVal == "noginv") 7656 return parseSetNoGINVDirective(); 7657 7658 // It is just an identifier, look for an assignment. 7659 return parseSetAssignment(); 7660 } 7661 7662 /// parseDirectiveGpWord 7663 /// ::= .gpword local_sym 7664 bool MipsAsmParser::parseDirectiveGpWord() { 7665 MCAsmParser &Parser = getParser(); 7666 const MCExpr *Value; 7667 // EmitGPRel32Value requires an expression, so we are using base class 7668 // method to evaluate the expression. 7669 if (getParser().parseExpression(Value)) 7670 return true; 7671 getParser().getStreamer().EmitGPRel32Value(Value); 7672 7673 if (getLexer().isNot(AsmToken::EndOfStatement)) 7674 return Error(getLexer().getLoc(), 7675 "unexpected token, expected end of statement"); 7676 Parser.Lex(); // Eat EndOfStatement token. 7677 return false; 7678 } 7679 7680 /// parseDirectiveGpDWord 7681 /// ::= .gpdword local_sym 7682 bool MipsAsmParser::parseDirectiveGpDWord() { 7683 MCAsmParser &Parser = getParser(); 7684 const MCExpr *Value; 7685 // EmitGPRel64Value requires an expression, so we are using base class 7686 // method to evaluate the expression. 7687 if (getParser().parseExpression(Value)) 7688 return true; 7689 getParser().getStreamer().EmitGPRel64Value(Value); 7690 7691 if (getLexer().isNot(AsmToken::EndOfStatement)) 7692 return Error(getLexer().getLoc(), 7693 "unexpected token, expected end of statement"); 7694 Parser.Lex(); // Eat EndOfStatement token. 7695 return false; 7696 } 7697 7698 /// parseDirectiveDtpRelWord 7699 /// ::= .dtprelword tls_sym 7700 bool MipsAsmParser::parseDirectiveDtpRelWord() { 7701 MCAsmParser &Parser = getParser(); 7702 const MCExpr *Value; 7703 // EmitDTPRel32Value requires an expression, so we are using base class 7704 // method to evaluate the expression. 7705 if (getParser().parseExpression(Value)) 7706 return true; 7707 getParser().getStreamer().EmitDTPRel32Value(Value); 7708 7709 if (getLexer().isNot(AsmToken::EndOfStatement)) 7710 return Error(getLexer().getLoc(), 7711 "unexpected token, expected end of statement"); 7712 Parser.Lex(); // Eat EndOfStatement token. 7713 return false; 7714 } 7715 7716 /// parseDirectiveDtpRelDWord 7717 /// ::= .dtpreldword tls_sym 7718 bool MipsAsmParser::parseDirectiveDtpRelDWord() { 7719 MCAsmParser &Parser = getParser(); 7720 const MCExpr *Value; 7721 // EmitDTPRel64Value requires an expression, so we are using base class 7722 // method to evaluate the expression. 7723 if (getParser().parseExpression(Value)) 7724 return true; 7725 getParser().getStreamer().EmitDTPRel64Value(Value); 7726 7727 if (getLexer().isNot(AsmToken::EndOfStatement)) 7728 return Error(getLexer().getLoc(), 7729 "unexpected token, expected end of statement"); 7730 Parser.Lex(); // Eat EndOfStatement token. 7731 return false; 7732 } 7733 7734 /// parseDirectiveTpRelWord 7735 /// ::= .tprelword tls_sym 7736 bool MipsAsmParser::parseDirectiveTpRelWord() { 7737 MCAsmParser &Parser = getParser(); 7738 const MCExpr *Value; 7739 // EmitTPRel32Value requires an expression, so we are using base class 7740 // method to evaluate the expression. 7741 if (getParser().parseExpression(Value)) 7742 return true; 7743 getParser().getStreamer().EmitTPRel32Value(Value); 7744 7745 if (getLexer().isNot(AsmToken::EndOfStatement)) 7746 return Error(getLexer().getLoc(), 7747 "unexpected token, expected end of statement"); 7748 Parser.Lex(); // Eat EndOfStatement token. 7749 return false; 7750 } 7751 7752 /// parseDirectiveTpRelDWord 7753 /// ::= .tpreldword tls_sym 7754 bool MipsAsmParser::parseDirectiveTpRelDWord() { 7755 MCAsmParser &Parser = getParser(); 7756 const MCExpr *Value; 7757 // EmitTPRel64Value requires an expression, so we are using base class 7758 // method to evaluate the expression. 7759 if (getParser().parseExpression(Value)) 7760 return true; 7761 getParser().getStreamer().EmitTPRel64Value(Value); 7762 7763 if (getLexer().isNot(AsmToken::EndOfStatement)) 7764 return Error(getLexer().getLoc(), 7765 "unexpected token, expected end of statement"); 7766 Parser.Lex(); // Eat EndOfStatement token. 7767 return false; 7768 } 7769 7770 bool MipsAsmParser::parseDirectiveOption() { 7771 MCAsmParser &Parser = getParser(); 7772 // Get the option token. 7773 AsmToken Tok = Parser.getTok(); 7774 // At the moment only identifiers are supported. 7775 if (Tok.isNot(AsmToken::Identifier)) { 7776 return Error(Parser.getTok().getLoc(), 7777 "unexpected token, expected identifier"); 7778 } 7779 7780 StringRef Option = Tok.getIdentifier(); 7781 7782 if (Option == "pic0") { 7783 // MipsAsmParser needs to know if the current PIC mode changes. 7784 IsPicEnabled = false; 7785 7786 getTargetStreamer().emitDirectiveOptionPic0(); 7787 Parser.Lex(); 7788 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7789 return Error(Parser.getTok().getLoc(), 7790 "unexpected token, expected end of statement"); 7791 } 7792 return false; 7793 } 7794 7795 if (Option == "pic2") { 7796 // MipsAsmParser needs to know if the current PIC mode changes. 7797 IsPicEnabled = true; 7798 7799 getTargetStreamer().emitDirectiveOptionPic2(); 7800 Parser.Lex(); 7801 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7802 return Error(Parser.getTok().getLoc(), 7803 "unexpected token, expected end of statement"); 7804 } 7805 return false; 7806 } 7807 7808 // Unknown option. 7809 Warning(Parser.getTok().getLoc(), 7810 "unknown option, expected 'pic0' or 'pic2'"); 7811 Parser.eatToEndOfStatement(); 7812 return false; 7813 } 7814 7815 /// parseInsnDirective 7816 /// ::= .insn 7817 bool MipsAsmParser::parseInsnDirective() { 7818 // If this is not the end of the statement, report an error. 7819 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7820 reportParseError("unexpected token, expected end of statement"); 7821 return false; 7822 } 7823 7824 // The actual label marking happens in 7825 // MipsELFStreamer::createPendingLabelRelocs(). 7826 getTargetStreamer().emitDirectiveInsn(); 7827 7828 getParser().Lex(); // Eat EndOfStatement token. 7829 return false; 7830 } 7831 7832 /// parseRSectionDirective 7833 /// ::= .rdata 7834 bool MipsAsmParser::parseRSectionDirective(StringRef Section) { 7835 // If this is not the end of the statement, report an error. 7836 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7837 reportParseError("unexpected token, expected end of statement"); 7838 return false; 7839 } 7840 7841 MCSection *ELFSection = getContext().getELFSection( 7842 Section, ELF::SHT_PROGBITS, ELF::SHF_ALLOC); 7843 getParser().getStreamer().SwitchSection(ELFSection); 7844 7845 getParser().Lex(); // Eat EndOfStatement token. 7846 return false; 7847 } 7848 7849 /// parseSSectionDirective 7850 /// ::= .sbss 7851 /// ::= .sdata 7852 bool MipsAsmParser::parseSSectionDirective(StringRef Section, unsigned Type) { 7853 // If this is not the end of the statement, report an error. 7854 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7855 reportParseError("unexpected token, expected end of statement"); 7856 return false; 7857 } 7858 7859 MCSection *ELFSection = getContext().getELFSection( 7860 Section, Type, ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_MIPS_GPREL); 7861 getParser().getStreamer().SwitchSection(ELFSection); 7862 7863 getParser().Lex(); // Eat EndOfStatement token. 7864 return false; 7865 } 7866 7867 /// parseDirectiveModule 7868 /// ::= .module oddspreg 7869 /// ::= .module nooddspreg 7870 /// ::= .module fp=value 7871 /// ::= .module softfloat 7872 /// ::= .module hardfloat 7873 /// ::= .module mt 7874 /// ::= .module crc 7875 /// ::= .module nocrc 7876 /// ::= .module virt 7877 /// ::= .module novirt 7878 /// ::= .module ginv 7879 /// ::= .module noginv 7880 bool MipsAsmParser::parseDirectiveModule() { 7881 MCAsmParser &Parser = getParser(); 7882 MCAsmLexer &Lexer = getLexer(); 7883 SMLoc L = Lexer.getLoc(); 7884 7885 if (!getTargetStreamer().isModuleDirectiveAllowed()) { 7886 // TODO : get a better message. 7887 reportParseError(".module directive must appear before any code"); 7888 return false; 7889 } 7890 7891 StringRef Option; 7892 if (Parser.parseIdentifier(Option)) { 7893 reportParseError("expected .module option identifier"); 7894 return false; 7895 } 7896 7897 if (Option == "oddspreg") { 7898 clearModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); 7899 7900 // Synchronize the abiflags information with the FeatureBits information we 7901 // changed above. 7902 getTargetStreamer().updateABIInfo(*this); 7903 7904 // If printing assembly, use the recently updated abiflags information. 7905 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 7906 // emitted at the end). 7907 getTargetStreamer().emitDirectiveModuleOddSPReg(); 7908 7909 // If this is not the end of the statement, report an error. 7910 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7911 reportParseError("unexpected token, expected end of statement"); 7912 return false; 7913 } 7914 7915 return false; // parseDirectiveModule has finished successfully. 7916 } else if (Option == "nooddspreg") { 7917 if (!isABI_O32()) { 7918 return Error(L, "'.module nooddspreg' requires the O32 ABI"); 7919 } 7920 7921 setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); 7922 7923 // Synchronize the abiflags information with the FeatureBits information we 7924 // changed above. 7925 getTargetStreamer().updateABIInfo(*this); 7926 7927 // If printing assembly, use the recently updated abiflags information. 7928 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 7929 // emitted at the end). 7930 getTargetStreamer().emitDirectiveModuleOddSPReg(); 7931 7932 // If this is not the end of the statement, report an error. 7933 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7934 reportParseError("unexpected token, expected end of statement"); 7935 return false; 7936 } 7937 7938 return false; // parseDirectiveModule has finished successfully. 7939 } else if (Option == "fp") { 7940 return parseDirectiveModuleFP(); 7941 } else if (Option == "softfloat") { 7942 setModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); 7943 7944 // Synchronize the ABI Flags information with the FeatureBits information we 7945 // updated above. 7946 getTargetStreamer().updateABIInfo(*this); 7947 7948 // If printing assembly, use the recently updated ABI Flags information. 7949 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 7950 // emitted later). 7951 getTargetStreamer().emitDirectiveModuleSoftFloat(); 7952 7953 // If this is not the end of the statement, report an error. 7954 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7955 reportParseError("unexpected token, expected end of statement"); 7956 return false; 7957 } 7958 7959 return false; // parseDirectiveModule has finished successfully. 7960 } else if (Option == "hardfloat") { 7961 clearModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); 7962 7963 // Synchronize the ABI Flags information with the FeatureBits information we 7964 // updated above. 7965 getTargetStreamer().updateABIInfo(*this); 7966 7967 // If printing assembly, use the recently updated ABI Flags information. 7968 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 7969 // emitted later). 7970 getTargetStreamer().emitDirectiveModuleHardFloat(); 7971 7972 // If this is not the end of the statement, report an error. 7973 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7974 reportParseError("unexpected token, expected end of statement"); 7975 return false; 7976 } 7977 7978 return false; // parseDirectiveModule has finished successfully. 7979 } else if (Option == "mt") { 7980 setModuleFeatureBits(Mips::FeatureMT, "mt"); 7981 7982 // Synchronize the ABI Flags information with the FeatureBits information we 7983 // updated above. 7984 getTargetStreamer().updateABIInfo(*this); 7985 7986 // If printing assembly, use the recently updated ABI Flags information. 7987 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 7988 // emitted later). 7989 getTargetStreamer().emitDirectiveModuleMT(); 7990 7991 // If this is not the end of the statement, report an error. 7992 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7993 reportParseError("unexpected token, expected end of statement"); 7994 return false; 7995 } 7996 7997 return false; // parseDirectiveModule has finished successfully. 7998 } else if (Option == "crc") { 7999 setModuleFeatureBits(Mips::FeatureCRC, "crc"); 8000 8001 // Synchronize the ABI Flags information with the FeatureBits information we 8002 // updated above. 8003 getTargetStreamer().updateABIInfo(*this); 8004 8005 // If printing assembly, use the recently updated ABI Flags information. 8006 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 8007 // emitted later). 8008 getTargetStreamer().emitDirectiveModuleCRC(); 8009 8010 // If this is not the end of the statement, report an error. 8011 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8012 reportParseError("unexpected token, expected end of statement"); 8013 return false; 8014 } 8015 8016 return false; // parseDirectiveModule has finished successfully. 8017 } else if (Option == "nocrc") { 8018 clearModuleFeatureBits(Mips::FeatureCRC, "crc"); 8019 8020 // Synchronize the ABI Flags information with the FeatureBits information we 8021 // updated above. 8022 getTargetStreamer().updateABIInfo(*this); 8023 8024 // If printing assembly, use the recently updated ABI Flags information. 8025 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 8026 // emitted later). 8027 getTargetStreamer().emitDirectiveModuleNoCRC(); 8028 8029 // If this is not the end of the statement, report an error. 8030 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8031 reportParseError("unexpected token, expected end of statement"); 8032 return false; 8033 } 8034 8035 return false; // parseDirectiveModule has finished successfully. 8036 } else if (Option == "virt") { 8037 setModuleFeatureBits(Mips::FeatureVirt, "virt"); 8038 8039 // Synchronize the ABI Flags information with the FeatureBits information we 8040 // updated above. 8041 getTargetStreamer().updateABIInfo(*this); 8042 8043 // If printing assembly, use the recently updated ABI Flags information. 8044 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 8045 // emitted later). 8046 getTargetStreamer().emitDirectiveModuleVirt(); 8047 8048 // If this is not the end of the statement, report an error. 8049 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8050 reportParseError("unexpected token, expected end of statement"); 8051 return false; 8052 } 8053 8054 return false; // parseDirectiveModule has finished successfully. 8055 } else if (Option == "novirt") { 8056 clearModuleFeatureBits(Mips::FeatureVirt, "virt"); 8057 8058 // Synchronize the ABI Flags information with the FeatureBits information we 8059 // updated above. 8060 getTargetStreamer().updateABIInfo(*this); 8061 8062 // If printing assembly, use the recently updated ABI Flags information. 8063 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 8064 // emitted later). 8065 getTargetStreamer().emitDirectiveModuleNoVirt(); 8066 8067 // If this is not the end of the statement, report an error. 8068 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8069 reportParseError("unexpected token, expected end of statement"); 8070 return false; 8071 } 8072 8073 return false; // parseDirectiveModule has finished successfully. 8074 } else if (Option == "ginv") { 8075 setModuleFeatureBits(Mips::FeatureGINV, "ginv"); 8076 8077 // Synchronize the ABI Flags information with the FeatureBits information we 8078 // updated above. 8079 getTargetStreamer().updateABIInfo(*this); 8080 8081 // If printing assembly, use the recently updated ABI Flags information. 8082 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 8083 // emitted later). 8084 getTargetStreamer().emitDirectiveModuleGINV(); 8085 8086 // If this is not the end of the statement, report an error. 8087 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8088 reportParseError("unexpected token, expected end of statement"); 8089 return false; 8090 } 8091 8092 return false; // parseDirectiveModule has finished successfully. 8093 } else if (Option == "noginv") { 8094 clearModuleFeatureBits(Mips::FeatureGINV, "ginv"); 8095 8096 // Synchronize the ABI Flags information with the FeatureBits information we 8097 // updated above. 8098 getTargetStreamer().updateABIInfo(*this); 8099 8100 // If printing assembly, use the recently updated ABI Flags information. 8101 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 8102 // emitted later). 8103 getTargetStreamer().emitDirectiveModuleNoGINV(); 8104 8105 // If this is not the end of the statement, report an error. 8106 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8107 reportParseError("unexpected token, expected end of statement"); 8108 return false; 8109 } 8110 8111 return false; // parseDirectiveModule has finished successfully. 8112 } else { 8113 return Error(L, "'" + Twine(Option) + "' is not a valid .module option."); 8114 } 8115 } 8116 8117 /// parseDirectiveModuleFP 8118 /// ::= =32 8119 /// ::= =xx 8120 /// ::= =64 8121 bool MipsAsmParser::parseDirectiveModuleFP() { 8122 MCAsmParser &Parser = getParser(); 8123 MCAsmLexer &Lexer = getLexer(); 8124 8125 if (Lexer.isNot(AsmToken::Equal)) { 8126 reportParseError("unexpected token, expected equals sign '='"); 8127 return false; 8128 } 8129 Parser.Lex(); // Eat '=' token. 8130 8131 MipsABIFlagsSection::FpABIKind FpABI; 8132 if (!parseFpABIValue(FpABI, ".module")) 8133 return false; 8134 8135 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8136 reportParseError("unexpected token, expected end of statement"); 8137 return false; 8138 } 8139 8140 // Synchronize the abiflags information with the FeatureBits information we 8141 // changed above. 8142 getTargetStreamer().updateABIInfo(*this); 8143 8144 // If printing assembly, use the recently updated abiflags information. 8145 // If generating ELF, don't do anything (the .MIPS.abiflags section gets 8146 // emitted at the end). 8147 getTargetStreamer().emitDirectiveModuleFP(); 8148 8149 Parser.Lex(); // Consume the EndOfStatement. 8150 return false; 8151 } 8152 8153 bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI, 8154 StringRef Directive) { 8155 MCAsmParser &Parser = getParser(); 8156 MCAsmLexer &Lexer = getLexer(); 8157 bool ModuleLevelOptions = Directive == ".module"; 8158 8159 if (Lexer.is(AsmToken::Identifier)) { 8160 StringRef Value = Parser.getTok().getString(); 8161 Parser.Lex(); 8162 8163 if (Value != "xx") { 8164 reportParseError("unsupported value, expected 'xx', '32' or '64'"); 8165 return false; 8166 } 8167 8168 if (!isABI_O32()) { 8169 reportParseError("'" + Directive + " fp=xx' requires the O32 ABI"); 8170 return false; 8171 } 8172 8173 FpABI = MipsABIFlagsSection::FpABIKind::XX; 8174 if (ModuleLevelOptions) { 8175 setModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); 8176 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); 8177 } else { 8178 setFeatureBits(Mips::FeatureFPXX, "fpxx"); 8179 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); 8180 } 8181 return true; 8182 } 8183 8184 if (Lexer.is(AsmToken::Integer)) { 8185 unsigned Value = Parser.getTok().getIntVal(); 8186 Parser.Lex(); 8187 8188 if (Value != 32 && Value != 64) { 8189 reportParseError("unsupported value, expected 'xx', '32' or '64'"); 8190 return false; 8191 } 8192 8193 if (Value == 32) { 8194 if (!isABI_O32()) { 8195 reportParseError("'" + Directive + " fp=32' requires the O32 ABI"); 8196 return false; 8197 } 8198 8199 FpABI = MipsABIFlagsSection::FpABIKind::S32; 8200 if (ModuleLevelOptions) { 8201 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); 8202 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); 8203 } else { 8204 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); 8205 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); 8206 } 8207 } else { 8208 FpABI = MipsABIFlagsSection::FpABIKind::S64; 8209 if (ModuleLevelOptions) { 8210 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); 8211 setModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); 8212 } else { 8213 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); 8214 setFeatureBits(Mips::FeatureFP64Bit, "fp64"); 8215 } 8216 } 8217 8218 return true; 8219 } 8220 8221 return false; 8222 } 8223 8224 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { 8225 // This returns false if this function recognizes the directive 8226 // regardless of whether it is successfully handles or reports an 8227 // error. Otherwise it returns true to give the generic parser a 8228 // chance at recognizing it. 8229 8230 MCAsmParser &Parser = getParser(); 8231 StringRef IDVal = DirectiveID.getString(); 8232 8233 if (IDVal == ".cpload") { 8234 parseDirectiveCpLoad(DirectiveID.getLoc()); 8235 return false; 8236 } 8237 if (IDVal == ".cprestore") { 8238 parseDirectiveCpRestore(DirectiveID.getLoc()); 8239 return false; 8240 } 8241 if (IDVal == ".cplocal") { 8242 parseDirectiveCpLocal(DirectiveID.getLoc()); 8243 return false; 8244 } 8245 if (IDVal == ".ent") { 8246 StringRef SymbolName; 8247 8248 if (Parser.parseIdentifier(SymbolName)) { 8249 reportParseError("expected identifier after .ent"); 8250 return false; 8251 } 8252 8253 // There's an undocumented extension that allows an integer to 8254 // follow the name of the procedure which AFAICS is ignored by GAS. 8255 // Example: .ent foo,2 8256 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8257 if (getLexer().isNot(AsmToken::Comma)) { 8258 // Even though we accept this undocumented extension for compatibility 8259 // reasons, the additional integer argument does not actually change 8260 // the behaviour of the '.ent' directive, so we would like to discourage 8261 // its use. We do this by not referring to the extended version in 8262 // error messages which are not directly related to its use. 8263 reportParseError("unexpected token, expected end of statement"); 8264 return false; 8265 } 8266 Parser.Lex(); // Eat the comma. 8267 const MCExpr *DummyNumber; 8268 int64_t DummyNumberVal; 8269 // If the user was explicitly trying to use the extended version, 8270 // we still give helpful extension-related error messages. 8271 if (Parser.parseExpression(DummyNumber)) { 8272 reportParseError("expected number after comma"); 8273 return false; 8274 } 8275 if (!DummyNumber->evaluateAsAbsolute(DummyNumberVal)) { 8276 reportParseError("expected an absolute expression after comma"); 8277 return false; 8278 } 8279 } 8280 8281 // If this is not the end of the statement, report an error. 8282 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8283 reportParseError("unexpected token, expected end of statement"); 8284 return false; 8285 } 8286 8287 MCSymbol *Sym = getContext().getOrCreateSymbol(SymbolName); 8288 8289 getTargetStreamer().emitDirectiveEnt(*Sym); 8290 CurrentFn = Sym; 8291 IsCpRestoreSet = false; 8292 return false; 8293 } 8294 8295 if (IDVal == ".end") { 8296 StringRef SymbolName; 8297 8298 if (Parser.parseIdentifier(SymbolName)) { 8299 reportParseError("expected identifier after .end"); 8300 return false; 8301 } 8302 8303 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8304 reportParseError("unexpected token, expected end of statement"); 8305 return false; 8306 } 8307 8308 if (CurrentFn == nullptr) { 8309 reportParseError(".end used without .ent"); 8310 return false; 8311 } 8312 8313 if ((SymbolName != CurrentFn->getName())) { 8314 reportParseError(".end symbol does not match .ent symbol"); 8315 return false; 8316 } 8317 8318 getTargetStreamer().emitDirectiveEnd(SymbolName); 8319 CurrentFn = nullptr; 8320 IsCpRestoreSet = false; 8321 return false; 8322 } 8323 8324 if (IDVal == ".frame") { 8325 // .frame $stack_reg, frame_size_in_bytes, $return_reg 8326 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; 8327 OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); 8328 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { 8329 reportParseError("expected stack register"); 8330 return false; 8331 } 8332 8333 MipsOperand &StackRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]); 8334 if (!StackRegOpnd.isGPRAsmReg()) { 8335 reportParseError(StackRegOpnd.getStartLoc(), 8336 "expected general purpose register"); 8337 return false; 8338 } 8339 unsigned StackReg = StackRegOpnd.getGPR32Reg(); 8340 8341 if (Parser.getTok().is(AsmToken::Comma)) 8342 Parser.Lex(); 8343 else { 8344 reportParseError("unexpected token, expected comma"); 8345 return false; 8346 } 8347 8348 // Parse the frame size. 8349 const MCExpr *FrameSize; 8350 int64_t FrameSizeVal; 8351 8352 if (Parser.parseExpression(FrameSize)) { 8353 reportParseError("expected frame size value"); 8354 return false; 8355 } 8356 8357 if (!FrameSize->evaluateAsAbsolute(FrameSizeVal)) { 8358 reportParseError("frame size not an absolute expression"); 8359 return false; 8360 } 8361 8362 if (Parser.getTok().is(AsmToken::Comma)) 8363 Parser.Lex(); 8364 else { 8365 reportParseError("unexpected token, expected comma"); 8366 return false; 8367 } 8368 8369 // Parse the return register. 8370 TmpReg.clear(); 8371 ResTy = parseAnyRegister(TmpReg); 8372 if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { 8373 reportParseError("expected return register"); 8374 return false; 8375 } 8376 8377 MipsOperand &ReturnRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]); 8378 if (!ReturnRegOpnd.isGPRAsmReg()) { 8379 reportParseError(ReturnRegOpnd.getStartLoc(), 8380 "expected general purpose register"); 8381 return false; 8382 } 8383 8384 // If this is not the end of the statement, report an error. 8385 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8386 reportParseError("unexpected token, expected end of statement"); 8387 return false; 8388 } 8389 8390 getTargetStreamer().emitFrame(StackReg, FrameSizeVal, 8391 ReturnRegOpnd.getGPR32Reg()); 8392 IsCpRestoreSet = false; 8393 return false; 8394 } 8395 8396 if (IDVal == ".set") { 8397 parseDirectiveSet(); 8398 return false; 8399 } 8400 8401 if (IDVal == ".mask" || IDVal == ".fmask") { 8402 // .mask bitmask, frame_offset 8403 // bitmask: One bit for each register used. 8404 // frame_offset: Offset from Canonical Frame Address ($sp on entry) where 8405 // first register is expected to be saved. 8406 // Examples: 8407 // .mask 0x80000000, -4 8408 // .fmask 0x80000000, -4 8409 // 8410 8411 // Parse the bitmask 8412 const MCExpr *BitMask; 8413 int64_t BitMaskVal; 8414 8415 if (Parser.parseExpression(BitMask)) { 8416 reportParseError("expected bitmask value"); 8417 return false; 8418 } 8419 8420 if (!BitMask->evaluateAsAbsolute(BitMaskVal)) { 8421 reportParseError("bitmask not an absolute expression"); 8422 return false; 8423 } 8424 8425 if (Parser.getTok().is(AsmToken::Comma)) 8426 Parser.Lex(); 8427 else { 8428 reportParseError("unexpected token, expected comma"); 8429 return false; 8430 } 8431 8432 // Parse the frame_offset 8433 const MCExpr *FrameOffset; 8434 int64_t FrameOffsetVal; 8435 8436 if (Parser.parseExpression(FrameOffset)) { 8437 reportParseError("expected frame offset value"); 8438 return false; 8439 } 8440 8441 if (!FrameOffset->evaluateAsAbsolute(FrameOffsetVal)) { 8442 reportParseError("frame offset not an absolute expression"); 8443 return false; 8444 } 8445 8446 // If this is not the end of the statement, report an error. 8447 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8448 reportParseError("unexpected token, expected end of statement"); 8449 return false; 8450 } 8451 8452 if (IDVal == ".mask") 8453 getTargetStreamer().emitMask(BitMaskVal, FrameOffsetVal); 8454 else 8455 getTargetStreamer().emitFMask(BitMaskVal, FrameOffsetVal); 8456 return false; 8457 } 8458 8459 if (IDVal == ".nan") 8460 return parseDirectiveNaN(); 8461 8462 if (IDVal == ".gpword") { 8463 parseDirectiveGpWord(); 8464 return false; 8465 } 8466 8467 if (IDVal == ".gpdword") { 8468 parseDirectiveGpDWord(); 8469 return false; 8470 } 8471 8472 if (IDVal == ".dtprelword") { 8473 parseDirectiveDtpRelWord(); 8474 return false; 8475 } 8476 8477 if (IDVal == ".dtpreldword") { 8478 parseDirectiveDtpRelDWord(); 8479 return false; 8480 } 8481 8482 if (IDVal == ".tprelword") { 8483 parseDirectiveTpRelWord(); 8484 return false; 8485 } 8486 8487 if (IDVal == ".tpreldword") { 8488 parseDirectiveTpRelDWord(); 8489 return false; 8490 } 8491 8492 if (IDVal == ".option") { 8493 parseDirectiveOption(); 8494 return false; 8495 } 8496 8497 if (IDVal == ".abicalls") { 8498 getTargetStreamer().emitDirectiveAbiCalls(); 8499 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 8500 Error(Parser.getTok().getLoc(), 8501 "unexpected token, expected end of statement"); 8502 } 8503 return false; 8504 } 8505 8506 if (IDVal == ".cpsetup") { 8507 parseDirectiveCPSetup(); 8508 return false; 8509 } 8510 if (IDVal == ".cpreturn") { 8511 parseDirectiveCPReturn(); 8512 return false; 8513 } 8514 if (IDVal == ".module") { 8515 parseDirectiveModule(); 8516 return false; 8517 } 8518 if (IDVal == ".llvm_internal_mips_reallow_module_directive") { 8519 parseInternalDirectiveReallowModule(); 8520 return false; 8521 } 8522 if (IDVal == ".insn") { 8523 parseInsnDirective(); 8524 return false; 8525 } 8526 if (IDVal == ".rdata") { 8527 parseRSectionDirective(".rodata"); 8528 return false; 8529 } 8530 if (IDVal == ".sbss") { 8531 parseSSectionDirective(IDVal, ELF::SHT_NOBITS); 8532 return false; 8533 } 8534 if (IDVal == ".sdata") { 8535 parseSSectionDirective(IDVal, ELF::SHT_PROGBITS); 8536 return false; 8537 } 8538 8539 return true; 8540 } 8541 8542 bool MipsAsmParser::parseInternalDirectiveReallowModule() { 8543 // If this is not the end of the statement, report an error. 8544 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8545 reportParseError("unexpected token, expected end of statement"); 8546 return false; 8547 } 8548 8549 getTargetStreamer().reallowModuleDirective(); 8550 8551 getParser().Lex(); // Eat EndOfStatement token. 8552 return false; 8553 } 8554 8555 extern "C" void LLVMInitializeMipsAsmParser() { 8556 RegisterMCAsmParser<MipsAsmParser> X(getTheMipsTarget()); 8557 RegisterMCAsmParser<MipsAsmParser> Y(getTheMipselTarget()); 8558 RegisterMCAsmParser<MipsAsmParser> A(getTheMips64Target()); 8559 RegisterMCAsmParser<MipsAsmParser> B(getTheMips64elTarget()); 8560 } 8561 8562 #define GET_REGISTER_MATCHER 8563 #define GET_MATCHER_IMPLEMENTATION 8564 #define GET_MNEMONIC_SPELL_CHECKER 8565 #include "MipsGenAsmMatcher.inc" 8566 8567 bool MipsAsmParser::mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) { 8568 // Find the appropriate table for this asm variant. 8569 const MatchEntry *Start, *End; 8570 switch (VariantID) { 8571 default: llvm_unreachable("invalid variant!"); 8572 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 8573 } 8574 // Search the table. 8575 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 8576 return MnemonicRange.first != MnemonicRange.second; 8577 } 8578