1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "msp430-reg-info"
15 
16 #include "MSP430.h"
17 #include "MSP430MachineFunctionInfo.h"
18 #include "MSP430RegisterInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/Support/ErrorHandling.h"
27 
28 using namespace llvm;
29 
30 // FIXME: Provide proper call frame setup / destroy opcodes.
31 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
32                                        const TargetInstrInfo &tii)
33   : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
34     TM(tm), TII(tii) {
35   StackAlign = TM.getFrameInfo()->getStackAlignment();
36 }
37 
38 const unsigned*
39 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40   static const unsigned CalleeSavedRegs[] = {
41     MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
42     MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
43     0
44   };
45 
46   return CalleeSavedRegs;
47 }
48 
49 const TargetRegisterClass *const *
50 MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
51   static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
52     &MSP430::GR16RegClass, &MSP430::GR16RegClass,
53     &MSP430::GR16RegClass, &MSP430::GR16RegClass,
54     &MSP430::GR16RegClass, &MSP430::GR16RegClass,
55     &MSP430::GR16RegClass, &MSP430::GR16RegClass,
56     0
57   };
58 
59   return CalleeSavedRegClasses;
60 }
61 
62 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
63   BitVector Reserved(getNumRegs());
64 
65   // Mark 4 special registers as reserved.
66   Reserved.set(MSP430::PCW);
67   Reserved.set(MSP430::SPW);
68   Reserved.set(MSP430::SRW);
69   Reserved.set(MSP430::CGW);
70 
71   // Mark frame pointer as reserved if needed.
72   if (hasFP(MF))
73     Reserved.set(MSP430::FPW);
74 
75   return Reserved;
76 }
77 
78 const TargetRegisterClass *
79 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
80   return &MSP430::GR16RegClass;
81 }
82 
83 
84 bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
85   return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
86 }
87 
88 bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
89   return !MF.getFrameInfo()->hasVarSizedObjects();
90 }
91 
92 void MSP430RegisterInfo::
93 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
94                               MachineBasicBlock::iterator I) const {
95   if (!hasReservedCallFrame(MF)) {
96     // If the stack pointer can be changed after prologue, turn the
97     // adjcallstackup instruction into a 'sub SPW, <amt>' and the
98     // adjcallstackdown instruction into 'add SPW, <amt>'
99     // TODO: consider using push / pop instead of sub + store / add
100     MachineInstr *Old = I;
101     uint64_t Amount = Old->getOperand(0).getImm();
102     if (Amount != 0) {
103       // We need to keep the stack aligned properly.  To do this, we round the
104       // amount of space needed for the outgoing arguments up to the next
105       // alignment boundary.
106       Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
107 
108       MachineInstr *New = 0;
109       if (Old->getOpcode() == getCallFrameSetupOpcode()) {
110         New = BuildMI(MF, Old->getDebugLoc(),
111                       TII.get(MSP430::SUB16ri), MSP430::SPW)
112           .addReg(MSP430::SPW).addImm(Amount);
113       } else {
114         assert(Old->getOpcode() == getCallFrameDestroyOpcode());
115         // factor out the amount the callee already popped.
116         uint64_t CalleeAmt = Old->getOperand(1).getImm();
117         Amount -= CalleeAmt;
118         if (Amount)
119           New = BuildMI(MF, Old->getDebugLoc(),
120                         TII.get(MSP430::ADD16ri), MSP430::SPW)
121             .addReg(MSP430::SPW).addImm(Amount);
122       }
123 
124       if (New) {
125         // The SRW implicit def is dead.
126         New->getOperand(3).setIsDead();
127 
128         // Replace the pseudo instruction with a new instruction...
129         MBB.insert(I, New);
130       }
131     }
132   } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
133     // If we are performing frame pointer elimination and if the callee pops
134     // something off the stack pointer, add it back.
135     if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
136       MachineInstr *Old = I;
137       MachineInstr *New =
138         BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
139                 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
140       // The SRW implicit def is dead.
141       New->getOperand(3).setIsDead();
142 
143       MBB.insert(I, New);
144     }
145   }
146 
147   MBB.erase(I);
148 }
149 
150 void
151 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
152                                         int SPAdj, RegScavenger *RS) const {
153   assert(SPAdj == 0 && "Unexpected");
154 
155   unsigned i = 0;
156   MachineInstr &MI = *II;
157   MachineBasicBlock &MBB = *MI.getParent();
158   MachineFunction &MF = *MBB.getParent();
159   DebugLoc dl = MI.getDebugLoc();
160   while (!MI.getOperand(i).isFI()) {
161     ++i;
162     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
163   }
164 
165   int FrameIndex = MI.getOperand(i).getIndex();
166 
167   unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
168   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
169 
170   // Skip the saved PC
171   Offset += 2;
172 
173   if (!hasFP(MF))
174     Offset += MF.getFrameInfo()->getStackSize();
175   else
176     Offset += 2; // Skip the saved FPW
177 
178   // Fold imm into offset
179   Offset += MI.getOperand(i+1).getImm();
180 
181   if (MI.getOpcode() == MSP430::ADD16ri) {
182     // This is actually "load effective address" of the stack slot
183     // instruction. We have only two-address instructions, thus we need to
184     // expand it into mov + add
185 
186     MI.setDesc(TII.get(MSP430::MOV16rr));
187     MI.getOperand(i).ChangeToRegister(BasePtr, false);
188 
189     if (Offset == 0)
190       return;
191 
192     // We need to materialize the offset via add instruction.
193     unsigned DstReg = MI.getOperand(0).getReg();
194     if (Offset < 0)
195       BuildMI(MBB, next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
196         .addReg(DstReg).addImm(-Offset);
197     else
198       BuildMI(MBB, next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
199         .addReg(DstReg).addImm(Offset);
200 
201     return;
202   }
203 
204   MI.getOperand(i).ChangeToRegister(BasePtr, false);
205   MI.getOperand(i+1).ChangeToImmediate(Offset);
206 }
207 
208 void
209 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
210                                                                          const {
211   // Create a frame entry for the FPW register that must be saved.
212   if (hasFP(MF)) {
213     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4);
214     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
215            "Slot for FPW register must be last in order to be found!");
216     FrameIdx = 0;
217   }
218 }
219 
220 
221 void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
222   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
223   MachineFrameInfo *MFI = MF.getFrameInfo();
224   MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
225   MachineBasicBlock::iterator MBBI = MBB.begin();
226   DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
227                  DebugLoc::getUnknownLoc());
228 
229   // Get the number of bytes to allocate from the FrameInfo.
230   uint64_t StackSize = MFI->getStackSize();
231 
232   uint64_t NumBytes = 0;
233   if (hasFP(MF)) {
234     // Calculate required stack adjustment
235     uint64_t FrameSize = StackSize - 2;
236     NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
237 
238     // Get the offset of the stack slot for the EBP register... which is
239     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
240     // Update the frame offset adjustment.
241     MFI->setOffsetAdjustment(-NumBytes);
242 
243     // Save FPW into the appropriate stack slot...
244     BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
245       .addReg(MSP430::FPW, RegState::Kill);
246 
247     // Update FPW with the new base value...
248     BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
249       .addReg(MSP430::SPW);
250 
251     // Mark the FramePtr as live-in in every block except the entry.
252     for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
253          I != E; ++I)
254       I->addLiveIn(MSP430::FPW);
255 
256   } else
257     NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
258 
259   // Skip the callee-saved push instructions.
260   while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
261     ++MBBI;
262 
263   if (MBBI != MBB.end())
264     DL = MBBI->getDebugLoc();
265 
266   if (NumBytes) { // adjust stack pointer: SPW -= numbytes
267     // If there is an SUB16ri of SPW immediately before this instruction, merge
268     // the two.
269     //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
270     // If there is an ADD16ri or SUB16ri of SPW immediately after this
271     // instruction, merge the two instructions.
272     // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
273 
274     if (NumBytes) {
275       MachineInstr *MI =
276         BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
277         .addReg(MSP430::SPW).addImm(NumBytes);
278       // The SRW implicit def is dead.
279       MI->getOperand(3).setIsDead();
280     }
281   }
282 }
283 
284 void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
285                                       MachineBasicBlock &MBB) const {
286   const MachineFrameInfo *MFI = MF.getFrameInfo();
287   MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
288   MachineBasicBlock::iterator MBBI = prior(MBB.end());
289   unsigned RetOpcode = MBBI->getOpcode();
290   DebugLoc DL = MBBI->getDebugLoc();
291 
292   switch (RetOpcode) {
293   case MSP430::RET: break;  // These are ok
294   default:
295     llvm_unreachable("Can only insert epilog into returning blocks");
296   }
297 
298   // Get the number of bytes to allocate from the FrameInfo
299   uint64_t StackSize = MFI->getStackSize();
300   unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
301   uint64_t NumBytes = 0;
302 
303   if (hasFP(MF)) {
304     // Calculate required stack adjustment
305     uint64_t FrameSize = StackSize - 2;
306     NumBytes = FrameSize - CSSize;
307 
308     // pop FPW.
309     BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
310   } else
311     NumBytes = StackSize - CSSize;
312 
313   // Skip the callee-saved pop instructions.
314   while (MBBI != MBB.begin()) {
315     MachineBasicBlock::iterator PI = prior(MBBI);
316     unsigned Opc = PI->getOpcode();
317     if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
318       break;
319     --MBBI;
320   }
321 
322   DL = MBBI->getDebugLoc();
323 
324   // If there is an ADD16ri or SUB16ri of SPW immediately before this
325   // instruction, merge the two instructions.
326   //if (NumBytes || MFI->hasVarSizedObjects())
327   //  mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
328 
329   if (MFI->hasVarSizedObjects()) {
330     BuildMI(MBB, MBBI, DL,
331             TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
332     if (CSSize) {
333       MachineInstr *MI =
334         BuildMI(MBB, MBBI, DL,
335                 TII.get(MSP430::SUB16ri), MSP430::SPW)
336         .addReg(MSP430::SPW).addImm(CSSize);
337       // The SRW implicit def is dead.
338       MI->getOperand(3).setIsDead();
339     }
340   } else {
341     // adjust stack pointer back: SPW += numbytes
342     if (NumBytes) {
343       MachineInstr *MI =
344         BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
345         .addReg(MSP430::SPW).addImm(NumBytes);
346       // The SRW implicit def is dead.
347       MI->getOperand(3).setIsDead();
348     }
349   }
350 }
351 
352 unsigned MSP430RegisterInfo::getRARegister() const {
353   return MSP430::PCW;
354 }
355 
356 unsigned MSP430RegisterInfo::getFrameRegister(MachineFunction &MF) const {
357   return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
358 }
359 
360 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
361   llvm_unreachable("Not implemented yet!");
362   return 0;
363 }
364 
365 #include "MSP430GenRegisterInfo.inc"
366