1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MSP430.h"
15 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "MSP430GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
25 
26 using namespace llvm;
27 
28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
29   : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
30     RI(tm, *this), TM(tm) {}
31 
32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
33                                           MachineBasicBlock::iterator MI,
34                                     unsigned SrcReg, bool isKill, int FrameIdx,
35                                           const TargetRegisterClass *RC,
36                                           const TargetRegisterInfo *TRI) const {
37   DebugLoc DL;
38   if (MI != MBB.end()) DL = MI->getDebugLoc();
39   MachineFunction &MF = *MBB.getParent();
40   MachineFrameInfo &MFI = *MF.getFrameInfo();
41 
42   MachineMemOperand *MMO =
43     MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
44                             MachineMemOperand::MOStore, 0,
45                             MFI.getObjectSize(FrameIdx),
46                             MFI.getObjectAlignment(FrameIdx));
47 
48   if (RC == &MSP430::GR16RegClass)
49     BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
50       .addFrameIndex(FrameIdx).addImm(0)
51       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
52   else if (RC == &MSP430::GR8RegClass)
53     BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
54       .addFrameIndex(FrameIdx).addImm(0)
55       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56   else
57     llvm_unreachable("Cannot store this register to stack slot!");
58 }
59 
60 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
61                                            MachineBasicBlock::iterator MI,
62                                            unsigned DestReg, int FrameIdx,
63                                            const TargetRegisterClass *RC,
64                                            const TargetRegisterInfo *TRI) const{
65   DebugLoc DL;
66   if (MI != MBB.end()) DL = MI->getDebugLoc();
67   MachineFunction &MF = *MBB.getParent();
68   MachineFrameInfo &MFI = *MF.getFrameInfo();
69 
70   MachineMemOperand *MMO =
71     MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
72                             MachineMemOperand::MOLoad, 0,
73                             MFI.getObjectSize(FrameIdx),
74                             MFI.getObjectAlignment(FrameIdx));
75 
76   if (RC == &MSP430::GR16RegClass)
77     BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
78       .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
79   else if (RC == &MSP430::GR8RegClass)
80     BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
81       .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
82   else
83     llvm_unreachable("Cannot store this register to stack slot!");
84 }
85 
86 bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
87                                    MachineBasicBlock::iterator I,
88                                    unsigned DestReg, unsigned SrcReg,
89                                    const TargetRegisterClass *DestRC,
90                                    const TargetRegisterClass *SrcRC,
91                                    DebugLoc DL) const {
92   if (DestRC == SrcRC) {
93     unsigned Opc;
94     if (DestRC == &MSP430::GR16RegClass) {
95       Opc = MSP430::MOV16rr;
96     } else if (DestRC == &MSP430::GR8RegClass) {
97       Opc = MSP430::MOV8rr;
98     } else {
99       return false;
100     }
101 
102     BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
103     return true;
104   }
105 
106   return false;
107 }
108 
109 bool
110 MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
111                              unsigned &SrcReg, unsigned &DstReg,
112                              unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
113   SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
114 
115   switch (MI.getOpcode()) {
116   default:
117     return false;
118   case MSP430::MOV8rr:
119   case MSP430::MOV16rr:
120    assert(MI.getNumOperands() >= 2 &&
121            MI.getOperand(0).isReg() &&
122            MI.getOperand(1).isReg() &&
123            "invalid register-register move instruction");
124     SrcReg = MI.getOperand(1).getReg();
125     DstReg = MI.getOperand(0).getReg();
126     return true;
127   }
128 }
129 
130 bool
131 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
132                                            MachineBasicBlock::iterator MI,
133                                 const std::vector<CalleeSavedInfo> &CSI) const {
134   if (CSI.empty())
135     return false;
136 
137   DebugLoc DL;
138   if (MI != MBB.end()) DL = MI->getDebugLoc();
139 
140   MachineFunction &MF = *MBB.getParent();
141   MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
142   MFI->setCalleeSavedFrameSize(CSI.size() * 2);
143 
144   for (unsigned i = CSI.size(); i != 0; --i) {
145     unsigned Reg = CSI[i-1].getReg();
146     // Add the callee-saved register as live-in. It's killed at the spill.
147     MBB.addLiveIn(Reg);
148     BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
149       .addReg(Reg, RegState::Kill);
150   }
151   return true;
152 }
153 
154 bool
155 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
156                                              MachineBasicBlock::iterator MI,
157                                 const std::vector<CalleeSavedInfo> &CSI) const {
158   if (CSI.empty())
159     return false;
160 
161   DebugLoc DL;
162   if (MI != MBB.end()) DL = MI->getDebugLoc();
163 
164   for (unsigned i = 0, e = CSI.size(); i != e; ++i)
165     BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
166 
167   return true;
168 }
169 
170 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
171   MachineBasicBlock::iterator I = MBB.end();
172   unsigned Count = 0;
173 
174   while (I != MBB.begin()) {
175     --I;
176     if (I->isDebugValue())
177       continue;
178     if (I->getOpcode() != MSP430::JMP &&
179         I->getOpcode() != MSP430::JCC &&
180         I->getOpcode() != MSP430::Br &&
181         I->getOpcode() != MSP430::Bm)
182       break;
183     // Remove the branch.
184     I->eraseFromParent();
185     I = MBB.end();
186     ++Count;
187   }
188 
189   return Count;
190 }
191 
192 bool MSP430InstrInfo::
193 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
194   assert(Cond.size() == 1 && "Invalid Xbranch condition!");
195 
196   MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
197 
198   switch (CC) {
199   default:
200     assert(0 && "Invalid branch condition!");
201     break;
202   case MSP430CC::COND_E:
203     CC = MSP430CC::COND_NE;
204     break;
205   case MSP430CC::COND_NE:
206     CC = MSP430CC::COND_E;
207     break;
208   case MSP430CC::COND_L:
209     CC = MSP430CC::COND_GE;
210     break;
211   case MSP430CC::COND_GE:
212     CC = MSP430CC::COND_L;
213     break;
214   case MSP430CC::COND_HS:
215     CC = MSP430CC::COND_LO;
216     break;
217   case MSP430CC::COND_LO:
218     CC = MSP430CC::COND_HS;
219     break;
220   }
221 
222   Cond[0].setImm(CC);
223   return false;
224 }
225 
226 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
227   const TargetInstrDesc &TID = MI->getDesc();
228   if (!TID.isTerminator()) return false;
229 
230   // Conditional branch is a special case.
231   if (TID.isBranch() && !TID.isBarrier())
232     return true;
233   if (!TID.isPredicable())
234     return true;
235   return !isPredicated(MI);
236 }
237 
238 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
239                                     MachineBasicBlock *&TBB,
240                                     MachineBasicBlock *&FBB,
241                                     SmallVectorImpl<MachineOperand> &Cond,
242                                     bool AllowModify) const {
243   // Start from the bottom of the block and work up, examining the
244   // terminator instructions.
245   MachineBasicBlock::iterator I = MBB.end();
246   while (I != MBB.begin()) {
247     --I;
248     if (I->isDebugValue())
249       continue;
250 
251     // Working from the bottom, when we see a non-terminator
252     // instruction, we're done.
253     if (!isUnpredicatedTerminator(I))
254       break;
255 
256     // A terminator that isn't a branch can't easily be handled
257     // by this analysis.
258     if (!I->getDesc().isBranch())
259       return true;
260 
261     // Cannot handle indirect branches.
262     if (I->getOpcode() == MSP430::Br ||
263         I->getOpcode() == MSP430::Bm)
264       return true;
265 
266     // Handle unconditional branches.
267     if (I->getOpcode() == MSP430::JMP) {
268       if (!AllowModify) {
269         TBB = I->getOperand(0).getMBB();
270         continue;
271       }
272 
273       // If the block has any instructions after a JMP, delete them.
274       while (llvm::next(I) != MBB.end())
275         llvm::next(I)->eraseFromParent();
276       Cond.clear();
277       FBB = 0;
278 
279       // Delete the JMP if it's equivalent to a fall-through.
280       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
281         TBB = 0;
282         I->eraseFromParent();
283         I = MBB.end();
284         continue;
285       }
286 
287       // TBB is used to indicate the unconditinal destination.
288       TBB = I->getOperand(0).getMBB();
289       continue;
290     }
291 
292     // Handle conditional branches.
293     assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
294     MSP430CC::CondCodes BranchCode =
295       static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
296     if (BranchCode == MSP430CC::COND_INVALID)
297       return true;  // Can't handle weird stuff.
298 
299     // Working from the bottom, handle the first conditional branch.
300     if (Cond.empty()) {
301       FBB = TBB;
302       TBB = I->getOperand(0).getMBB();
303       Cond.push_back(MachineOperand::CreateImm(BranchCode));
304       continue;
305     }
306 
307     // Handle subsequent conditional branches. Only handle the case where all
308     // conditional branches branch to the same destination.
309     assert(Cond.size() == 1);
310     assert(TBB);
311 
312     // Only handle the case where all conditional branches branch to
313     // the same destination.
314     if (TBB != I->getOperand(0).getMBB())
315       return true;
316 
317     MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
318     // If the conditions are the same, we can leave them alone.
319     if (OldBranchCode == BranchCode)
320       continue;
321 
322     return true;
323   }
324 
325   return false;
326 }
327 
328 unsigned
329 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
330                               MachineBasicBlock *FBB,
331                             const SmallVectorImpl<MachineOperand> &Cond) const {
332   // FIXME this should probably have a DebugLoc operand
333   DebugLoc DL;
334 
335   // Shouldn't be a fall through.
336   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
337   assert((Cond.size() == 1 || Cond.size() == 0) &&
338          "MSP430 branch conditions have one component!");
339 
340   if (Cond.empty()) {
341     // Unconditional branch?
342     assert(!FBB && "Unconditional branch with multiple successors!");
343     BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
344     return 1;
345   }
346 
347   // Conditional branch.
348   unsigned Count = 0;
349   BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
350   ++Count;
351 
352   if (FBB) {
353     // Two-way Conditional branch. Insert the second branch.
354     BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
355     ++Count;
356   }
357   return Count;
358 }
359 
360 /// GetInstSize - Return the number of bytes of code the specified
361 /// instruction may be.  This returns the maximum number of bytes.
362 ///
363 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
364   const TargetInstrDesc &Desc = MI->getDesc();
365 
366   switch (Desc.TSFlags & MSP430II::SizeMask) {
367   default:
368     switch (Desc.getOpcode()) {
369     default:
370       assert(0 && "Unknown instruction size!");
371     case TargetOpcode::DBG_LABEL:
372     case TargetOpcode::EH_LABEL:
373     case TargetOpcode::IMPLICIT_DEF:
374     case TargetOpcode::KILL:
375     case TargetOpcode::DBG_VALUE:
376       return 0;
377     case TargetOpcode::INLINEASM: {
378       const MachineFunction *MF = MI->getParent()->getParent();
379       const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
380       return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
381                                     *MF->getTarget().getMCAsmInfo());
382     }
383     }
384   case MSP430II::SizeSpecial:
385     switch (MI->getOpcode()) {
386     default:
387       assert(0 && "Unknown instruction size!");
388     case MSP430::SAR8r1c:
389     case MSP430::SAR16r1c:
390       return 4;
391     }
392   case MSP430II::Size2Bytes:
393     return 2;
394   case MSP430II::Size4Bytes:
395     return 4;
396   case MSP430II::Size6Bytes:
397     return 6;
398   }
399 
400   return 6;
401 }
402