1 //===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MSP430InstrInfo.h"
15 #include "MSP430.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 using namespace llvm;
26 
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "MSP430GenInstrInfo.inc"
29 
30 // Pin the vtable to this file.
31 void MSP430InstrInfo::anchor() {}
32 
33 MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI)
34   : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
35     RI() {}
36 
37 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
38                                           MachineBasicBlock::iterator MI,
39                                     unsigned SrcReg, bool isKill, int FrameIdx,
40                                           const TargetRegisterClass *RC,
41                                           const TargetRegisterInfo *TRI) const {
42   DebugLoc DL;
43   if (MI != MBB.end()) DL = MI->getDebugLoc();
44   MachineFunction &MF = *MBB.getParent();
45   MachineFrameInfo &MFI = MF.getFrameInfo();
46 
47   MachineMemOperand *MMO = MF.getMachineMemOperand(
48       MachinePointerInfo::getFixedStack(MF, FrameIdx),
49       MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
50       MFI.getObjectAlignment(FrameIdx));
51 
52   if (RC == &MSP430::GR16RegClass)
53     BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
54       .addFrameIndex(FrameIdx).addImm(0)
55       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56   else if (RC == &MSP430::GR8RegClass)
57     BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
58       .addFrameIndex(FrameIdx).addImm(0)
59       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
60   else
61     llvm_unreachable("Cannot store this register to stack slot!");
62 }
63 
64 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
65                                            MachineBasicBlock::iterator MI,
66                                            unsigned DestReg, int FrameIdx,
67                                            const TargetRegisterClass *RC,
68                                            const TargetRegisterInfo *TRI) const{
69   DebugLoc DL;
70   if (MI != MBB.end()) DL = MI->getDebugLoc();
71   MachineFunction &MF = *MBB.getParent();
72   MachineFrameInfo &MFI = MF.getFrameInfo();
73 
74   MachineMemOperand *MMO = MF.getMachineMemOperand(
75       MachinePointerInfo::getFixedStack(MF, FrameIdx),
76       MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
77       MFI.getObjectAlignment(FrameIdx));
78 
79   if (RC == &MSP430::GR16RegClass)
80     BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
81       .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
82       .addImm(0).addMemOperand(MMO);
83   else if (RC == &MSP430::GR8RegClass)
84     BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
85       .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
86       .addImm(0).addMemOperand(MMO);
87   else
88     llvm_unreachable("Cannot store this register to stack slot!");
89 }
90 
91 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
92                                   MachineBasicBlock::iterator I,
93                                   const DebugLoc &DL, unsigned DestReg,
94                                   unsigned SrcReg, bool KillSrc) const {
95   unsigned Opc;
96   if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
97     Opc = MSP430::MOV16rr;
98   else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
99     Opc = MSP430::MOV8rr;
100   else
101     llvm_unreachable("Impossible reg-to-reg copy");
102 
103   BuildMI(MBB, I, DL, get(Opc), DestReg)
104     .addReg(SrcReg, getKillRegState(KillSrc));
105 }
106 
107 unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
108                                        int *BytesRemoved) const {
109   assert(!BytesRemoved && "code size not handled");
110 
111   MachineBasicBlock::iterator I = MBB.end();
112   unsigned Count = 0;
113 
114   while (I != MBB.begin()) {
115     --I;
116     if (I->isDebugValue())
117       continue;
118     if (I->getOpcode() != MSP430::JMP &&
119         I->getOpcode() != MSP430::JCC &&
120         I->getOpcode() != MSP430::Br &&
121         I->getOpcode() != MSP430::Bm)
122       break;
123     // Remove the branch.
124     I->eraseFromParent();
125     I = MBB.end();
126     ++Count;
127   }
128 
129   return Count;
130 }
131 
132 bool MSP430InstrInfo::
133 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
134   assert(Cond.size() == 1 && "Invalid Xbranch condition!");
135 
136   MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
137 
138   switch (CC) {
139   default: llvm_unreachable("Invalid branch condition!");
140   case MSP430CC::COND_E:
141     CC = MSP430CC::COND_NE;
142     break;
143   case MSP430CC::COND_NE:
144     CC = MSP430CC::COND_E;
145     break;
146   case MSP430CC::COND_L:
147     CC = MSP430CC::COND_GE;
148     break;
149   case MSP430CC::COND_GE:
150     CC = MSP430CC::COND_L;
151     break;
152   case MSP430CC::COND_HS:
153     CC = MSP430CC::COND_LO;
154     break;
155   case MSP430CC::COND_LO:
156     CC = MSP430CC::COND_HS;
157     break;
158   }
159 
160   Cond[0].setImm(CC);
161   return false;
162 }
163 
164 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
165   if (!MI.isTerminator())
166     return false;
167 
168   // Conditional branch is a special case.
169   if (MI.isBranch() && !MI.isBarrier())
170     return true;
171   if (!MI.isPredicable())
172     return true;
173   return !isPredicated(MI);
174 }
175 
176 bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
177                                     MachineBasicBlock *&TBB,
178                                     MachineBasicBlock *&FBB,
179                                     SmallVectorImpl<MachineOperand> &Cond,
180                                     bool AllowModify) const {
181   // Start from the bottom of the block and work up, examining the
182   // terminator instructions.
183   MachineBasicBlock::iterator I = MBB.end();
184   while (I != MBB.begin()) {
185     --I;
186     if (I->isDebugValue())
187       continue;
188 
189     // Working from the bottom, when we see a non-terminator
190     // instruction, we're done.
191     if (!isUnpredicatedTerminator(*I))
192       break;
193 
194     // A terminator that isn't a branch can't easily be handled
195     // by this analysis.
196     if (!I->isBranch())
197       return true;
198 
199     // Cannot handle indirect branches.
200     if (I->getOpcode() == MSP430::Br ||
201         I->getOpcode() == MSP430::Bm)
202       return true;
203 
204     // Handle unconditional branches.
205     if (I->getOpcode() == MSP430::JMP) {
206       if (!AllowModify) {
207         TBB = I->getOperand(0).getMBB();
208         continue;
209       }
210 
211       // If the block has any instructions after a JMP, delete them.
212       while (std::next(I) != MBB.end())
213         std::next(I)->eraseFromParent();
214       Cond.clear();
215       FBB = nullptr;
216 
217       // Delete the JMP if it's equivalent to a fall-through.
218       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
219         TBB = nullptr;
220         I->eraseFromParent();
221         I = MBB.end();
222         continue;
223       }
224 
225       // TBB is used to indicate the unconditinal destination.
226       TBB = I->getOperand(0).getMBB();
227       continue;
228     }
229 
230     // Handle conditional branches.
231     assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
232     MSP430CC::CondCodes BranchCode =
233       static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
234     if (BranchCode == MSP430CC::COND_INVALID)
235       return true;  // Can't handle weird stuff.
236 
237     // Working from the bottom, handle the first conditional branch.
238     if (Cond.empty()) {
239       FBB = TBB;
240       TBB = I->getOperand(0).getMBB();
241       Cond.push_back(MachineOperand::CreateImm(BranchCode));
242       continue;
243     }
244 
245     // Handle subsequent conditional branches. Only handle the case where all
246     // conditional branches branch to the same destination.
247     assert(Cond.size() == 1);
248     assert(TBB);
249 
250     // Only handle the case where all conditional branches branch to
251     // the same destination.
252     if (TBB != I->getOperand(0).getMBB())
253       return true;
254 
255     MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
256     // If the conditions are the same, we can leave them alone.
257     if (OldBranchCode == BranchCode)
258       continue;
259 
260     return true;
261   }
262 
263   return false;
264 }
265 
266 unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB,
267                                        MachineBasicBlock *TBB,
268                                        MachineBasicBlock *FBB,
269                                        ArrayRef<MachineOperand> Cond,
270                                        const DebugLoc &DL,
271                                        int *BytesAdded) const {
272   // Shouldn't be a fall through.
273   assert(TBB && "insertBranch must not be told to insert a fallthrough");
274   assert((Cond.size() == 1 || Cond.size() == 0) &&
275          "MSP430 branch conditions have one component!");
276   assert(!BytesAdded && "code size not handled");
277 
278   if (Cond.empty()) {
279     // Unconditional branch?
280     assert(!FBB && "Unconditional branch with multiple successors!");
281     BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
282     return 1;
283   }
284 
285   // Conditional branch.
286   unsigned Count = 0;
287   BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
288   ++Count;
289 
290   if (FBB) {
291     // Two-way Conditional branch. Insert the second branch.
292     BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
293     ++Count;
294   }
295   return Count;
296 }
297 
298 /// GetInstSize - Return the number of bytes of code the specified
299 /// instruction may be.  This returns the maximum number of bytes.
300 ///
301 unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
302   const MCInstrDesc &Desc = MI.getDesc();
303 
304   switch (Desc.TSFlags & MSP430II::SizeMask) {
305   default:
306     switch (Desc.getOpcode()) {
307     default: llvm_unreachable("Unknown instruction size!");
308     case TargetOpcode::CFI_INSTRUCTION:
309     case TargetOpcode::EH_LABEL:
310     case TargetOpcode::IMPLICIT_DEF:
311     case TargetOpcode::KILL:
312     case TargetOpcode::DBG_VALUE:
313       return 0;
314     case TargetOpcode::INLINEASM: {
315       const MachineFunction *MF = MI.getParent()->getParent();
316       const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
317       return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
318                                     *MF->getTarget().getMCAsmInfo());
319     }
320     }
321   case MSP430II::SizeSpecial:
322     switch (MI.getOpcode()) {
323     default: llvm_unreachable("Unknown instruction size!");
324     case MSP430::SAR8r1c:
325     case MSP430::SAR16r1c:
326       return 4;
327     }
328   case MSP430II::Size2Bytes:
329     return 2;
330   case MSP430II::Size4Bytes:
331     return 4;
332   case MSP430II::Size6Bytes:
333     return 6;
334   }
335 }
336