1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MSP430TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MSP430ISelLowering.h" 15 #include "MSP430.h" 16 #include "MSP430MachineFunctionInfo.h" 17 #include "MSP430Subtarget.h" 18 #include "MSP430TargetMachine.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGISel.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/DerivedTypes.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/GlobalAlias.h" 31 #include "llvm/IR/GlobalVariable.h" 32 #include "llvm/IR/Intrinsics.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/raw_ostream.h" 37 using namespace llvm; 38 39 #define DEBUG_TYPE "msp430-lower" 40 41 typedef enum { 42 NoHWMult, 43 HWMultIntr, 44 HWMultNoIntr 45 } HWMultUseMode; 46 47 static cl::opt<HWMultUseMode> 48 HWMultMode("msp430-hwmult-mode", cl::Hidden, 49 cl::desc("Hardware multiplier use mode"), 50 cl::init(HWMultNoIntr), 51 cl::values( 52 clEnumValN(NoHWMult, "no", 53 "Do not use hardware multiplier"), 54 clEnumValN(HWMultIntr, "interrupts", 55 "Assume hardware multiplier can be used inside interrupts"), 56 clEnumValN(HWMultNoIntr, "use", 57 "Assume hardware multiplier cannot be used inside interrupts"), 58 clEnumValEnd)); 59 60 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM, 61 const MSP430Subtarget &STI) 62 : TargetLowering(TM) { 63 64 // Set up the register classes. 65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); 66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); 67 68 // Compute derived properties from the register classes 69 computeRegisterProperties(STI.getRegisterInfo()); 70 71 // Provide all sorts of operation actions 72 73 // Division is expensive 74 setIntDivIsCheap(false); 75 76 setStackPointerRegisterToSaveRestore(MSP430::SP); 77 setBooleanContents(ZeroOrOneBooleanContent); 78 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 79 80 // We have post-incremented loads / stores. 81 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 82 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 83 84 for (MVT VT : MVT::integer_valuetypes()) { 85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 90 } 91 92 // We don't have any truncstores 93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 94 95 setOperationAction(ISD::SRA, MVT::i8, Custom); 96 setOperationAction(ISD::SHL, MVT::i8, Custom); 97 setOperationAction(ISD::SRL, MVT::i8, Custom); 98 setOperationAction(ISD::SRA, MVT::i16, Custom); 99 setOperationAction(ISD::SHL, MVT::i16, Custom); 100 setOperationAction(ISD::SRL, MVT::i16, Custom); 101 setOperationAction(ISD::ROTL, MVT::i8, Expand); 102 setOperationAction(ISD::ROTR, MVT::i8, Expand); 103 setOperationAction(ISD::ROTL, MVT::i16, Expand); 104 setOperationAction(ISD::ROTR, MVT::i16, Expand); 105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 106 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); 107 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 108 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 109 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 110 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 111 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 112 setOperationAction(ISD::SETCC, MVT::i8, Custom); 113 setOperationAction(ISD::SETCC, MVT::i16, Custom); 114 setOperationAction(ISD::SELECT, MVT::i8, Expand); 115 setOperationAction(ISD::SELECT, MVT::i16, Expand); 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 118 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); 119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 120 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 121 122 setOperationAction(ISD::CTTZ, MVT::i8, Expand); 123 setOperationAction(ISD::CTTZ, MVT::i16, Expand); 124 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand); 125 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand); 126 setOperationAction(ISD::CTLZ, MVT::i8, Expand); 127 setOperationAction(ISD::CTLZ, MVT::i16, Expand); 128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand); 129 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand); 130 setOperationAction(ISD::CTPOP, MVT::i8, Expand); 131 setOperationAction(ISD::CTPOP, MVT::i16, Expand); 132 133 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); 134 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 135 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); 136 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 137 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); 138 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 139 140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 141 142 // FIXME: Implement efficiently multiplication by a constant 143 setOperationAction(ISD::MUL, MVT::i8, Expand); 144 setOperationAction(ISD::MULHS, MVT::i8, Expand); 145 setOperationAction(ISD::MULHU, MVT::i8, Expand); 146 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); 147 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); 148 setOperationAction(ISD::MUL, MVT::i16, Expand); 149 setOperationAction(ISD::MULHS, MVT::i16, Expand); 150 setOperationAction(ISD::MULHU, MVT::i16, Expand); 151 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 152 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 153 154 setOperationAction(ISD::UDIV, MVT::i8, Expand); 155 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); 156 setOperationAction(ISD::UREM, MVT::i8, Expand); 157 setOperationAction(ISD::SDIV, MVT::i8, Expand); 158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); 159 setOperationAction(ISD::SREM, MVT::i8, Expand); 160 setOperationAction(ISD::UDIV, MVT::i16, Expand); 161 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); 162 setOperationAction(ISD::UREM, MVT::i16, Expand); 163 setOperationAction(ISD::SDIV, MVT::i16, Expand); 164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); 165 setOperationAction(ISD::SREM, MVT::i16, Expand); 166 167 // varargs support 168 setOperationAction(ISD::VASTART, MVT::Other, Custom); 169 setOperationAction(ISD::VAARG, MVT::Other, Expand); 170 setOperationAction(ISD::VAEND, MVT::Other, Expand); 171 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 172 setOperationAction(ISD::JumpTable, MVT::i16, Custom); 173 174 // Libcalls names. 175 if (HWMultMode == HWMultIntr) { 176 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw"); 177 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw"); 178 } else if (HWMultMode == HWMultNoIntr) { 179 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint"); 180 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint"); 181 } 182 183 setMinFunctionAlignment(1); 184 setPrefFunctionAlignment(2); 185 } 186 187 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, 188 SelectionDAG &DAG) const { 189 switch (Op.getOpcode()) { 190 case ISD::SHL: // FALLTHROUGH 191 case ISD::SRL: 192 case ISD::SRA: return LowerShifts(Op, DAG); 193 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 194 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 195 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 196 case ISD::SETCC: return LowerSETCC(Op, DAG); 197 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 199 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 200 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 201 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 202 case ISD::VASTART: return LowerVASTART(Op, DAG); 203 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 204 default: 205 llvm_unreachable("unimplemented operand"); 206 } 207 } 208 209 //===----------------------------------------------------------------------===// 210 // MSP430 Inline Assembly Support 211 //===----------------------------------------------------------------------===// 212 213 /// getConstraintType - Given a constraint letter, return the type of 214 /// constraint it is for this target. 215 TargetLowering::ConstraintType 216 MSP430TargetLowering::getConstraintType(StringRef Constraint) const { 217 if (Constraint.size() == 1) { 218 switch (Constraint[0]) { 219 case 'r': 220 return C_RegisterClass; 221 default: 222 break; 223 } 224 } 225 return TargetLowering::getConstraintType(Constraint); 226 } 227 228 std::pair<unsigned, const TargetRegisterClass *> 229 MSP430TargetLowering::getRegForInlineAsmConstraint( 230 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { 231 if (Constraint.size() == 1) { 232 // GCC Constraint Letters 233 switch (Constraint[0]) { 234 default: break; 235 case 'r': // GENERAL_REGS 236 if (VT == MVT::i8) 237 return std::make_pair(0U, &MSP430::GR8RegClass); 238 239 return std::make_pair(0U, &MSP430::GR16RegClass); 240 } 241 } 242 243 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 244 } 245 246 //===----------------------------------------------------------------------===// 247 // Calling Convention Implementation 248 //===----------------------------------------------------------------------===// 249 250 #include "MSP430GenCallingConv.inc" 251 252 /// For each argument in a function store the number of pieces it is composed 253 /// of. 254 template<typename ArgT> 255 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args, 256 SmallVectorImpl<unsigned> &Out) { 257 unsigned CurrentArgIndex = ~0U; 258 for (unsigned i = 0, e = Args.size(); i != e; i++) { 259 if (CurrentArgIndex == Args[i].OrigArgIndex) { 260 Out.back()++; 261 } else { 262 Out.push_back(1); 263 CurrentArgIndex++; 264 } 265 } 266 } 267 268 static void AnalyzeVarArgs(CCState &State, 269 const SmallVectorImpl<ISD::OutputArg> &Outs) { 270 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); 271 } 272 273 static void AnalyzeVarArgs(CCState &State, 274 const SmallVectorImpl<ISD::InputArg> &Ins) { 275 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack); 276 } 277 278 /// Analyze incoming and outgoing function arguments. We need custom C++ code 279 /// to handle special constraints in the ABI like reversing the order of the 280 /// pieces of splitted arguments. In addition, all pieces of a certain argument 281 /// have to be passed either using registers or the stack but never mixing both. 282 template<typename ArgT> 283 static void AnalyzeArguments(CCState &State, 284 SmallVectorImpl<CCValAssign> &ArgLocs, 285 const SmallVectorImpl<ArgT> &Args) { 286 static const MCPhysReg RegList[] = { 287 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12 288 }; 289 static const unsigned NbRegs = array_lengthof(RegList); 290 291 if (State.isVarArg()) { 292 AnalyzeVarArgs(State, Args); 293 return; 294 } 295 296 SmallVector<unsigned, 4> ArgsParts; 297 ParseFunctionArgs(Args, ArgsParts); 298 299 unsigned RegsLeft = NbRegs; 300 bool UseStack = false; 301 unsigned ValNo = 0; 302 303 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) { 304 MVT ArgVT = Args[ValNo].VT; 305 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags; 306 MVT LocVT = ArgVT; 307 CCValAssign::LocInfo LocInfo = CCValAssign::Full; 308 309 // Promote i8 to i16 310 if (LocVT == MVT::i8) { 311 LocVT = MVT::i16; 312 if (ArgFlags.isSExt()) 313 LocInfo = CCValAssign::SExt; 314 else if (ArgFlags.isZExt()) 315 LocInfo = CCValAssign::ZExt; 316 else 317 LocInfo = CCValAssign::AExt; 318 } 319 320 // Handle byval arguments 321 if (ArgFlags.isByVal()) { 322 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags); 323 continue; 324 } 325 326 unsigned Parts = ArgsParts[i]; 327 328 if (!UseStack && Parts <= RegsLeft) { 329 unsigned FirstVal = ValNo; 330 for (unsigned j = 0; j < Parts; j++) { 331 unsigned Reg = State.AllocateReg(RegList); 332 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); 333 RegsLeft--; 334 } 335 336 // Reverse the order of the pieces to agree with the "big endian" format 337 // required in the calling convention ABI. 338 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal; 339 std::reverse(B, B + Parts); 340 } else { 341 UseStack = true; 342 for (unsigned j = 0; j < Parts; j++) 343 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); 344 } 345 } 346 } 347 348 static void AnalyzeRetResult(CCState &State, 349 const SmallVectorImpl<ISD::InputArg> &Ins) { 350 State.AnalyzeCallResult(Ins, RetCC_MSP430); 351 } 352 353 static void AnalyzeRetResult(CCState &State, 354 const SmallVectorImpl<ISD::OutputArg> &Outs) { 355 State.AnalyzeReturn(Outs, RetCC_MSP430); 356 } 357 358 template<typename ArgT> 359 static void AnalyzeReturnValues(CCState &State, 360 SmallVectorImpl<CCValAssign> &RVLocs, 361 const SmallVectorImpl<ArgT> &Args) { 362 AnalyzeRetResult(State, Args); 363 364 // Reverse splitted return values to get the "big endian" format required 365 // to agree with the calling convention ABI. 366 std::reverse(RVLocs.begin(), RVLocs.end()); 367 } 368 369 SDValue 370 MSP430TargetLowering::LowerFormalArguments(SDValue Chain, 371 CallingConv::ID CallConv, 372 bool isVarArg, 373 const SmallVectorImpl<ISD::InputArg> 374 &Ins, 375 SDLoc dl, 376 SelectionDAG &DAG, 377 SmallVectorImpl<SDValue> &InVals) 378 const { 379 380 switch (CallConv) { 381 default: 382 llvm_unreachable("Unsupported calling convention"); 383 case CallingConv::C: 384 case CallingConv::Fast: 385 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 386 case CallingConv::MSP430_INTR: 387 if (Ins.empty()) 388 return Chain; 389 report_fatal_error("ISRs cannot have arguments"); 390 } 391 } 392 393 SDValue 394 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 395 SmallVectorImpl<SDValue> &InVals) const { 396 SelectionDAG &DAG = CLI.DAG; 397 SDLoc &dl = CLI.DL; 398 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 399 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 400 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 401 SDValue Chain = CLI.Chain; 402 SDValue Callee = CLI.Callee; 403 bool &isTailCall = CLI.IsTailCall; 404 CallingConv::ID CallConv = CLI.CallConv; 405 bool isVarArg = CLI.IsVarArg; 406 407 // MSP430 target does not yet support tail call optimization. 408 isTailCall = false; 409 410 switch (CallConv) { 411 default: 412 llvm_unreachable("Unsupported calling convention"); 413 case CallingConv::Fast: 414 case CallingConv::C: 415 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 416 Outs, OutVals, Ins, dl, DAG, InVals); 417 case CallingConv::MSP430_INTR: 418 report_fatal_error("ISRs cannot be called directly"); 419 } 420 } 421 422 /// LowerCCCArguments - transform physical registers into virtual registers and 423 /// generate load operations for arguments places on the stack. 424 // FIXME: struct return stuff 425 SDValue 426 MSP430TargetLowering::LowerCCCArguments(SDValue Chain, 427 CallingConv::ID CallConv, 428 bool isVarArg, 429 const SmallVectorImpl<ISD::InputArg> 430 &Ins, 431 SDLoc dl, 432 SelectionDAG &DAG, 433 SmallVectorImpl<SDValue> &InVals) 434 const { 435 MachineFunction &MF = DAG.getMachineFunction(); 436 MachineFrameInfo *MFI = MF.getFrameInfo(); 437 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 438 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 439 440 // Assign locations to all of the incoming arguments. 441 SmallVector<CCValAssign, 16> ArgLocs; 442 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 443 *DAG.getContext()); 444 AnalyzeArguments(CCInfo, ArgLocs, Ins); 445 446 // Create frame index for the start of the first vararg value 447 if (isVarArg) { 448 unsigned Offset = CCInfo.getNextStackOffset(); 449 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true)); 450 } 451 452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 453 CCValAssign &VA = ArgLocs[i]; 454 if (VA.isRegLoc()) { 455 // Arguments passed in registers 456 EVT RegVT = VA.getLocVT(); 457 switch (RegVT.getSimpleVT().SimpleTy) { 458 default: 459 { 460 #ifndef NDEBUG 461 errs() << "LowerFormalArguments Unhandled argument type: " 462 << RegVT.getSimpleVT().SimpleTy << "\n"; 463 #endif 464 llvm_unreachable(nullptr); 465 } 466 case MVT::i16: 467 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); 468 RegInfo.addLiveIn(VA.getLocReg(), VReg); 469 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 470 471 // If this is an 8-bit value, it is really passed promoted to 16 472 // bits. Insert an assert[sz]ext to capture this, then truncate to the 473 // right size. 474 if (VA.getLocInfo() == CCValAssign::SExt) 475 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 476 DAG.getValueType(VA.getValVT())); 477 else if (VA.getLocInfo() == CCValAssign::ZExt) 478 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 479 DAG.getValueType(VA.getValVT())); 480 481 if (VA.getLocInfo() != CCValAssign::Full) 482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 483 484 InVals.push_back(ArgValue); 485 } 486 } else { 487 // Sanity check 488 assert(VA.isMemLoc()); 489 490 SDValue InVal; 491 ISD::ArgFlagsTy Flags = Ins[i].Flags; 492 493 if (Flags.isByVal()) { 494 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 495 VA.getLocMemOffset(), true); 496 InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 497 } else { 498 // Load the argument to a virtual register 499 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 500 if (ObjSize > 2) { 501 errs() << "LowerFormalArguments Unhandled argument type: " 502 << EVT(VA.getLocVT()).getEVTString() 503 << "\n"; 504 } 505 // Create the frame index object for this incoming parameter... 506 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); 507 508 // Create the SelectionDAG nodes corresponding to a load 509 //from this parameter 510 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); 511 InVal = DAG.getLoad( 512 VA.getLocVT(), dl, Chain, FIN, 513 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), 514 false, false, false, 0); 515 } 516 517 InVals.push_back(InVal); 518 } 519 } 520 521 return Chain; 522 } 523 524 SDValue 525 MSP430TargetLowering::LowerReturn(SDValue Chain, 526 CallingConv::ID CallConv, bool isVarArg, 527 const SmallVectorImpl<ISD::OutputArg> &Outs, 528 const SmallVectorImpl<SDValue> &OutVals, 529 SDLoc dl, SelectionDAG &DAG) const { 530 531 // CCValAssign - represent the assignment of the return value to a location 532 SmallVector<CCValAssign, 16> RVLocs; 533 534 // ISRs cannot return any value. 535 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 536 report_fatal_error("ISRs cannot return any value"); 537 538 // CCState - Info about the registers and stack slot. 539 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 540 *DAG.getContext()); 541 542 // Analize return values. 543 AnalyzeReturnValues(CCInfo, RVLocs, Outs); 544 545 SDValue Flag; 546 SmallVector<SDValue, 4> RetOps(1, Chain); 547 548 // Copy the result values into the output registers. 549 for (unsigned i = 0; i != RVLocs.size(); ++i) { 550 CCValAssign &VA = RVLocs[i]; 551 assert(VA.isRegLoc() && "Can only return in registers!"); 552 553 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 554 OutVals[i], Flag); 555 556 // Guarantee that all emitted copies are stuck together, 557 // avoiding something bad. 558 Flag = Chain.getValue(1); 559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 560 } 561 562 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? 563 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG); 564 565 RetOps[0] = Chain; // Update chain. 566 567 // Add the flag if we have it. 568 if (Flag.getNode()) 569 RetOps.push_back(Flag); 570 571 return DAG.getNode(Opc, dl, MVT::Other, RetOps); 572 } 573 574 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 575 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 576 // TODO: sret. 577 SDValue 578 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 579 CallingConv::ID CallConv, bool isVarArg, 580 bool isTailCall, 581 const SmallVectorImpl<ISD::OutputArg> 582 &Outs, 583 const SmallVectorImpl<SDValue> &OutVals, 584 const SmallVectorImpl<ISD::InputArg> &Ins, 585 SDLoc dl, SelectionDAG &DAG, 586 SmallVectorImpl<SDValue> &InVals) const { 587 // Analyze operands of the call, assigning locations to each operand. 588 SmallVector<CCValAssign, 16> ArgLocs; 589 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 590 *DAG.getContext()); 591 AnalyzeArguments(CCInfo, ArgLocs, Outs); 592 593 // Get a count of how many bytes are to be pushed on the stack. 594 unsigned NumBytes = CCInfo.getNextStackOffset(); 595 auto PtrVT = getPointerTy(DAG.getDataLayout()); 596 597 Chain = DAG.getCALLSEQ_START(Chain, 598 DAG.getConstant(NumBytes, dl, PtrVT, true), dl); 599 600 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 601 SmallVector<SDValue, 12> MemOpChains; 602 SDValue StackPtr; 603 604 // Walk the register/memloc assignments, inserting copies/loads. 605 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 606 CCValAssign &VA = ArgLocs[i]; 607 608 SDValue Arg = OutVals[i]; 609 610 // Promote the value if needed. 611 switch (VA.getLocInfo()) { 612 default: llvm_unreachable("Unknown loc info!"); 613 case CCValAssign::Full: break; 614 case CCValAssign::SExt: 615 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 616 break; 617 case CCValAssign::ZExt: 618 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 619 break; 620 case CCValAssign::AExt: 621 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 622 break; 623 } 624 625 // Arguments that can be passed on register must be kept at RegsToPass 626 // vector 627 if (VA.isRegLoc()) { 628 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 629 } else { 630 assert(VA.isMemLoc()); 631 632 if (!StackPtr.getNode()) 633 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT); 634 635 SDValue PtrOff = 636 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 637 DAG.getIntPtrConstant(VA.getLocMemOffset(), dl)); 638 639 SDValue MemOp; 640 ISD::ArgFlagsTy Flags = Outs[i].Flags; 641 642 if (Flags.isByVal()) { 643 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16); 644 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, 645 Flags.getByValAlign(), 646 /*isVolatile*/false, 647 /*AlwaysInline=*/true, 648 /*isTailCall=*/false, 649 MachinePointerInfo(), 650 MachinePointerInfo()); 651 } else { 652 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), 653 false, false, 0); 654 } 655 656 MemOpChains.push_back(MemOp); 657 } 658 } 659 660 // Transform all store nodes into one single node because all store nodes are 661 // independent of each other. 662 if (!MemOpChains.empty()) 663 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 664 665 // Build a sequence of copy-to-reg nodes chained together with token chain and 666 // flag operands which copy the outgoing args into registers. The InFlag in 667 // necessary since all emitted instructions must be stuck together. 668 SDValue InFlag; 669 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 670 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 671 RegsToPass[i].second, InFlag); 672 InFlag = Chain.getValue(1); 673 } 674 675 // If the callee is a GlobalAddress node (quite common, every direct call is) 676 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 677 // Likewise ExternalSymbol -> TargetExternalSymbol. 678 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 679 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16); 680 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 681 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); 682 683 // Returns a chain & a flag for retval copy to use. 684 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 685 SmallVector<SDValue, 8> Ops; 686 Ops.push_back(Chain); 687 Ops.push_back(Callee); 688 689 // Add argument registers to the end of the list so that they are 690 // known live into the call. 691 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 692 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 693 RegsToPass[i].second.getValueType())); 694 695 if (InFlag.getNode()) 696 Ops.push_back(InFlag); 697 698 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops); 699 InFlag = Chain.getValue(1); 700 701 // Create the CALLSEQ_END node. 702 Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true), 703 DAG.getConstant(0, dl, PtrVT, true), InFlag, dl); 704 InFlag = Chain.getValue(1); 705 706 // Handle result values, copying them out of physregs into vregs that we 707 // return. 708 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 709 DAG, InVals); 710 } 711 712 /// LowerCallResult - Lower the result values of a call into the 713 /// appropriate copies out of appropriate physical registers. 714 /// 715 SDValue 716 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 717 CallingConv::ID CallConv, bool isVarArg, 718 const SmallVectorImpl<ISD::InputArg> &Ins, 719 SDLoc dl, SelectionDAG &DAG, 720 SmallVectorImpl<SDValue> &InVals) const { 721 722 // Assign locations to each value returned by this call. 723 SmallVector<CCValAssign, 16> RVLocs; 724 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 725 *DAG.getContext()); 726 727 AnalyzeReturnValues(CCInfo, RVLocs, Ins); 728 729 // Copy all of the result registers out of their specified physreg. 730 for (unsigned i = 0; i != RVLocs.size(); ++i) { 731 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 732 RVLocs[i].getValVT(), InFlag).getValue(1); 733 InFlag = Chain.getValue(2); 734 InVals.push_back(Chain.getValue(0)); 735 } 736 737 return Chain; 738 } 739 740 SDValue MSP430TargetLowering::LowerShifts(SDValue Op, 741 SelectionDAG &DAG) const { 742 unsigned Opc = Op.getOpcode(); 743 SDNode* N = Op.getNode(); 744 EVT VT = Op.getValueType(); 745 SDLoc dl(N); 746 747 // Expand non-constant shifts to loops: 748 if (!isa<ConstantSDNode>(N->getOperand(1))) 749 switch (Opc) { 750 default: llvm_unreachable("Invalid shift opcode!"); 751 case ISD::SHL: 752 return DAG.getNode(MSP430ISD::SHL, dl, 753 VT, N->getOperand(0), N->getOperand(1)); 754 case ISD::SRA: 755 return DAG.getNode(MSP430ISD::SRA, dl, 756 VT, N->getOperand(0), N->getOperand(1)); 757 case ISD::SRL: 758 return DAG.getNode(MSP430ISD::SRL, dl, 759 VT, N->getOperand(0), N->getOperand(1)); 760 } 761 762 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 763 764 // Expand the stuff into sequence of shifts. 765 // FIXME: for some shift amounts this might be done better! 766 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N 767 SDValue Victim = N->getOperand(0); 768 769 if (Opc == ISD::SRL && ShiftAmount) { 770 // Emit a special goodness here: 771 // srl A, 1 => clrc; rrc A 772 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim); 773 ShiftAmount -= 1; 774 } 775 776 while (ShiftAmount--) 777 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 778 dl, VT, Victim); 779 780 return Victim; 781 } 782 783 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, 784 SelectionDAG &DAG) const { 785 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 786 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 787 auto PtrVT = getPointerTy(DAG.getDataLayout()); 788 789 // Create the TargetGlobalAddress node, folding in the constant offset. 790 SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset); 791 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result); 792 } 793 794 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, 795 SelectionDAG &DAG) const { 796 SDLoc dl(Op); 797 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 798 auto PtrVT = getPointerTy(DAG.getDataLayout()); 799 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT); 800 801 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result); 802 } 803 804 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op, 805 SelectionDAG &DAG) const { 806 SDLoc dl(Op); 807 auto PtrVT = getPointerTy(DAG.getDataLayout()); 808 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 809 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT); 810 811 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result); 812 } 813 814 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, 815 ISD::CondCode CC, 816 SDLoc dl, SelectionDAG &DAG) { 817 // FIXME: Handle bittests someday 818 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); 819 820 // FIXME: Handle jump negative someday 821 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID; 822 switch (CC) { 823 default: llvm_unreachable("Invalid integer condition!"); 824 case ISD::SETEQ: 825 TCC = MSP430CC::COND_E; // aka COND_Z 826 // Minor optimization: if LHS is a constant, swap operands, then the 827 // constant can be folded into comparison. 828 if (LHS.getOpcode() == ISD::Constant) 829 std::swap(LHS, RHS); 830 break; 831 case ISD::SETNE: 832 TCC = MSP430CC::COND_NE; // aka COND_NZ 833 // Minor optimization: if LHS is a constant, swap operands, then the 834 // constant can be folded into comparison. 835 if (LHS.getOpcode() == ISD::Constant) 836 std::swap(LHS, RHS); 837 break; 838 case ISD::SETULE: 839 std::swap(LHS, RHS); // FALLTHROUGH 840 case ISD::SETUGE: 841 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to 842 // fold constant into instruction. 843 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 844 LHS = RHS; 845 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 846 TCC = MSP430CC::COND_LO; 847 break; 848 } 849 TCC = MSP430CC::COND_HS; // aka COND_C 850 break; 851 case ISD::SETUGT: 852 std::swap(LHS, RHS); // FALLTHROUGH 853 case ISD::SETULT: 854 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to 855 // fold constant into instruction. 856 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 857 LHS = RHS; 858 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 859 TCC = MSP430CC::COND_HS; 860 break; 861 } 862 TCC = MSP430CC::COND_LO; // aka COND_NC 863 break; 864 case ISD::SETLE: 865 std::swap(LHS, RHS); // FALLTHROUGH 866 case ISD::SETGE: 867 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to 868 // fold constant into instruction. 869 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 870 LHS = RHS; 871 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 872 TCC = MSP430CC::COND_L; 873 break; 874 } 875 TCC = MSP430CC::COND_GE; 876 break; 877 case ISD::SETGT: 878 std::swap(LHS, RHS); // FALLTHROUGH 879 case ISD::SETLT: 880 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 881 // fold constant into instruction. 882 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 883 LHS = RHS; 884 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 885 TCC = MSP430CC::COND_GE; 886 break; 887 } 888 TCC = MSP430CC::COND_L; 889 break; 890 } 891 892 TargetCC = DAG.getConstant(TCC, dl, MVT::i8); 893 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS); 894 } 895 896 897 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 898 SDValue Chain = Op.getOperand(0); 899 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 900 SDValue LHS = Op.getOperand(2); 901 SDValue RHS = Op.getOperand(3); 902 SDValue Dest = Op.getOperand(4); 903 SDLoc dl (Op); 904 905 SDValue TargetCC; 906 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 907 908 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 909 Chain, Dest, TargetCC, Flag); 910 } 911 912 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 913 SDValue LHS = Op.getOperand(0); 914 SDValue RHS = Op.getOperand(1); 915 SDLoc dl (Op); 916 917 // If we are doing an AND and testing against zero, then the CMP 918 // will not be generated. The AND (or BIT) will generate the condition codes, 919 // but they are different from CMP. 920 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so 921 // lowering & isel wouldn't diverge. 922 bool andCC = false; 923 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 924 if (RHSC->isNullValue() && LHS.hasOneUse() && 925 (LHS.getOpcode() == ISD::AND || 926 (LHS.getOpcode() == ISD::TRUNCATE && 927 LHS.getOperand(0).getOpcode() == ISD::AND))) { 928 andCC = true; 929 } 930 } 931 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 932 SDValue TargetCC; 933 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 934 935 // Get the condition codes directly from the status register, if its easy. 936 // Otherwise a branch will be generated. Note that the AND and BIT 937 // instructions generate different flags than CMP, the carry bit can be used 938 // for NE/EQ. 939 bool Invert = false; 940 bool Shift = false; 941 bool Convert = true; 942 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) { 943 default: 944 Convert = false; 945 break; 946 case MSP430CC::COND_HS: 947 // Res = SR & 1, no processing is required 948 break; 949 case MSP430CC::COND_LO: 950 // Res = ~(SR & 1) 951 Invert = true; 952 break; 953 case MSP430CC::COND_NE: 954 if (andCC) { 955 // C = ~Z, thus Res = SR & 1, no processing is required 956 } else { 957 // Res = ~((SR >> 1) & 1) 958 Shift = true; 959 Invert = true; 960 } 961 break; 962 case MSP430CC::COND_E: 963 Shift = true; 964 // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however, 965 // Res = (SR >> 1) & 1 is 1 word shorter. 966 break; 967 } 968 EVT VT = Op.getValueType(); 969 SDValue One = DAG.getConstant(1, dl, VT); 970 if (Convert) { 971 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, 972 MVT::i16, Flag); 973 if (Shift) 974 // FIXME: somewhere this is turned into a SRL, lower it MSP specific? 975 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); 976 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); 977 if (Invert) 978 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); 979 return SR; 980 } else { 981 SDValue Zero = DAG.getConstant(0, dl, VT); 982 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 983 SDValue Ops[] = {One, Zero, TargetCC, Flag}; 984 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 985 } 986 } 987 988 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, 989 SelectionDAG &DAG) const { 990 SDValue LHS = Op.getOperand(0); 991 SDValue RHS = Op.getOperand(1); 992 SDValue TrueV = Op.getOperand(2); 993 SDValue FalseV = Op.getOperand(3); 994 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 995 SDLoc dl (Op); 996 997 SDValue TargetCC; 998 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 999 1000 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 1001 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag}; 1002 1003 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1004 } 1005 1006 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, 1007 SelectionDAG &DAG) const { 1008 SDValue Val = Op.getOperand(0); 1009 EVT VT = Op.getValueType(); 1010 SDLoc dl(Op); 1011 1012 assert(VT == MVT::i16 && "Only support i16 for now!"); 1013 1014 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, 1015 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), 1016 DAG.getValueType(Val.getValueType())); 1017 } 1018 1019 SDValue 1020 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 1021 MachineFunction &MF = DAG.getMachineFunction(); 1022 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1023 int ReturnAddrIndex = FuncInfo->getRAIndex(); 1024 auto PtrVT = getPointerTy(MF.getDataLayout()); 1025 1026 if (ReturnAddrIndex == 0) { 1027 // Set up a frame object for the return address. 1028 uint64_t SlotSize = MF.getDataLayout().getPointerSize(); 1029 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 1030 true); 1031 FuncInfo->setRAIndex(ReturnAddrIndex); 1032 } 1033 1034 return DAG.getFrameIndex(ReturnAddrIndex, PtrVT); 1035 } 1036 1037 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, 1038 SelectionDAG &DAG) const { 1039 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1040 MFI->setReturnAddressIsTaken(true); 1041 1042 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 1043 return SDValue(); 1044 1045 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1046 SDLoc dl(Op); 1047 auto PtrVT = getPointerTy(DAG.getDataLayout()); 1048 1049 if (Depth > 0) { 1050 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 1051 SDValue Offset = 1052 DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16); 1053 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 1054 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset), 1055 MachinePointerInfo(), false, false, false, 0); 1056 } 1057 1058 // Just load the return address. 1059 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 1060 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI, 1061 MachinePointerInfo(), false, false, false, 0); 1062 } 1063 1064 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, 1065 SelectionDAG &DAG) const { 1066 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1067 MFI->setFrameAddressIsTaken(true); 1068 1069 EVT VT = Op.getValueType(); 1070 SDLoc dl(Op); // FIXME probably not meaningful 1071 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1072 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1073 MSP430::FP, VT); 1074 while (Depth--) 1075 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 1076 MachinePointerInfo(), 1077 false, false, false, 0); 1078 return FrameAddr; 1079 } 1080 1081 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op, 1082 SelectionDAG &DAG) const { 1083 MachineFunction &MF = DAG.getMachineFunction(); 1084 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1085 auto PtrVT = getPointerTy(DAG.getDataLayout()); 1086 1087 // Frame index of first vararg argument 1088 SDValue FrameIndex = 1089 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1090 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1091 1092 // Create a store of the frame index to the location operand 1093 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, 1094 Op.getOperand(1), MachinePointerInfo(SV), 1095 false, false, 0); 1096 } 1097 1098 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op, 1099 SelectionDAG &DAG) const { 1100 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1101 auto PtrVT = getPointerTy(DAG.getDataLayout()); 1102 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1103 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result); 1104 } 1105 1106 /// getPostIndexedAddressParts - returns true by value, base pointer and 1107 /// offset pointer and addressing mode by reference if this node can be 1108 /// combined with a load / store to form a post-indexed load / store. 1109 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1110 SDValue &Base, 1111 SDValue &Offset, 1112 ISD::MemIndexedMode &AM, 1113 SelectionDAG &DAG) const { 1114 1115 LoadSDNode *LD = cast<LoadSDNode>(N); 1116 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 1117 return false; 1118 1119 EVT VT = LD->getMemoryVT(); 1120 if (VT != MVT::i8 && VT != MVT::i16) 1121 return false; 1122 1123 if (Op->getOpcode() != ISD::ADD) 1124 return false; 1125 1126 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 1127 uint64_t RHSC = RHS->getZExtValue(); 1128 if ((VT == MVT::i16 && RHSC != 2) || 1129 (VT == MVT::i8 && RHSC != 1)) 1130 return false; 1131 1132 Base = Op->getOperand(0); 1133 Offset = DAG.getConstant(RHSC, SDLoc(N), VT); 1134 AM = ISD::POST_INC; 1135 return true; 1136 } 1137 1138 return false; 1139 } 1140 1141 1142 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { 1143 switch ((MSP430ISD::NodeType)Opcode) { 1144 case MSP430ISD::FIRST_NUMBER: break; 1145 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; 1146 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG"; 1147 case MSP430ISD::RRA: return "MSP430ISD::RRA"; 1148 case MSP430ISD::RLA: return "MSP430ISD::RLA"; 1149 case MSP430ISD::RRC: return "MSP430ISD::RRC"; 1150 case MSP430ISD::CALL: return "MSP430ISD::CALL"; 1151 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; 1152 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; 1153 case MSP430ISD::CMP: return "MSP430ISD::CMP"; 1154 case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; 1155 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; 1156 case MSP430ISD::SHL: return "MSP430ISD::SHL"; 1157 case MSP430ISD::SRA: return "MSP430ISD::SRA"; 1158 case MSP430ISD::SRL: return "MSP430ISD::SRL"; 1159 } 1160 return nullptr; 1161 } 1162 1163 bool MSP430TargetLowering::isTruncateFree(Type *Ty1, 1164 Type *Ty2) const { 1165 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 1166 return false; 1167 1168 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits()); 1169 } 1170 1171 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 1172 if (!VT1.isInteger() || !VT2.isInteger()) 1173 return false; 1174 1175 return (VT1.getSizeInBits() > VT2.getSizeInBits()); 1176 } 1177 1178 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 1179 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1180 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16); 1181 } 1182 1183 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 1184 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1185 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; 1186 } 1187 1188 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 1189 return isZExtFree(Val.getValueType(), VT2); 1190 } 1191 1192 //===----------------------------------------------------------------------===// 1193 // Other Lowering Code 1194 //===----------------------------------------------------------------------===// 1195 1196 MachineBasicBlock* 1197 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, 1198 MachineBasicBlock *BB) const { 1199 MachineFunction *F = BB->getParent(); 1200 MachineRegisterInfo &RI = F->getRegInfo(); 1201 DebugLoc dl = MI->getDebugLoc(); 1202 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); 1203 1204 unsigned Opc; 1205 const TargetRegisterClass * RC; 1206 switch (MI->getOpcode()) { 1207 default: llvm_unreachable("Invalid shift opcode!"); 1208 case MSP430::Shl8: 1209 Opc = MSP430::SHL8r1; 1210 RC = &MSP430::GR8RegClass; 1211 break; 1212 case MSP430::Shl16: 1213 Opc = MSP430::SHL16r1; 1214 RC = &MSP430::GR16RegClass; 1215 break; 1216 case MSP430::Sra8: 1217 Opc = MSP430::SAR8r1; 1218 RC = &MSP430::GR8RegClass; 1219 break; 1220 case MSP430::Sra16: 1221 Opc = MSP430::SAR16r1; 1222 RC = &MSP430::GR16RegClass; 1223 break; 1224 case MSP430::Srl8: 1225 Opc = MSP430::SAR8r1c; 1226 RC = &MSP430::GR8RegClass; 1227 break; 1228 case MSP430::Srl16: 1229 Opc = MSP430::SAR16r1c; 1230 RC = &MSP430::GR16RegClass; 1231 break; 1232 } 1233 1234 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1235 MachineFunction::iterator I = BB; 1236 ++I; 1237 1238 // Create loop block 1239 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1240 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1241 1242 F->insert(I, LoopBB); 1243 F->insert(I, RemBB); 1244 1245 // Update machine-CFG edges by transferring all successors of the current 1246 // block to the block containing instructions after shift. 1247 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 1248 BB->end()); 1249 RemBB->transferSuccessorsAndUpdatePHIs(BB); 1250 1251 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB 1252 BB->addSuccessor(LoopBB); 1253 BB->addSuccessor(RemBB); 1254 LoopBB->addSuccessor(RemBB); 1255 LoopBB->addSuccessor(LoopBB); 1256 1257 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass); 1258 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); 1259 unsigned ShiftReg = RI.createVirtualRegister(RC); 1260 unsigned ShiftReg2 = RI.createVirtualRegister(RC); 1261 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg(); 1262 unsigned SrcReg = MI->getOperand(1).getReg(); 1263 unsigned DstReg = MI->getOperand(0).getReg(); 1264 1265 // BB: 1266 // cmp 0, N 1267 // je RemBB 1268 BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) 1269 .addReg(ShiftAmtSrcReg).addImm(0); 1270 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1271 .addMBB(RemBB) 1272 .addImm(MSP430CC::COND_E); 1273 1274 // LoopBB: 1275 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1276 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1277 // ShiftReg2 = shift ShiftReg 1278 // ShiftAmt2 = ShiftAmt - 1; 1279 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) 1280 .addReg(SrcReg).addMBB(BB) 1281 .addReg(ShiftReg2).addMBB(LoopBB); 1282 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) 1283 .addReg(ShiftAmtSrcReg).addMBB(BB) 1284 .addReg(ShiftAmtReg2).addMBB(LoopBB); 1285 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) 1286 .addReg(ShiftReg); 1287 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) 1288 .addReg(ShiftAmtReg).addImm(1); 1289 BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) 1290 .addMBB(LoopBB) 1291 .addImm(MSP430CC::COND_NE); 1292 1293 // RemBB: 1294 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1295 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) 1296 .addReg(SrcReg).addMBB(BB) 1297 .addReg(ShiftReg2).addMBB(LoopBB); 1298 1299 MI->eraseFromParent(); // The pseudo instruction is gone now. 1300 return RemBB; 1301 } 1302 1303 MachineBasicBlock* 1304 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1305 MachineBasicBlock *BB) const { 1306 unsigned Opc = MI->getOpcode(); 1307 1308 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || 1309 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || 1310 Opc == MSP430::Srl8 || Opc == MSP430::Srl16) 1311 return EmitShiftInstr(MI, BB); 1312 1313 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 1314 DebugLoc dl = MI->getDebugLoc(); 1315 1316 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && 1317 "Unexpected instr type to insert"); 1318 1319 // To "insert" a SELECT instruction, we actually have to insert the diamond 1320 // control-flow pattern. The incoming instruction knows the destination vreg 1321 // to set, the condition code register to branch on, the true/false values to 1322 // select between, and a branch opcode to use. 1323 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1324 MachineFunction::iterator I = BB; 1325 ++I; 1326 1327 // thisMBB: 1328 // ... 1329 // TrueVal = ... 1330 // cmpTY ccX, r1, r2 1331 // jCC copy1MBB 1332 // fallthrough --> copy0MBB 1333 MachineBasicBlock *thisMBB = BB; 1334 MachineFunction *F = BB->getParent(); 1335 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1336 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 1337 F->insert(I, copy0MBB); 1338 F->insert(I, copy1MBB); 1339 // Update machine-CFG edges by transferring all successors of the current 1340 // block to the new block which will contain the Phi node for the select. 1341 copy1MBB->splice(copy1MBB->begin(), BB, 1342 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1343 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 1344 // Next, add the true and fallthrough blocks as its successors. 1345 BB->addSuccessor(copy0MBB); 1346 BB->addSuccessor(copy1MBB); 1347 1348 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1349 .addMBB(copy1MBB) 1350 .addImm(MI->getOperand(3).getImm()); 1351 1352 // copy0MBB: 1353 // %FalseValue = ... 1354 // # fallthrough to copy1MBB 1355 BB = copy0MBB; 1356 1357 // Update machine-CFG edges 1358 BB->addSuccessor(copy1MBB); 1359 1360 // copy1MBB: 1361 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1362 // ... 1363 BB = copy1MBB; 1364 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), 1365 MI->getOperand(0).getReg()) 1366 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1367 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1368 1369 MI->eraseFromParent(); // The pseudo instruction is gone now. 1370 return BB; 1371 } 1372