1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MSP430TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MSP430ISelLowering.h" 15 #include "MSP430.h" 16 #include "MSP430MachineFunctionInfo.h" 17 #include "MSP430Subtarget.h" 18 #include "MSP430TargetMachine.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGISel.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/DerivedTypes.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/GlobalAlias.h" 31 #include "llvm/IR/GlobalVariable.h" 32 #include "llvm/IR/Intrinsics.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/raw_ostream.h" 37 using namespace llvm; 38 39 #define DEBUG_TYPE "msp430-lower" 40 41 typedef enum { 42 NoHWMult, 43 HWMultIntr, 44 HWMultNoIntr 45 } HWMultUseMode; 46 47 static cl::opt<HWMultUseMode> 48 HWMultMode("msp430-hwmult-mode", cl::Hidden, 49 cl::desc("Hardware multiplier use mode"), 50 cl::init(HWMultNoIntr), 51 cl::values( 52 clEnumValN(NoHWMult, "no", 53 "Do not use hardware multiplier"), 54 clEnumValN(HWMultIntr, "interrupts", 55 "Assume hardware multiplier can be used inside interrupts"), 56 clEnumValN(HWMultNoIntr, "use", 57 "Assume hardware multiplier cannot be used inside interrupts"), 58 clEnumValEnd)); 59 60 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM, 61 const MSP430Subtarget &STI) 62 : TargetLowering(TM) { 63 64 // Set up the register classes. 65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); 66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); 67 68 // Compute derived properties from the register classes 69 computeRegisterProperties(STI.getRegisterInfo()); 70 71 // Provide all sorts of operation actions 72 73 // Division is expensive 74 setIntDivIsCheap(false); 75 76 setStackPointerRegisterToSaveRestore(MSP430::SP); 77 setBooleanContents(ZeroOrOneBooleanContent); 78 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 79 80 // We have post-incremented loads / stores. 81 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 82 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 83 84 for (MVT VT : MVT::integer_valuetypes()) { 85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 90 } 91 92 // We don't have any truncstores 93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 94 95 setOperationAction(ISD::SRA, MVT::i8, Custom); 96 setOperationAction(ISD::SHL, MVT::i8, Custom); 97 setOperationAction(ISD::SRL, MVT::i8, Custom); 98 setOperationAction(ISD::SRA, MVT::i16, Custom); 99 setOperationAction(ISD::SHL, MVT::i16, Custom); 100 setOperationAction(ISD::SRL, MVT::i16, Custom); 101 setOperationAction(ISD::ROTL, MVT::i8, Expand); 102 setOperationAction(ISD::ROTR, MVT::i8, Expand); 103 setOperationAction(ISD::ROTL, MVT::i16, Expand); 104 setOperationAction(ISD::ROTR, MVT::i16, Expand); 105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 106 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); 107 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 108 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 109 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 110 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 111 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 112 setOperationAction(ISD::SETCC, MVT::i8, Custom); 113 setOperationAction(ISD::SETCC, MVT::i16, Custom); 114 setOperationAction(ISD::SELECT, MVT::i8, Expand); 115 setOperationAction(ISD::SELECT, MVT::i16, Expand); 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 118 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); 119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 120 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 121 122 setOperationAction(ISD::CTTZ, MVT::i8, Expand); 123 setOperationAction(ISD::CTTZ, MVT::i16, Expand); 124 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand); 125 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand); 126 setOperationAction(ISD::CTLZ, MVT::i8, Expand); 127 setOperationAction(ISD::CTLZ, MVT::i16, Expand); 128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand); 129 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand); 130 setOperationAction(ISD::CTPOP, MVT::i8, Expand); 131 setOperationAction(ISD::CTPOP, MVT::i16, Expand); 132 133 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); 134 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 135 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); 136 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 137 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); 138 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 139 140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 141 142 // FIXME: Implement efficiently multiplication by a constant 143 setOperationAction(ISD::MUL, MVT::i8, Expand); 144 setOperationAction(ISD::MULHS, MVT::i8, Expand); 145 setOperationAction(ISD::MULHU, MVT::i8, Expand); 146 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); 147 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); 148 setOperationAction(ISD::MUL, MVT::i16, Expand); 149 setOperationAction(ISD::MULHS, MVT::i16, Expand); 150 setOperationAction(ISD::MULHU, MVT::i16, Expand); 151 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 152 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 153 154 setOperationAction(ISD::UDIV, MVT::i8, Expand); 155 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); 156 setOperationAction(ISD::UREM, MVT::i8, Expand); 157 setOperationAction(ISD::SDIV, MVT::i8, Expand); 158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); 159 setOperationAction(ISD::SREM, MVT::i8, Expand); 160 setOperationAction(ISD::UDIV, MVT::i16, Expand); 161 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); 162 setOperationAction(ISD::UREM, MVT::i16, Expand); 163 setOperationAction(ISD::SDIV, MVT::i16, Expand); 164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); 165 setOperationAction(ISD::SREM, MVT::i16, Expand); 166 167 // varargs support 168 setOperationAction(ISD::VASTART, MVT::Other, Custom); 169 setOperationAction(ISD::VAARG, MVT::Other, Expand); 170 setOperationAction(ISD::VAEND, MVT::Other, Expand); 171 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 172 setOperationAction(ISD::JumpTable, MVT::i16, Custom); 173 174 // Libcalls names. 175 if (HWMultMode == HWMultIntr) { 176 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw"); 177 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw"); 178 } else if (HWMultMode == HWMultNoIntr) { 179 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint"); 180 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint"); 181 } 182 183 setMinFunctionAlignment(1); 184 setPrefFunctionAlignment(2); 185 } 186 187 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, 188 SelectionDAG &DAG) const { 189 switch (Op.getOpcode()) { 190 case ISD::SHL: // FALLTHROUGH 191 case ISD::SRL: 192 case ISD::SRA: return LowerShifts(Op, DAG); 193 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 194 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 195 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 196 case ISD::SETCC: return LowerSETCC(Op, DAG); 197 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 199 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 200 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 201 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 202 case ISD::VASTART: return LowerVASTART(Op, DAG); 203 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 204 default: 205 llvm_unreachable("unimplemented operand"); 206 } 207 } 208 209 //===----------------------------------------------------------------------===// 210 // MSP430 Inline Assembly Support 211 //===----------------------------------------------------------------------===// 212 213 /// getConstraintType - Given a constraint letter, return the type of 214 /// constraint it is for this target. 215 TargetLowering::ConstraintType 216 MSP430TargetLowering::getConstraintType(const std::string &Constraint) const { 217 if (Constraint.size() == 1) { 218 switch (Constraint[0]) { 219 case 'r': 220 return C_RegisterClass; 221 default: 222 break; 223 } 224 } 225 return TargetLowering::getConstraintType(Constraint); 226 } 227 228 std::pair<unsigned, const TargetRegisterClass *> 229 MSP430TargetLowering::getRegForInlineAsmConstraint( 230 const TargetRegisterInfo *TRI, const std::string &Constraint, 231 MVT VT) const { 232 if (Constraint.size() == 1) { 233 // GCC Constraint Letters 234 switch (Constraint[0]) { 235 default: break; 236 case 'r': // GENERAL_REGS 237 if (VT == MVT::i8) 238 return std::make_pair(0U, &MSP430::GR8RegClass); 239 240 return std::make_pair(0U, &MSP430::GR16RegClass); 241 } 242 } 243 244 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 245 } 246 247 //===----------------------------------------------------------------------===// 248 // Calling Convention Implementation 249 //===----------------------------------------------------------------------===// 250 251 #include "MSP430GenCallingConv.inc" 252 253 /// For each argument in a function store the number of pieces it is composed 254 /// of. 255 template<typename ArgT> 256 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args, 257 SmallVectorImpl<unsigned> &Out) { 258 unsigned CurrentArgIndex = ~0U; 259 for (unsigned i = 0, e = Args.size(); i != e; i++) { 260 if (CurrentArgIndex == Args[i].OrigArgIndex) { 261 Out.back()++; 262 } else { 263 Out.push_back(1); 264 CurrentArgIndex++; 265 } 266 } 267 } 268 269 static void AnalyzeVarArgs(CCState &State, 270 const SmallVectorImpl<ISD::OutputArg> &Outs) { 271 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); 272 } 273 274 static void AnalyzeVarArgs(CCState &State, 275 const SmallVectorImpl<ISD::InputArg> &Ins) { 276 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack); 277 } 278 279 /// Analyze incoming and outgoing function arguments. We need custom C++ code 280 /// to handle special constraints in the ABI like reversing the order of the 281 /// pieces of splitted arguments. In addition, all pieces of a certain argument 282 /// have to be passed either using registers or the stack but never mixing both. 283 template<typename ArgT> 284 static void AnalyzeArguments(CCState &State, 285 SmallVectorImpl<CCValAssign> &ArgLocs, 286 const SmallVectorImpl<ArgT> &Args) { 287 static const MCPhysReg RegList[] = { 288 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12 289 }; 290 static const unsigned NbRegs = array_lengthof(RegList); 291 292 if (State.isVarArg()) { 293 AnalyzeVarArgs(State, Args); 294 return; 295 } 296 297 SmallVector<unsigned, 4> ArgsParts; 298 ParseFunctionArgs(Args, ArgsParts); 299 300 unsigned RegsLeft = NbRegs; 301 bool UseStack = false; 302 unsigned ValNo = 0; 303 304 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) { 305 MVT ArgVT = Args[ValNo].VT; 306 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags; 307 MVT LocVT = ArgVT; 308 CCValAssign::LocInfo LocInfo = CCValAssign::Full; 309 310 // Promote i8 to i16 311 if (LocVT == MVT::i8) { 312 LocVT = MVT::i16; 313 if (ArgFlags.isSExt()) 314 LocInfo = CCValAssign::SExt; 315 else if (ArgFlags.isZExt()) 316 LocInfo = CCValAssign::ZExt; 317 else 318 LocInfo = CCValAssign::AExt; 319 } 320 321 // Handle byval arguments 322 if (ArgFlags.isByVal()) { 323 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags); 324 continue; 325 } 326 327 unsigned Parts = ArgsParts[i]; 328 329 if (!UseStack && Parts <= RegsLeft) { 330 unsigned FirstVal = ValNo; 331 for (unsigned j = 0; j < Parts; j++) { 332 unsigned Reg = State.AllocateReg(RegList); 333 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); 334 RegsLeft--; 335 } 336 337 // Reverse the order of the pieces to agree with the "big endian" format 338 // required in the calling convention ABI. 339 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal; 340 std::reverse(B, B + Parts); 341 } else { 342 UseStack = true; 343 for (unsigned j = 0; j < Parts; j++) 344 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); 345 } 346 } 347 } 348 349 static void AnalyzeRetResult(CCState &State, 350 const SmallVectorImpl<ISD::InputArg> &Ins) { 351 State.AnalyzeCallResult(Ins, RetCC_MSP430); 352 } 353 354 static void AnalyzeRetResult(CCState &State, 355 const SmallVectorImpl<ISD::OutputArg> &Outs) { 356 State.AnalyzeReturn(Outs, RetCC_MSP430); 357 } 358 359 template<typename ArgT> 360 static void AnalyzeReturnValues(CCState &State, 361 SmallVectorImpl<CCValAssign> &RVLocs, 362 const SmallVectorImpl<ArgT> &Args) { 363 AnalyzeRetResult(State, Args); 364 365 // Reverse splitted return values to get the "big endian" format required 366 // to agree with the calling convention ABI. 367 std::reverse(RVLocs.begin(), RVLocs.end()); 368 } 369 370 SDValue 371 MSP430TargetLowering::LowerFormalArguments(SDValue Chain, 372 CallingConv::ID CallConv, 373 bool isVarArg, 374 const SmallVectorImpl<ISD::InputArg> 375 &Ins, 376 SDLoc dl, 377 SelectionDAG &DAG, 378 SmallVectorImpl<SDValue> &InVals) 379 const { 380 381 switch (CallConv) { 382 default: 383 llvm_unreachable("Unsupported calling convention"); 384 case CallingConv::C: 385 case CallingConv::Fast: 386 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 387 case CallingConv::MSP430_INTR: 388 if (Ins.empty()) 389 return Chain; 390 report_fatal_error("ISRs cannot have arguments"); 391 } 392 } 393 394 SDValue 395 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 396 SmallVectorImpl<SDValue> &InVals) const { 397 SelectionDAG &DAG = CLI.DAG; 398 SDLoc &dl = CLI.DL; 399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 400 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 401 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 402 SDValue Chain = CLI.Chain; 403 SDValue Callee = CLI.Callee; 404 bool &isTailCall = CLI.IsTailCall; 405 CallingConv::ID CallConv = CLI.CallConv; 406 bool isVarArg = CLI.IsVarArg; 407 408 // MSP430 target does not yet support tail call optimization. 409 isTailCall = false; 410 411 switch (CallConv) { 412 default: 413 llvm_unreachable("Unsupported calling convention"); 414 case CallingConv::Fast: 415 case CallingConv::C: 416 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 417 Outs, OutVals, Ins, dl, DAG, InVals); 418 case CallingConv::MSP430_INTR: 419 report_fatal_error("ISRs cannot be called directly"); 420 } 421 } 422 423 /// LowerCCCArguments - transform physical registers into virtual registers and 424 /// generate load operations for arguments places on the stack. 425 // FIXME: struct return stuff 426 SDValue 427 MSP430TargetLowering::LowerCCCArguments(SDValue Chain, 428 CallingConv::ID CallConv, 429 bool isVarArg, 430 const SmallVectorImpl<ISD::InputArg> 431 &Ins, 432 SDLoc dl, 433 SelectionDAG &DAG, 434 SmallVectorImpl<SDValue> &InVals) 435 const { 436 MachineFunction &MF = DAG.getMachineFunction(); 437 MachineFrameInfo *MFI = MF.getFrameInfo(); 438 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 439 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 440 441 // Assign locations to all of the incoming arguments. 442 SmallVector<CCValAssign, 16> ArgLocs; 443 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 444 *DAG.getContext()); 445 AnalyzeArguments(CCInfo, ArgLocs, Ins); 446 447 // Create frame index for the start of the first vararg value 448 if (isVarArg) { 449 unsigned Offset = CCInfo.getNextStackOffset(); 450 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true)); 451 } 452 453 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 454 CCValAssign &VA = ArgLocs[i]; 455 if (VA.isRegLoc()) { 456 // Arguments passed in registers 457 EVT RegVT = VA.getLocVT(); 458 switch (RegVT.getSimpleVT().SimpleTy) { 459 default: 460 { 461 #ifndef NDEBUG 462 errs() << "LowerFormalArguments Unhandled argument type: " 463 << RegVT.getSimpleVT().SimpleTy << "\n"; 464 #endif 465 llvm_unreachable(nullptr); 466 } 467 case MVT::i16: 468 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); 469 RegInfo.addLiveIn(VA.getLocReg(), VReg); 470 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 471 472 // If this is an 8-bit value, it is really passed promoted to 16 473 // bits. Insert an assert[sz]ext to capture this, then truncate to the 474 // right size. 475 if (VA.getLocInfo() == CCValAssign::SExt) 476 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 477 DAG.getValueType(VA.getValVT())); 478 else if (VA.getLocInfo() == CCValAssign::ZExt) 479 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 480 DAG.getValueType(VA.getValVT())); 481 482 if (VA.getLocInfo() != CCValAssign::Full) 483 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 484 485 InVals.push_back(ArgValue); 486 } 487 } else { 488 // Sanity check 489 assert(VA.isMemLoc()); 490 491 SDValue InVal; 492 ISD::ArgFlagsTy Flags = Ins[i].Flags; 493 494 if (Flags.isByVal()) { 495 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 496 VA.getLocMemOffset(), true); 497 InVal = DAG.getFrameIndex(FI, getPointerTy()); 498 } else { 499 // Load the argument to a virtual register 500 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 501 if (ObjSize > 2) { 502 errs() << "LowerFormalArguments Unhandled argument type: " 503 << EVT(VA.getLocVT()).getEVTString() 504 << "\n"; 505 } 506 // Create the frame index object for this incoming parameter... 507 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); 508 509 // Create the SelectionDAG nodes corresponding to a load 510 //from this parameter 511 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); 512 InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 513 MachinePointerInfo::getFixedStack(FI), 514 false, false, false, 0); 515 } 516 517 InVals.push_back(InVal); 518 } 519 } 520 521 return Chain; 522 } 523 524 SDValue 525 MSP430TargetLowering::LowerReturn(SDValue Chain, 526 CallingConv::ID CallConv, bool isVarArg, 527 const SmallVectorImpl<ISD::OutputArg> &Outs, 528 const SmallVectorImpl<SDValue> &OutVals, 529 SDLoc dl, SelectionDAG &DAG) const { 530 531 // CCValAssign - represent the assignment of the return value to a location 532 SmallVector<CCValAssign, 16> RVLocs; 533 534 // ISRs cannot return any value. 535 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 536 report_fatal_error("ISRs cannot return any value"); 537 538 // CCState - Info about the registers and stack slot. 539 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 540 *DAG.getContext()); 541 542 // Analize return values. 543 AnalyzeReturnValues(CCInfo, RVLocs, Outs); 544 545 SDValue Flag; 546 SmallVector<SDValue, 4> RetOps(1, Chain); 547 548 // Copy the result values into the output registers. 549 for (unsigned i = 0; i != RVLocs.size(); ++i) { 550 CCValAssign &VA = RVLocs[i]; 551 assert(VA.isRegLoc() && "Can only return in registers!"); 552 553 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 554 OutVals[i], Flag); 555 556 // Guarantee that all emitted copies are stuck together, 557 // avoiding something bad. 558 Flag = Chain.getValue(1); 559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 560 } 561 562 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? 563 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG); 564 565 RetOps[0] = Chain; // Update chain. 566 567 // Add the flag if we have it. 568 if (Flag.getNode()) 569 RetOps.push_back(Flag); 570 571 return DAG.getNode(Opc, dl, MVT::Other, RetOps); 572 } 573 574 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 575 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 576 // TODO: sret. 577 SDValue 578 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 579 CallingConv::ID CallConv, bool isVarArg, 580 bool isTailCall, 581 const SmallVectorImpl<ISD::OutputArg> 582 &Outs, 583 const SmallVectorImpl<SDValue> &OutVals, 584 const SmallVectorImpl<ISD::InputArg> &Ins, 585 SDLoc dl, SelectionDAG &DAG, 586 SmallVectorImpl<SDValue> &InVals) const { 587 // Analyze operands of the call, assigning locations to each operand. 588 SmallVector<CCValAssign, 16> ArgLocs; 589 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 590 *DAG.getContext()); 591 AnalyzeArguments(CCInfo, ArgLocs, Outs); 592 593 // Get a count of how many bytes are to be pushed on the stack. 594 unsigned NumBytes = CCInfo.getNextStackOffset(); 595 596 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, dl, 597 getPointerTy(), true), 598 dl); 599 600 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 601 SmallVector<SDValue, 12> MemOpChains; 602 SDValue StackPtr; 603 604 // Walk the register/memloc assignments, inserting copies/loads. 605 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 606 CCValAssign &VA = ArgLocs[i]; 607 608 SDValue Arg = OutVals[i]; 609 610 // Promote the value if needed. 611 switch (VA.getLocInfo()) { 612 default: llvm_unreachable("Unknown loc info!"); 613 case CCValAssign::Full: break; 614 case CCValAssign::SExt: 615 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 616 break; 617 case CCValAssign::ZExt: 618 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 619 break; 620 case CCValAssign::AExt: 621 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 622 break; 623 } 624 625 // Arguments that can be passed on register must be kept at RegsToPass 626 // vector 627 if (VA.isRegLoc()) { 628 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 629 } else { 630 assert(VA.isMemLoc()); 631 632 if (!StackPtr.getNode()) 633 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, getPointerTy()); 634 635 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 636 StackPtr, 637 DAG.getIntPtrConstant(VA.getLocMemOffset(), 638 dl)); 639 640 SDValue MemOp; 641 ISD::ArgFlagsTy Flags = Outs[i].Flags; 642 643 if (Flags.isByVal()) { 644 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16); 645 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, 646 Flags.getByValAlign(), 647 /*isVolatile*/false, 648 /*AlwaysInline=*/true, 649 /*isTailCall=*/false, 650 MachinePointerInfo(), 651 MachinePointerInfo()); 652 } else { 653 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), 654 false, false, 0); 655 } 656 657 MemOpChains.push_back(MemOp); 658 } 659 } 660 661 // Transform all store nodes into one single node because all store nodes are 662 // independent of each other. 663 if (!MemOpChains.empty()) 664 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 665 666 // Build a sequence of copy-to-reg nodes chained together with token chain and 667 // flag operands which copy the outgoing args into registers. The InFlag in 668 // necessary since all emitted instructions must be stuck together. 669 SDValue InFlag; 670 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 671 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 672 RegsToPass[i].second, InFlag); 673 InFlag = Chain.getValue(1); 674 } 675 676 // If the callee is a GlobalAddress node (quite common, every direct call is) 677 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 678 // Likewise ExternalSymbol -> TargetExternalSymbol. 679 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 680 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16); 681 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 682 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); 683 684 // Returns a chain & a flag for retval copy to use. 685 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 686 SmallVector<SDValue, 8> Ops; 687 Ops.push_back(Chain); 688 Ops.push_back(Callee); 689 690 // Add argument registers to the end of the list so that they are 691 // known live into the call. 692 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 693 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 694 RegsToPass[i].second.getValueType())); 695 696 if (InFlag.getNode()) 697 Ops.push_back(InFlag); 698 699 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops); 700 InFlag = Chain.getValue(1); 701 702 // Create the CALLSEQ_END node. 703 Chain = DAG.getCALLSEQ_END(Chain, 704 DAG.getConstant(NumBytes, dl, getPointerTy(), 705 true), 706 DAG.getConstant(0, dl, getPointerTy(), true), 707 InFlag, dl); 708 InFlag = Chain.getValue(1); 709 710 // Handle result values, copying them out of physregs into vregs that we 711 // return. 712 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 713 DAG, InVals); 714 } 715 716 /// LowerCallResult - Lower the result values of a call into the 717 /// appropriate copies out of appropriate physical registers. 718 /// 719 SDValue 720 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 721 CallingConv::ID CallConv, bool isVarArg, 722 const SmallVectorImpl<ISD::InputArg> &Ins, 723 SDLoc dl, SelectionDAG &DAG, 724 SmallVectorImpl<SDValue> &InVals) const { 725 726 // Assign locations to each value returned by this call. 727 SmallVector<CCValAssign, 16> RVLocs; 728 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 729 *DAG.getContext()); 730 731 AnalyzeReturnValues(CCInfo, RVLocs, Ins); 732 733 // Copy all of the result registers out of their specified physreg. 734 for (unsigned i = 0; i != RVLocs.size(); ++i) { 735 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 736 RVLocs[i].getValVT(), InFlag).getValue(1); 737 InFlag = Chain.getValue(2); 738 InVals.push_back(Chain.getValue(0)); 739 } 740 741 return Chain; 742 } 743 744 SDValue MSP430TargetLowering::LowerShifts(SDValue Op, 745 SelectionDAG &DAG) const { 746 unsigned Opc = Op.getOpcode(); 747 SDNode* N = Op.getNode(); 748 EVT VT = Op.getValueType(); 749 SDLoc dl(N); 750 751 // Expand non-constant shifts to loops: 752 if (!isa<ConstantSDNode>(N->getOperand(1))) 753 switch (Opc) { 754 default: llvm_unreachable("Invalid shift opcode!"); 755 case ISD::SHL: 756 return DAG.getNode(MSP430ISD::SHL, dl, 757 VT, N->getOperand(0), N->getOperand(1)); 758 case ISD::SRA: 759 return DAG.getNode(MSP430ISD::SRA, dl, 760 VT, N->getOperand(0), N->getOperand(1)); 761 case ISD::SRL: 762 return DAG.getNode(MSP430ISD::SRL, dl, 763 VT, N->getOperand(0), N->getOperand(1)); 764 } 765 766 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 767 768 // Expand the stuff into sequence of shifts. 769 // FIXME: for some shift amounts this might be done better! 770 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N 771 SDValue Victim = N->getOperand(0); 772 773 if (Opc == ISD::SRL && ShiftAmount) { 774 // Emit a special goodness here: 775 // srl A, 1 => clrc; rrc A 776 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim); 777 ShiftAmount -= 1; 778 } 779 780 while (ShiftAmount--) 781 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 782 dl, VT, Victim); 783 784 return Victim; 785 } 786 787 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, 788 SelectionDAG &DAG) const { 789 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 790 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 791 792 // Create the TargetGlobalAddress node, folding in the constant offset. 793 SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), 794 getPointerTy(), Offset); 795 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), 796 getPointerTy(), Result); 797 } 798 799 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, 800 SelectionDAG &DAG) const { 801 SDLoc dl(Op); 802 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 803 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 804 805 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result); 806 } 807 808 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op, 809 SelectionDAG &DAG) const { 810 SDLoc dl(Op); 811 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 812 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy()); 813 814 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result); 815 } 816 817 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, 818 ISD::CondCode CC, 819 SDLoc dl, SelectionDAG &DAG) { 820 // FIXME: Handle bittests someday 821 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); 822 823 // FIXME: Handle jump negative someday 824 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID; 825 switch (CC) { 826 default: llvm_unreachable("Invalid integer condition!"); 827 case ISD::SETEQ: 828 TCC = MSP430CC::COND_E; // aka COND_Z 829 // Minor optimization: if LHS is a constant, swap operands, then the 830 // constant can be folded into comparison. 831 if (LHS.getOpcode() == ISD::Constant) 832 std::swap(LHS, RHS); 833 break; 834 case ISD::SETNE: 835 TCC = MSP430CC::COND_NE; // aka COND_NZ 836 // Minor optimization: if LHS is a constant, swap operands, then the 837 // constant can be folded into comparison. 838 if (LHS.getOpcode() == ISD::Constant) 839 std::swap(LHS, RHS); 840 break; 841 case ISD::SETULE: 842 std::swap(LHS, RHS); // FALLTHROUGH 843 case ISD::SETUGE: 844 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to 845 // fold constant into instruction. 846 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 847 LHS = RHS; 848 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 849 TCC = MSP430CC::COND_LO; 850 break; 851 } 852 TCC = MSP430CC::COND_HS; // aka COND_C 853 break; 854 case ISD::SETUGT: 855 std::swap(LHS, RHS); // FALLTHROUGH 856 case ISD::SETULT: 857 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to 858 // fold constant into instruction. 859 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 860 LHS = RHS; 861 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 862 TCC = MSP430CC::COND_HS; 863 break; 864 } 865 TCC = MSP430CC::COND_LO; // aka COND_NC 866 break; 867 case ISD::SETLE: 868 std::swap(LHS, RHS); // FALLTHROUGH 869 case ISD::SETGE: 870 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to 871 // fold constant into instruction. 872 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 873 LHS = RHS; 874 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 875 TCC = MSP430CC::COND_L; 876 break; 877 } 878 TCC = MSP430CC::COND_GE; 879 break; 880 case ISD::SETGT: 881 std::swap(LHS, RHS); // FALLTHROUGH 882 case ISD::SETLT: 883 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 884 // fold constant into instruction. 885 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 886 LHS = RHS; 887 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); 888 TCC = MSP430CC::COND_GE; 889 break; 890 } 891 TCC = MSP430CC::COND_L; 892 break; 893 } 894 895 TargetCC = DAG.getConstant(TCC, dl, MVT::i8); 896 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS); 897 } 898 899 900 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 901 SDValue Chain = Op.getOperand(0); 902 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 903 SDValue LHS = Op.getOperand(2); 904 SDValue RHS = Op.getOperand(3); 905 SDValue Dest = Op.getOperand(4); 906 SDLoc dl (Op); 907 908 SDValue TargetCC; 909 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 910 911 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 912 Chain, Dest, TargetCC, Flag); 913 } 914 915 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 916 SDValue LHS = Op.getOperand(0); 917 SDValue RHS = Op.getOperand(1); 918 SDLoc dl (Op); 919 920 // If we are doing an AND and testing against zero, then the CMP 921 // will not be generated. The AND (or BIT) will generate the condition codes, 922 // but they are different from CMP. 923 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so 924 // lowering & isel wouldn't diverge. 925 bool andCC = false; 926 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 927 if (RHSC->isNullValue() && LHS.hasOneUse() && 928 (LHS.getOpcode() == ISD::AND || 929 (LHS.getOpcode() == ISD::TRUNCATE && 930 LHS.getOperand(0).getOpcode() == ISD::AND))) { 931 andCC = true; 932 } 933 } 934 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 935 SDValue TargetCC; 936 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 937 938 // Get the condition codes directly from the status register, if its easy. 939 // Otherwise a branch will be generated. Note that the AND and BIT 940 // instructions generate different flags than CMP, the carry bit can be used 941 // for NE/EQ. 942 bool Invert = false; 943 bool Shift = false; 944 bool Convert = true; 945 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) { 946 default: 947 Convert = false; 948 break; 949 case MSP430CC::COND_HS: 950 // Res = SR & 1, no processing is required 951 break; 952 case MSP430CC::COND_LO: 953 // Res = ~(SR & 1) 954 Invert = true; 955 break; 956 case MSP430CC::COND_NE: 957 if (andCC) { 958 // C = ~Z, thus Res = SR & 1, no processing is required 959 } else { 960 // Res = ~((SR >> 1) & 1) 961 Shift = true; 962 Invert = true; 963 } 964 break; 965 case MSP430CC::COND_E: 966 Shift = true; 967 // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however, 968 // Res = (SR >> 1) & 1 is 1 word shorter. 969 break; 970 } 971 EVT VT = Op.getValueType(); 972 SDValue One = DAG.getConstant(1, dl, VT); 973 if (Convert) { 974 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, 975 MVT::i16, Flag); 976 if (Shift) 977 // FIXME: somewhere this is turned into a SRL, lower it MSP specific? 978 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); 979 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); 980 if (Invert) 981 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); 982 return SR; 983 } else { 984 SDValue Zero = DAG.getConstant(0, dl, VT); 985 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 986 SDValue Ops[] = {One, Zero, TargetCC, Flag}; 987 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 988 } 989 } 990 991 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, 992 SelectionDAG &DAG) const { 993 SDValue LHS = Op.getOperand(0); 994 SDValue RHS = Op.getOperand(1); 995 SDValue TrueV = Op.getOperand(2); 996 SDValue FalseV = Op.getOperand(3); 997 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 998 SDLoc dl (Op); 999 1000 SDValue TargetCC; 1001 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 1002 1003 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 1004 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag}; 1005 1006 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1007 } 1008 1009 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, 1010 SelectionDAG &DAG) const { 1011 SDValue Val = Op.getOperand(0); 1012 EVT VT = Op.getValueType(); 1013 SDLoc dl(Op); 1014 1015 assert(VT == MVT::i16 && "Only support i16 for now!"); 1016 1017 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, 1018 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), 1019 DAG.getValueType(Val.getValueType())); 1020 } 1021 1022 SDValue 1023 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 1024 MachineFunction &MF = DAG.getMachineFunction(); 1025 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1026 int ReturnAddrIndex = FuncInfo->getRAIndex(); 1027 1028 if (ReturnAddrIndex == 0) { 1029 // Set up a frame object for the return address. 1030 uint64_t SlotSize = getDataLayout()->getPointerSize(); 1031 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 1032 true); 1033 FuncInfo->setRAIndex(ReturnAddrIndex); 1034 } 1035 1036 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1037 } 1038 1039 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, 1040 SelectionDAG &DAG) const { 1041 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1042 MFI->setReturnAddressIsTaken(true); 1043 1044 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 1045 return SDValue(); 1046 1047 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1048 SDLoc dl(Op); 1049 1050 if (Depth > 0) { 1051 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 1052 SDValue Offset = 1053 DAG.getConstant(getDataLayout()->getPointerSize(), dl, MVT::i16); 1054 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 1055 DAG.getNode(ISD::ADD, dl, getPointerTy(), 1056 FrameAddr, Offset), 1057 MachinePointerInfo(), false, false, false, 0); 1058 } 1059 1060 // Just load the return address. 1061 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 1062 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 1063 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 1064 } 1065 1066 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, 1067 SelectionDAG &DAG) const { 1068 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1069 MFI->setFrameAddressIsTaken(true); 1070 1071 EVT VT = Op.getValueType(); 1072 SDLoc dl(Op); // FIXME probably not meaningful 1073 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1074 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1075 MSP430::FP, VT); 1076 while (Depth--) 1077 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 1078 MachinePointerInfo(), 1079 false, false, false, 0); 1080 return FrameAddr; 1081 } 1082 1083 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op, 1084 SelectionDAG &DAG) const { 1085 MachineFunction &MF = DAG.getMachineFunction(); 1086 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1087 1088 // Frame index of first vararg argument 1089 SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1090 getPointerTy()); 1091 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1092 1093 // Create a store of the frame index to the location operand 1094 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, 1095 Op.getOperand(1), MachinePointerInfo(SV), 1096 false, false, 0); 1097 } 1098 1099 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op, 1100 SelectionDAG &DAG) const { 1101 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1102 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 1103 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), 1104 getPointerTy(), Result); 1105 } 1106 1107 /// getPostIndexedAddressParts - returns true by value, base pointer and 1108 /// offset pointer and addressing mode by reference if this node can be 1109 /// combined with a load / store to form a post-indexed load / store. 1110 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1111 SDValue &Base, 1112 SDValue &Offset, 1113 ISD::MemIndexedMode &AM, 1114 SelectionDAG &DAG) const { 1115 1116 LoadSDNode *LD = cast<LoadSDNode>(N); 1117 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 1118 return false; 1119 1120 EVT VT = LD->getMemoryVT(); 1121 if (VT != MVT::i8 && VT != MVT::i16) 1122 return false; 1123 1124 if (Op->getOpcode() != ISD::ADD) 1125 return false; 1126 1127 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 1128 uint64_t RHSC = RHS->getZExtValue(); 1129 if ((VT == MVT::i16 && RHSC != 2) || 1130 (VT == MVT::i8 && RHSC != 1)) 1131 return false; 1132 1133 Base = Op->getOperand(0); 1134 Offset = DAG.getConstant(RHSC, SDLoc(N), VT); 1135 AM = ISD::POST_INC; 1136 return true; 1137 } 1138 1139 return false; 1140 } 1141 1142 1143 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { 1144 switch (Opcode) { 1145 default: return nullptr; 1146 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; 1147 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG"; 1148 case MSP430ISD::RRA: return "MSP430ISD::RRA"; 1149 case MSP430ISD::RLA: return "MSP430ISD::RLA"; 1150 case MSP430ISD::RRC: return "MSP430ISD::RRC"; 1151 case MSP430ISD::CALL: return "MSP430ISD::CALL"; 1152 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; 1153 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; 1154 case MSP430ISD::CMP: return "MSP430ISD::CMP"; 1155 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; 1156 case MSP430ISD::SHL: return "MSP430ISD::SHL"; 1157 case MSP430ISD::SRA: return "MSP430ISD::SRA"; 1158 } 1159 } 1160 1161 bool MSP430TargetLowering::isTruncateFree(Type *Ty1, 1162 Type *Ty2) const { 1163 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 1164 return false; 1165 1166 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits()); 1167 } 1168 1169 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 1170 if (!VT1.isInteger() || !VT2.isInteger()) 1171 return false; 1172 1173 return (VT1.getSizeInBits() > VT2.getSizeInBits()); 1174 } 1175 1176 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 1177 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1178 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16); 1179 } 1180 1181 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 1182 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1183 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; 1184 } 1185 1186 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 1187 return isZExtFree(Val.getValueType(), VT2); 1188 } 1189 1190 //===----------------------------------------------------------------------===// 1191 // Other Lowering Code 1192 //===----------------------------------------------------------------------===// 1193 1194 MachineBasicBlock* 1195 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, 1196 MachineBasicBlock *BB) const { 1197 MachineFunction *F = BB->getParent(); 1198 MachineRegisterInfo &RI = F->getRegInfo(); 1199 DebugLoc dl = MI->getDebugLoc(); 1200 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); 1201 1202 unsigned Opc; 1203 const TargetRegisterClass * RC; 1204 switch (MI->getOpcode()) { 1205 default: llvm_unreachable("Invalid shift opcode!"); 1206 case MSP430::Shl8: 1207 Opc = MSP430::SHL8r1; 1208 RC = &MSP430::GR8RegClass; 1209 break; 1210 case MSP430::Shl16: 1211 Opc = MSP430::SHL16r1; 1212 RC = &MSP430::GR16RegClass; 1213 break; 1214 case MSP430::Sra8: 1215 Opc = MSP430::SAR8r1; 1216 RC = &MSP430::GR8RegClass; 1217 break; 1218 case MSP430::Sra16: 1219 Opc = MSP430::SAR16r1; 1220 RC = &MSP430::GR16RegClass; 1221 break; 1222 case MSP430::Srl8: 1223 Opc = MSP430::SAR8r1c; 1224 RC = &MSP430::GR8RegClass; 1225 break; 1226 case MSP430::Srl16: 1227 Opc = MSP430::SAR16r1c; 1228 RC = &MSP430::GR16RegClass; 1229 break; 1230 } 1231 1232 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1233 MachineFunction::iterator I = BB; 1234 ++I; 1235 1236 // Create loop block 1237 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1238 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1239 1240 F->insert(I, LoopBB); 1241 F->insert(I, RemBB); 1242 1243 // Update machine-CFG edges by transferring all successors of the current 1244 // block to the block containing instructions after shift. 1245 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 1246 BB->end()); 1247 RemBB->transferSuccessorsAndUpdatePHIs(BB); 1248 1249 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB 1250 BB->addSuccessor(LoopBB); 1251 BB->addSuccessor(RemBB); 1252 LoopBB->addSuccessor(RemBB); 1253 LoopBB->addSuccessor(LoopBB); 1254 1255 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass); 1256 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); 1257 unsigned ShiftReg = RI.createVirtualRegister(RC); 1258 unsigned ShiftReg2 = RI.createVirtualRegister(RC); 1259 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg(); 1260 unsigned SrcReg = MI->getOperand(1).getReg(); 1261 unsigned DstReg = MI->getOperand(0).getReg(); 1262 1263 // BB: 1264 // cmp 0, N 1265 // je RemBB 1266 BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) 1267 .addReg(ShiftAmtSrcReg).addImm(0); 1268 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1269 .addMBB(RemBB) 1270 .addImm(MSP430CC::COND_E); 1271 1272 // LoopBB: 1273 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1274 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1275 // ShiftReg2 = shift ShiftReg 1276 // ShiftAmt2 = ShiftAmt - 1; 1277 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) 1278 .addReg(SrcReg).addMBB(BB) 1279 .addReg(ShiftReg2).addMBB(LoopBB); 1280 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) 1281 .addReg(ShiftAmtSrcReg).addMBB(BB) 1282 .addReg(ShiftAmtReg2).addMBB(LoopBB); 1283 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) 1284 .addReg(ShiftReg); 1285 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) 1286 .addReg(ShiftAmtReg).addImm(1); 1287 BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) 1288 .addMBB(LoopBB) 1289 .addImm(MSP430CC::COND_NE); 1290 1291 // RemBB: 1292 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1293 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) 1294 .addReg(SrcReg).addMBB(BB) 1295 .addReg(ShiftReg2).addMBB(LoopBB); 1296 1297 MI->eraseFromParent(); // The pseudo instruction is gone now. 1298 return RemBB; 1299 } 1300 1301 MachineBasicBlock* 1302 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1303 MachineBasicBlock *BB) const { 1304 unsigned Opc = MI->getOpcode(); 1305 1306 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || 1307 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || 1308 Opc == MSP430::Srl8 || Opc == MSP430::Srl16) 1309 return EmitShiftInstr(MI, BB); 1310 1311 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 1312 DebugLoc dl = MI->getDebugLoc(); 1313 1314 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && 1315 "Unexpected instr type to insert"); 1316 1317 // To "insert" a SELECT instruction, we actually have to insert the diamond 1318 // control-flow pattern. The incoming instruction knows the destination vreg 1319 // to set, the condition code register to branch on, the true/false values to 1320 // select between, and a branch opcode to use. 1321 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1322 MachineFunction::iterator I = BB; 1323 ++I; 1324 1325 // thisMBB: 1326 // ... 1327 // TrueVal = ... 1328 // cmpTY ccX, r1, r2 1329 // jCC copy1MBB 1330 // fallthrough --> copy0MBB 1331 MachineBasicBlock *thisMBB = BB; 1332 MachineFunction *F = BB->getParent(); 1333 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1334 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 1335 F->insert(I, copy0MBB); 1336 F->insert(I, copy1MBB); 1337 // Update machine-CFG edges by transferring all successors of the current 1338 // block to the new block which will contain the Phi node for the select. 1339 copy1MBB->splice(copy1MBB->begin(), BB, 1340 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1341 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 1342 // Next, add the true and fallthrough blocks as its successors. 1343 BB->addSuccessor(copy0MBB); 1344 BB->addSuccessor(copy1MBB); 1345 1346 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1347 .addMBB(copy1MBB) 1348 .addImm(MI->getOperand(3).getImm()); 1349 1350 // copy0MBB: 1351 // %FalseValue = ... 1352 // # fallthrough to copy1MBB 1353 BB = copy0MBB; 1354 1355 // Update machine-CFG edges 1356 BB->addSuccessor(copy1MBB); 1357 1358 // copy1MBB: 1359 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1360 // ... 1361 BB = copy1MBB; 1362 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), 1363 MI->getOperand(0).getReg()) 1364 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1365 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1366 1367 MI->eraseFromParent(); // The pseudo instruction is gone now. 1368 return BB; 1369 } 1370