1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MSP430TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "msp430-lower"
15 
16 #include "MSP430ISelLowering.h"
17 #include "MSP430.h"
18 #include "MSP430TargetMachine.h"
19 #include "MSP430Subtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/ADT/VectorExtras.h"
36 using namespace llvm;
37 
38 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
39   TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
40 
41   // Set up the register classes.
42   addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
43   addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
44 
45   // Compute derived properties from the register classes
46   computeRegisterProperties();
47 
48   // Provide all sorts of operation actions
49 
50   // Division is expensive
51   setIntDivIsCheap(false);
52 
53   // Even if we have only 1 bit shift here, we can perform
54   // shifts of the whole bitwidth 1 bit per step.
55   setShiftAmountType(MVT::i8);
56 
57   setStackPointerRegisterToSaveRestore(MSP430::SPW);
58   setBooleanContents(ZeroOrOneBooleanContent);
59   setSchedulingPreference(SchedulingForLatency);
60 
61   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
62   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
63   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
64   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
65   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
66 
67   // We don't have any truncstores
68   setTruncStoreAction(MVT::i16, MVT::i8, Expand);
69 
70   setOperationAction(ISD::SRA,              MVT::i8,    Custom);
71   setOperationAction(ISD::SHL,              MVT::i8,    Custom);
72   setOperationAction(ISD::SRL,              MVT::i8,    Custom);
73   setOperationAction(ISD::SRA,              MVT::i16,   Custom);
74   setOperationAction(ISD::SHL,              MVT::i16,   Custom);
75   setOperationAction(ISD::SRL,              MVT::i16,   Custom);
76   setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
77   setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
78   setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
79   setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
80   setOperationAction(ISD::RET,              MVT::Other, Custom);
81   setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
82   setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
83   setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
84   setOperationAction(ISD::BRIND,            MVT::Other, Expand);
85   setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
86   setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
87   setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
88   setOperationAction(ISD::SETCC,            MVT::i8,    Expand);
89   setOperationAction(ISD::SETCC,            MVT::i16,   Expand);
90   setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
91   setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
92   setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
93   setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
94   setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
95 
96   // FIXME: Implement efficiently multiplication by a constant
97   setOperationAction(ISD::MUL,              MVT::i16,   Expand);
98   setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
99   setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
100   setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
101   setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
102 
103   setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
104   setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
105   setOperationAction(ISD::UREM,             MVT::i16,   Expand);
106   setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
107   setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
108   setOperationAction(ISD::SREM,             MVT::i16,   Expand);
109 }
110 
111 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
112   switch (Op.getOpcode()) {
113   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
114   case ISD::SHL: // FALLTHROUGH
115   case ISD::SRL:
116   case ISD::SRA:              return LowerShifts(Op, DAG);
117   case ISD::RET:              return LowerRET(Op, DAG);
118   case ISD::CALL:             return LowerCALL(Op, DAG);
119   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
120   case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
121   case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
122   case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
123   case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
124   default:
125     assert(0 && "unimplemented operand");
126     return SDValue();
127   }
128 }
129 
130 /// getFunctionAlignment - Return the Log2 alignment of this function.
131 unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
132   return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
133 }
134 
135 //===----------------------------------------------------------------------===//
136 //                      Calling Convention Implementation
137 //===----------------------------------------------------------------------===//
138 
139 #include "MSP430GenCallingConv.inc"
140 
141 SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
142                                                     SelectionDAG &DAG) {
143   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
144   switch (CC) {
145   default:
146     assert(0 && "Unsupported calling convention");
147   case CallingConv::C:
148   case CallingConv::Fast:
149     return LowerCCCArguments(Op, DAG);
150   }
151 }
152 
153 SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
154   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
155   unsigned CallingConv = TheCall->getCallingConv();
156   switch (CallingConv) {
157   default:
158     assert(0 && "Unsupported calling convention");
159   case CallingConv::Fast:
160   case CallingConv::C:
161     return LowerCCCCallTo(Op, DAG, CallingConv);
162   }
163 }
164 
165 /// LowerCCCArguments - transform physical registers into virtual registers and
166 /// generate load operations for arguments places on the stack.
167 // FIXME: struct return stuff
168 // FIXME: varargs
169 SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
170                                                 SelectionDAG &DAG) {
171   MachineFunction &MF = DAG.getMachineFunction();
172   MachineFrameInfo *MFI = MF.getFrameInfo();
173   MachineRegisterInfo &RegInfo = MF.getRegInfo();
174   SDValue Root = Op.getOperand(0);
175   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
176   unsigned CC = MF.getFunction()->getCallingConv();
177   DebugLoc dl = Op.getDebugLoc();
178 
179   // Assign locations to all of the incoming arguments.
180   SmallVector<CCValAssign, 16> ArgLocs;
181   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
182   CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
183 
184   assert(!isVarArg && "Varargs not supported yet");
185 
186   SmallVector<SDValue, 16> ArgValues;
187   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
188     CCValAssign &VA = ArgLocs[i];
189     if (VA.isRegLoc()) {
190       // Arguments passed in registers
191       MVT RegVT = VA.getLocVT();
192       switch (RegVT.getSimpleVT()) {
193       default:
194         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
195              << RegVT.getSimpleVT()
196              << "\n";
197         abort();
198       case MVT::i16:
199         unsigned VReg =
200           RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
201         RegInfo.addLiveIn(VA.getLocReg(), VReg);
202         SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
203 
204         // If this is an 8-bit value, it is really passed promoted to 16
205         // bits. Insert an assert[sz]ext to capture this, then truncate to the
206         // right size.
207         if (VA.getLocInfo() == CCValAssign::SExt)
208           ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
209                                  DAG.getValueType(VA.getValVT()));
210         else if (VA.getLocInfo() == CCValAssign::ZExt)
211           ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
212                                  DAG.getValueType(VA.getValVT()));
213 
214         if (VA.getLocInfo() != CCValAssign::Full)
215           ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
216 
217         ArgValues.push_back(ArgValue);
218       }
219     } else {
220       // Sanity check
221       assert(VA.isMemLoc());
222       // Load the argument to a virtual register
223       unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
224       if (ObjSize > 2) {
225         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
226              << VA.getLocVT().getSimpleVT()
227              << "\n";
228       }
229       // Create the frame index object for this incoming parameter...
230       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
231 
232       // Create the SelectionDAG nodes corresponding to a load
233       //from this parameter
234       SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
235       ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
236                                       PseudoSourceValue::getFixedStack(FI), 0));
237     }
238   }
239 
240   ArgValues.push_back(Root);
241 
242   // Return the new list of results.
243   return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
244                      &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
245 }
246 
247 SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
248   // CCValAssign - represent the assignment of the return value to a location
249   SmallVector<CCValAssign, 16> RVLocs;
250   unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
251   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
252   DebugLoc dl = Op.getDebugLoc();
253 
254   // CCState - Info about the registers and stack slot.
255   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
256 
257   // Analize return values of ISD::RET
258   CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
259 
260   // If this is the first return lowered for this function, add the regs to the
261   // liveout set for the function.
262   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
263     for (unsigned i = 0; i != RVLocs.size(); ++i)
264       if (RVLocs[i].isRegLoc())
265         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
266   }
267 
268   // The chain is always operand #0
269   SDValue Chain = Op.getOperand(0);
270   SDValue Flag;
271 
272   // Copy the result values into the output registers.
273   for (unsigned i = 0; i != RVLocs.size(); ++i) {
274     CCValAssign &VA = RVLocs[i];
275     assert(VA.isRegLoc() && "Can only return in registers!");
276 
277     // ISD::RET => ret chain, (regnum1,val1), ...
278     // So i*2+1 index only the regnums
279     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
280                              Op.getOperand(i*2+1), Flag);
281 
282     // Guarantee that all emitted copies are stuck together,
283     // avoiding something bad.
284     Flag = Chain.getValue(1);
285   }
286 
287   if (Flag.getNode())
288     return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
289 
290   // Return Void
291   return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
292 }
293 
294 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
295 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
296 /// TODO: sret.
297 SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
298                                              unsigned CC) {
299   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
300   SDValue Chain  = TheCall->getChain();
301   SDValue Callee = TheCall->getCallee();
302   bool isVarArg  = TheCall->isVarArg();
303   DebugLoc dl = Op.getDebugLoc();
304 
305   // Analyze operands of the call, assigning locations to each operand.
306   SmallVector<CCValAssign, 16> ArgLocs;
307   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
308 
309   CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
310 
311   // Get a count of how many bytes are to be pushed on the stack.
312   unsigned NumBytes = CCInfo.getNextStackOffset();
313 
314   Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
315                                                       getPointerTy(), true));
316 
317   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
318   SmallVector<SDValue, 12> MemOpChains;
319   SDValue StackPtr;
320 
321   // Walk the register/memloc assignments, inserting copies/loads.
322   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
323     CCValAssign &VA = ArgLocs[i];
324 
325     // Arguments start after the 5 first operands of ISD::CALL
326     SDValue Arg = TheCall->getArg(i);
327 
328     // Promote the value if needed.
329     switch (VA.getLocInfo()) {
330       default: assert(0 && "Unknown loc info!");
331       case CCValAssign::Full: break;
332       case CCValAssign::SExt:
333         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
334         break;
335       case CCValAssign::ZExt:
336         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
337         break;
338       case CCValAssign::AExt:
339         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
340         break;
341     }
342 
343     // Arguments that can be passed on register must be kept at RegsToPass
344     // vector
345     if (VA.isRegLoc()) {
346       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
347     } else {
348       assert(VA.isMemLoc());
349 
350       if (StackPtr.getNode() == 0)
351         StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
352 
353       SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
354                                    StackPtr,
355                                    DAG.getIntPtrConstant(VA.getLocMemOffset()));
356 
357 
358       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
359                                          PseudoSourceValue::getStack(),
360                                          VA.getLocMemOffset()));
361     }
362   }
363 
364   // Transform all store nodes into one single node because all store nodes are
365   // independent of each other.
366   if (!MemOpChains.empty())
367     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
368                         &MemOpChains[0], MemOpChains.size());
369 
370   // Build a sequence of copy-to-reg nodes chained together with token chain and
371   // flag operands which copy the outgoing args into registers.  The InFlag in
372   // necessary since all emited instructions must be stuck together.
373   SDValue InFlag;
374   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
375     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
376                              RegsToPass[i].second, InFlag);
377     InFlag = Chain.getValue(1);
378   }
379 
380   // If the callee is a GlobalAddress node (quite common, every direct call is)
381   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
382   // Likewise ExternalSymbol -> TargetExternalSymbol.
383   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
384     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
385   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
386     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
387 
388   // Returns a chain & a flag for retval copy to use.
389   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
390   SmallVector<SDValue, 8> Ops;
391   Ops.push_back(Chain);
392   Ops.push_back(Callee);
393 
394   // Add argument registers to the end of the list so that they are
395   // known live into the call.
396   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
397     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
398                                   RegsToPass[i].second.getValueType()));
399 
400   if (InFlag.getNode())
401     Ops.push_back(InFlag);
402 
403   Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
404   InFlag = Chain.getValue(1);
405 
406   // Create the CALLSEQ_END node.
407   Chain = DAG.getCALLSEQ_END(Chain,
408                              DAG.getConstant(NumBytes, getPointerTy(), true),
409                              DAG.getConstant(0, getPointerTy(), true),
410                              InFlag);
411   InFlag = Chain.getValue(1);
412 
413   // Handle result values, copying them out of physregs into vregs that we
414   // return.
415   return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
416                  Op.getResNo());
417 }
418 
419 /// LowerCallResult - Lower the result values of an ISD::CALL into the
420 /// appropriate copies out of appropriate physical registers.  This assumes that
421 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
422 /// being lowered. Returns a SDNode with the same number of values as the
423 /// ISD::CALL.
424 SDNode*
425 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
426                                       CallSDNode *TheCall,
427                                       unsigned CallingConv,
428                                       SelectionDAG &DAG) {
429   bool isVarArg = TheCall->isVarArg();
430   DebugLoc dl = TheCall->getDebugLoc();
431 
432   // Assign locations to each value returned by this call.
433   SmallVector<CCValAssign, 16> RVLocs;
434   CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
435 
436   CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
437   SmallVector<SDValue, 8> ResultVals;
438 
439   // Copy all of the result registers out of their specified physreg.
440   for (unsigned i = 0; i != RVLocs.size(); ++i) {
441     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
442                                RVLocs[i].getValVT(), InFlag).getValue(1);
443     InFlag = Chain.getValue(2);
444     ResultVals.push_back(Chain.getValue(0));
445   }
446 
447   ResultVals.push_back(Chain);
448 
449   // Merge everything together with a MERGE_VALUES node.
450   return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
451                      &ResultVals[0], ResultVals.size()).getNode();
452 }
453 
454 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
455                                           SelectionDAG &DAG) {
456   unsigned Opc = Op.getOpcode();
457   SDNode* N = Op.getNode();
458   MVT VT = Op.getValueType();
459   DebugLoc dl = N->getDebugLoc();
460 
461   // We currently only lower shifts of constant argument.
462   if (!isa<ConstantSDNode>(N->getOperand(1)))
463     return SDValue();
464 
465   uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
466 
467   // Expand the stuff into sequence of shifts.
468   // FIXME: for some shift amounts this might be done better!
469   // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
470   SDValue Victim = N->getOperand(0);
471 
472   if (Opc == ISD::SRL && ShiftAmount) {
473     // Emit a special goodness here:
474     // srl A, 1 => clrc; rrc A
475     Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
476     ShiftAmount -= 1;
477   }
478 
479   while (ShiftAmount--)
480     Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
481                          dl, VT, Victim);
482 
483   return Victim;
484 }
485 
486 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
487   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
488   int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
489 
490   // Create the TargetGlobalAddress node, folding in the constant offset.
491   SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
492   return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
493                      getPointerTy(), Result);
494 }
495 
496 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
497                                                   SelectionDAG &DAG) {
498   DebugLoc dl = Op.getDebugLoc();
499   const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
500   SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
501 
502   return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
503 }
504 
505 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC,
506                        ISD::CondCode CC,
507                        DebugLoc dl, SelectionDAG &DAG) {
508   // FIXME: Handle bittests someday
509   assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
510 
511   // FIXME: Handle jump negative someday
512   TargetCC = MSP430::COND_INVALID;
513   switch (CC) {
514   default: assert(0 && "Invalid integer condition!");
515   case ISD::SETEQ:
516     TargetCC = MSP430::COND_E;  // aka COND_Z
517     break;
518   case ISD::SETNE:
519     TargetCC = MSP430::COND_NE; // aka COND_NZ
520     break;
521   case ISD::SETULE:
522     std::swap(LHS, RHS);        // FALLTHROUGH
523   case ISD::SETUGE:
524     TargetCC = MSP430::COND_HS; // aka COND_C
525     break;
526   case ISD::SETUGT:
527     std::swap(LHS, RHS);        // FALLTHROUGH
528   case ISD::SETULT:
529     TargetCC = MSP430::COND_LO; // aka COND_NC
530     break;
531   case ISD::SETLE:
532     std::swap(LHS, RHS);        // FALLTHROUGH
533   case ISD::SETGE:
534     TargetCC = MSP430::COND_GE;
535     break;
536   case ISD::SETGT:
537     std::swap(LHS, RHS);        // FALLTHROUGH
538   case ISD::SETLT:
539     TargetCC = MSP430::COND_L;
540     break;
541   }
542 
543   return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
544 }
545 
546 
547 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
548   SDValue Chain = Op.getOperand(0);
549   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
550   SDValue LHS   = Op.getOperand(2);
551   SDValue RHS   = Op.getOperand(3);
552   SDValue Dest  = Op.getOperand(4);
553   DebugLoc dl   = Op.getDebugLoc();
554 
555   unsigned TargetCC = MSP430::COND_INVALID;
556   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
557 
558   return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
559                      Chain,
560                      Dest, DAG.getConstant(TargetCC, MVT::i8),
561                      Flag);
562 }
563 
564 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
565   SDValue LHS    = Op.getOperand(0);
566   SDValue RHS    = Op.getOperand(1);
567   SDValue TrueV  = Op.getOperand(2);
568   SDValue FalseV = Op.getOperand(3);
569   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
570   DebugLoc dl    = Op.getDebugLoc();
571 
572   unsigned TargetCC = MSP430::COND_INVALID;
573   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
574 
575   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
576   SmallVector<SDValue, 4> Ops;
577   Ops.push_back(TrueV);
578   Ops.push_back(FalseV);
579   Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
580   Ops.push_back(Flag);
581 
582   return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
583 }
584 
585 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
586                                                SelectionDAG &DAG) {
587   SDValue Val = Op.getOperand(0);
588   MVT VT      = Op.getValueType();
589   DebugLoc dl = Op.getDebugLoc();
590 
591   assert(VT == MVT::i16 && "Only support i16 for now!");
592 
593   return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
594                      DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
595                      DAG.getValueType(Val.getValueType()));
596 }
597 
598 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
599   switch (Opcode) {
600   default: return NULL;
601   case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
602   case MSP430ISD::RRA:                return "MSP430ISD::RRA";
603   case MSP430ISD::RLA:                return "MSP430ISD::RLA";
604   case MSP430ISD::RRC:                return "MSP430ISD::RRC";
605   case MSP430ISD::CALL:               return "MSP430ISD::CALL";
606   case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
607   case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
608   case MSP430ISD::CMP:                return "MSP430ISD::CMP";
609   case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
610   }
611 }
612 
613 //===----------------------------------------------------------------------===//
614 //  Other Lowering Code
615 //===----------------------------------------------------------------------===//
616 
617 MachineBasicBlock*
618 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
619                                                   MachineBasicBlock *BB) const {
620   const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
621   DebugLoc dl = MI->getDebugLoc();
622   assert((MI->getOpcode() == MSP430::Select16 ||
623           MI->getOpcode() == MSP430::Select8) &&
624          "Unexpected instr type to insert");
625 
626   // To "insert" a SELECT instruction, we actually have to insert the diamond
627   // control-flow pattern.  The incoming instruction knows the destination vreg
628   // to set, the condition code register to branch on, the true/false values to
629   // select between, and a branch opcode to use.
630   const BasicBlock *LLVM_BB = BB->getBasicBlock();
631   MachineFunction::iterator I = BB;
632   ++I;
633 
634   //  thisMBB:
635   //  ...
636   //   TrueVal = ...
637   //   cmpTY ccX, r1, r2
638   //   jCC copy1MBB
639   //   fallthrough --> copy0MBB
640   MachineBasicBlock *thisMBB = BB;
641   MachineFunction *F = BB->getParent();
642   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
643   MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
644   BuildMI(BB, dl, TII.get(MSP430::JCC))
645     .addMBB(copy1MBB)
646     .addImm(MI->getOperand(3).getImm());
647   F->insert(I, copy0MBB);
648   F->insert(I, copy1MBB);
649   // Update machine-CFG edges by transferring all successors of the current
650   // block to the new block which will contain the Phi node for the select.
651   copy1MBB->transferSuccessors(BB);
652   // Next, add the true and fallthrough blocks as its successors.
653   BB->addSuccessor(copy0MBB);
654   BB->addSuccessor(copy1MBB);
655 
656   //  copy0MBB:
657   //   %FalseValue = ...
658   //   # fallthrough to copy1MBB
659   BB = copy0MBB;
660 
661   // Update machine-CFG edges
662   BB->addSuccessor(copy1MBB);
663 
664   //  copy1MBB:
665   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
666   //  ...
667   BB = copy1MBB;
668   BuildMI(BB, dl, TII.get(MSP430::PHI),
669           MI->getOperand(0).getReg())
670     .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
671     .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
672 
673   F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
674   return BB;
675 }
676