1 //===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Lanai target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "LanaiTargetMachine.h" 15 16 #include "Lanai.h" 17 #include "LanaiTargetObjectFile.h" 18 #include "LanaiTargetTransformInfo.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/CodeGen/Passes.h" 21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 22 #include "llvm/Support/FormattedStream.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetOptions.h" 25 26 using namespace llvm; 27 28 namespace llvm { 29 void initializeLanaiMemAluCombinerPass(PassRegistry &); 30 void initializeLanaiSetflagAluCombinerPass(PassRegistry &); 31 } // namespace llvm 32 33 extern "C" void LLVMInitializeLanaiTarget() { 34 // Register the target. 35 RegisterTargetMachine<LanaiTargetMachine> registered_target(TheLanaiTarget); 36 } 37 38 static std::string computeDataLayout(const Triple &TT) { 39 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp) 40 return "E" // Big endian 41 "-m:e" // ELF name manging 42 "-p:32:32" // 32-bit pointers, 32 bit aligned 43 "-i64:64" // 64 bit integers, 64 bit aligned 44 "-a:0:32" // 32 bit alignment of objects of aggregate type 45 "-n32" // 32 bit native integer width 46 "-S64"; // 64 bit natural stack alignment 47 } 48 49 LanaiTargetMachine::LanaiTargetMachine(const Target &TheTarget, 50 const Triple &TargetTriple, 51 StringRef Cpu, StringRef FeatureString, 52 const TargetOptions &Options, 53 Reloc::Model RelocationModel, 54 CodeModel::Model CodeModel, 55 CodeGenOpt::Level OptLevel) 56 : LLVMTargetMachine(TheTarget, computeDataLayout(TargetTriple), 57 TargetTriple, Cpu, FeatureString, Options, 58 RelocationModel, CodeModel, OptLevel), 59 Subtarget(TargetTriple, Cpu, FeatureString, *this, Options, 60 RelocationModel, CodeModel, OptLevel), 61 TLOF(new LanaiTargetObjectFile()) { 62 initAsmInfo(); 63 } 64 65 TargetIRAnalysis LanaiTargetMachine::getTargetIRAnalysis() { 66 return TargetIRAnalysis([this](const Function &F) { 67 return TargetTransformInfo(LanaiTTIImpl(this, F)); 68 }); 69 } 70 71 namespace { 72 // Lanai Code Generator Pass Configuration Options. 73 class LanaiPassConfig : public TargetPassConfig { 74 public: 75 LanaiPassConfig(LanaiTargetMachine *TM, PassManagerBase *PassManager) 76 : TargetPassConfig(TM, *PassManager) {} 77 78 LanaiTargetMachine &getLanaiTargetMachine() const { 79 return getTM<LanaiTargetMachine>(); 80 } 81 82 bool addInstSelector() override; 83 void addPreSched2() override; 84 void addPreEmitPass() override; 85 }; 86 } // namespace 87 88 TargetPassConfig * 89 LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) { 90 return new LanaiPassConfig(this, &PassManager); 91 } 92 93 // Install an instruction selector pass. 94 bool LanaiPassConfig::addInstSelector() { 95 addPass(createLanaiISelDag(getLanaiTargetMachine())); 96 return false; 97 } 98 99 // Implemented by targets that want to run passes immediately before 100 // machine code is emitted. 101 void LanaiPassConfig::addPreEmitPass() { 102 addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine())); 103 } 104 105 // Run passes after prolog-epilog insertion and before the second instruction 106 // scheduling pass. 107 void LanaiPassConfig::addPreSched2() { 108 addPass(createLanaiMemAluCombinerPass()); 109 addPass(createLanaiSetflagAluCombinerPass()); 110 } 111