1 //===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Lanai target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "LanaiTargetMachine.h" 15 16 #include "Lanai.h" 17 #include "LanaiTargetObjectFile.h" 18 #include "LanaiTargetTransformInfo.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/CodeGen/Passes.h" 21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 22 #include "llvm/CodeGen/TargetPassConfig.h" 23 #include "llvm/Support/FormattedStream.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Target/TargetOptions.h" 26 27 using namespace llvm; 28 29 namespace llvm { 30 void initializeLanaiMemAluCombinerPass(PassRegistry &); 31 } // namespace llvm 32 33 extern "C" void LLVMInitializeLanaiTarget() { 34 // Register the target. 35 RegisterTargetMachine<LanaiTargetMachine> registered_target( 36 getTheLanaiTarget()); 37 } 38 39 static std::string computeDataLayout() { 40 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp) 41 return "E" // Big endian 42 "-m:e" // ELF name manging 43 "-p:32:32" // 32-bit pointers, 32 bit aligned 44 "-i64:64" // 64 bit integers, 64 bit aligned 45 "-a:0:32" // 32 bit alignment of objects of aggregate type 46 "-n32" // 32 bit native integer width 47 "-S64"; // 64 bit natural stack alignment 48 } 49 50 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 51 if (!RM.hasValue()) 52 return Reloc::PIC_; 53 return *RM; 54 } 55 56 LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT, 57 StringRef Cpu, StringRef FeatureString, 58 const TargetOptions &Options, 59 Optional<Reloc::Model> RM, 60 CodeModel::Model CodeModel, 61 CodeGenOpt::Level OptLevel) 62 : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, 63 getEffectiveRelocModel(RM), CodeModel, OptLevel), 64 Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel), 65 TLOF(new LanaiTargetObjectFile()) { 66 initAsmInfo(); 67 } 68 69 TargetIRAnalysis LanaiTargetMachine::getTargetIRAnalysis() { 70 return TargetIRAnalysis([this](const Function &F) { 71 return TargetTransformInfo(LanaiTTIImpl(this, F)); 72 }); 73 } 74 75 namespace { 76 // Lanai Code Generator Pass Configuration Options. 77 class LanaiPassConfig : public TargetPassConfig { 78 public: 79 LanaiPassConfig(LanaiTargetMachine *TM, PassManagerBase *PassManager) 80 : TargetPassConfig(TM, *PassManager) {} 81 82 LanaiTargetMachine &getLanaiTargetMachine() const { 83 return getTM<LanaiTargetMachine>(); 84 } 85 86 bool addInstSelector() override; 87 void addPreSched2() override; 88 void addPreEmitPass() override; 89 }; 90 } // namespace 91 92 TargetPassConfig * 93 LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) { 94 return new LanaiPassConfig(this, &PassManager); 95 } 96 97 // Install an instruction selector pass. 98 bool LanaiPassConfig::addInstSelector() { 99 addPass(createLanaiISelDag(getLanaiTargetMachine())); 100 return false; 101 } 102 103 // Implemented by targets that want to run passes immediately before 104 // machine code is emitted. 105 void LanaiPassConfig::addPreEmitPass() { 106 addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine())); 107 } 108 109 // Run passes after prolog-epilog insertion and before the second instruction 110 // scheduling pass. 111 void LanaiPassConfig::addPreSched2() { 112 addPass(createLanaiMemAluCombinerPass()); 113 } 114