1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonMCInstrInfo.h"
15 
16 #include "Hexagon.h"
17 #include "HexagonBaseInfo.h"
18 #include "HexagonMCChecker.h"
19 
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 
25 namespace llvm {
26 void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
27                                      MCContext &Context) {
28   MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
29 }
30 
31 void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
32                                           MCInstrInfo const &MCII, MCInst &MCB,
33                                           MCInst const &MCI) {
34   assert(HexagonMCInstrInfo::isBundle(MCB));
35   MCOperand const &exOp =
36       MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
37 
38   // Create the extender.
39   MCInst *XMCI =
40       new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
41 
42   MCB.addOperand(MCOperand::createInst(XMCI));
43 }
44 
45 iterator_range<MCInst::const_iterator>
46 HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
47   assert(isBundle(MCI));
48   return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
49 }
50 
51 size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
52   if (HexagonMCInstrInfo::isBundle(MCI))
53     return (MCI.size() - bundleInstructionsOffset);
54   else
55     return (1);
56 }
57 
58 bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
59                                             MCSubtargetInfo const &STI,
60                                             MCContext &Context, MCInst &MCB,
61                                             HexagonMCChecker *Check) {
62   // Examine the packet and convert pairs of instructions to compound
63   // instructions when possible.
64   if (!HexagonDisableCompound)
65     HexagonMCInstrInfo::tryCompound(MCII, Context, MCB);
66   // Check the bundle for errors.
67   bool CheckOk = Check ? Check->check() : true;
68   if (!CheckOk)
69     return false;
70   HexagonMCShuffle(MCII, STI, MCB);
71   // Examine the packet and convert pairs of instructions to duplex
72   // instructions when possible.
73   MCInst InstBundlePreDuplex = MCInst(MCB);
74   if (!HexagonDisableDuplex) {
75     SmallVector<DuplexCandidate, 8> possibleDuplexes;
76     possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB);
77     HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes);
78   }
79   // Examines packet and pad the packet, if needed, when an
80   // end-loop is in the bundle.
81   HexagonMCInstrInfo::padEndloop(Context, MCB);
82   // If compounding and duplexing didn't reduce the size below
83   // 4 or less we have a packet that is too big.
84   if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE)
85     return false;
86   HexagonMCShuffle(MCII, STI, MCB);
87   return true;
88 }
89 
90 void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII,
91                                        MCContext &Context, MCInst &MCI) {
92   assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
93          HexagonMCInstrInfo::isExtended(MCII, MCI));
94   MCOperand &exOp =
95       MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
96   // If the extended value is a constant, then use it for the extended and
97   // for the extender instructions, masking off the lower 6 bits and
98   // including the assumed bits.
99   int64_t Value;
100   if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
101     unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
102     exOp.setExpr(HexagonMCExpr::create(
103         MCConstantExpr::create((Value & 0x3f) << Shift, Context), Context));
104   }
105 }
106 
107 MCInst HexagonMCInstrInfo::createBundle() {
108   MCInst Result;
109   Result.setOpcode(Hexagon::BUNDLE);
110   Result.addOperand(MCOperand::createImm(0));
111   return Result;
112 }
113 
114 MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
115                                          MCInst const &inst0,
116                                          MCInst const &inst1) {
117   assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
118   MCInst *duplexInst = new (Context) MCInst;
119   duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
120 
121   MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
122   MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
123   duplexInst->addOperand(MCOperand::createInst(SubInst0));
124   duplexInst->addOperand(MCOperand::createInst(SubInst1));
125   return duplexInst;
126 }
127 
128 MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
129                                           MCInst const &Inst,
130                                           MCOperand const &MO) {
131   assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
132          HexagonMCInstrInfo::isExtended(MCII, Inst));
133 
134   MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
135   MCInst XMI;
136   XMI.setOpcode((Desc.isBranch() || Desc.isCall() ||
137                  HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR)
138                     ? Hexagon::A4_ext_b
139                     : Hexagon::A4_ext);
140   if (MO.isImm())
141     XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
142   else if (MO.isExpr())
143     XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
144   else
145     llvm_unreachable("invalid extendable operand");
146   return XMI;
147 }
148 
149 MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
150                                                    size_t Index) {
151   assert(Index <= bundleSize(MCB));
152   if (Index == 0)
153     return nullptr;
154   MCInst const *Inst =
155       MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
156   if (isImmext(*Inst))
157     return Inst;
158   return nullptr;
159 }
160 
161 void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
162                                         MCInstrInfo const &MCII, MCInst &MCB,
163                                         MCInst const &MCI) {
164   if (isConstExtended(MCII, MCI))
165     addConstExtender(Context, MCII, MCB, MCI);
166 }
167 
168 HexagonII::MemAccessSize
169 HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
170   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
171 
172   return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
173                                    HexagonII::MemAccesSizeMask));
174 }
175 
176 unsigned HexagonMCInstrInfo::getBitCount(MCInstrInfo const &MCII,
177                                          MCInst const &MCI) {
178   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
179   return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
180 }
181 
182 // Return constant extended operand number.
183 unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII,
184                                                 MCInst const &MCI) {
185   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
186   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
187 }
188 
189 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
190                                                MCInst const &MCI) {
191   return (MCII.get(MCI.getOpcode()));
192 }
193 
194 unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
195   using namespace Hexagon;
196   switch (Reg) {
197   default:
198     llvm_unreachable("unknown duplex register");
199   // Rs       Rss
200   case R0:
201   case D0:
202     return 0;
203   case R1:
204   case D1:
205     return 1;
206   case R2:
207   case D2:
208     return 2;
209   case R3:
210   case D3:
211     return 3;
212   case R4:
213   case D8:
214     return 4;
215   case R5:
216   case D9:
217     return 5;
218   case R6:
219   case D10:
220     return 6;
221   case R7:
222   case D11:
223     return 7;
224   case R16:
225     return 8;
226   case R17:
227     return 9;
228   case R18:
229     return 10;
230   case R19:
231     return 11;
232   case R20:
233     return 12;
234   case R21:
235     return 13;
236   case R22:
237     return 14;
238   case R23:
239     return 15;
240   }
241 }
242 
243 MCExpr const &HexagonMCInstrInfo::getExpr(MCExpr const &Expr) {
244   const auto &HExpr = cast<HexagonMCExpr>(Expr);
245   assert(HExpr.getExpr());
246   return *HExpr.getExpr();
247 }
248 
249 unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
250                                                    MCInst const &MCI) {
251   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
252   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
253 }
254 
255 MCOperand const &
256 HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
257                                          MCInst const &MCI) {
258   unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
259   MCOperand const &MO = MCI.getOperand(O);
260 
261   assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
262           HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
263          (MO.isImm() || MO.isExpr()));
264   return (MO);
265 }
266 
267 unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
268                                                 MCInst const &MCI) {
269   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
270   return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
271 }
272 
273 unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
274                                            MCInst const &MCI) {
275   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
276   return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
277 }
278 
279 // Return the max value that a constant extendable operand can have
280 // without being extended.
281 int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
282                                     MCInst const &MCI) {
283   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
284   unsigned isSigned =
285       (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
286   unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
287 
288   if (isSigned) // if value is signed
289     return ~(-1U << (bits - 1));
290   else
291     return ~(-1U << bits);
292 }
293 
294 // Return the min value that a constant extendable operand can have
295 // without being extended.
296 int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
297                                     MCInst const &MCI) {
298   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
299   unsigned isSigned =
300       (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
301   unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
302 
303   if (isSigned) // if value is signed
304     return -1U << (bits - 1);
305   else
306     return 0;
307 }
308 
309 StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
310                                         MCInst const &MCI) {
311   return MCII.getName(MCI.getOpcode());
312 }
313 
314 unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
315                                                  MCInst const &MCI) {
316   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
317   return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
318 }
319 
320 MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
321                                                         MCInst const &MCI) {
322   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
323   unsigned const O =
324       (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
325   MCOperand const &MCO = MCI.getOperand(O);
326 
327   assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
328           HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
329          MCO.isReg());
330   return (MCO);
331 }
332 
333 /// Return the new value or the newly produced value.
334 unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
335                                                   MCInst const &MCI) {
336   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
337   return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
338 }
339 
340 MCOperand const &
341 HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
342                                         MCInst const &MCI) {
343   unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
344   MCOperand const &MCO = MCI.getOperand(O);
345 
346   assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
347           HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
348          MCO.isReg());
349   return (MCO);
350 }
351 
352 int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII,
353                                      MCInst const &MCI) {
354   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
355 
356   HexagonII::SubTarget Target = static_cast<HexagonII::SubTarget>(
357       (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask);
358 
359   switch (Target) {
360   default:
361     return Hexagon::ArchV4;
362   case HexagonII::HasV5SubT:
363     return Hexagon::ArchV5;
364   }
365 }
366 
367 // Return the Hexagon ISA class for the insn.
368 unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
369                                      MCInst const &MCI) {
370   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
371 
372   return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
373 }
374 
375 unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
376                                       MCSubtargetInfo const &STI,
377                                       MCInst const &MCI) {
378 
379   const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
380   int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
381   return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
382 }
383 
384 bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
385   if (!HexagonMCInstrInfo::isBundle(MCI))
386     return false;
387 
388   for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
389     auto MI = I.getInst();
390     if (isImmext(*MI))
391       return true;
392   }
393 
394   return false;
395 }
396 
397 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
398   return extenderForIndex(MCB, Index) != nullptr;
399 }
400 
401 // Return whether the instruction is a legal new-value producer.
402 bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
403                                      MCInst const &MCI) {
404   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
405   return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
406 }
407 
408 /// Return whether the insn produces a second value.
409 bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
410                                       MCInst const &MCI) {
411   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
412   return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
413 }
414 
415 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
416   assert(isBundle(MCB));
417   assert(Index < HEXAGON_PACKET_SIZE);
418   return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
419 }
420 
421 bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
422   auto Result = Hexagon::BUNDLE == MCI.getOpcode();
423   assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
424   return Result;
425 }
426 
427 // Return whether the insn is an actual insn.
428 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
429   return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
430           !HexagonMCInstrInfo::isPrefix(MCII, MCI) &&
431           HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP);
432 }
433 
434 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
435   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
436   return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask);
437 }
438 
439 bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
440                                     MCInst const &MCI) {
441   return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);
442 }
443 
444 bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
445   return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
446           (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
447 }
448 
449 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
450   return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
451 }
452 
453 // Return whether the instruction needs to be constant extended.
454 // 1) Always return true if the instruction has 'isExtended' flag set.
455 //
456 // isExtendable:
457 // 2) For immediate extended operands, return true only if the value is
458 //    out-of-range.
459 // 3) For global address, always return true.
460 
461 bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
462                                          MCInst const &MCI) {
463   if (HexagonMCInstrInfo::isExtended(MCII, MCI))
464     return true;
465   if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
466     return false;
467   MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
468   if (isa<HexagonMCExpr>(MO.getExpr()) &&
469       HexagonMCInstrInfo::mustExtend(*MO.getExpr()))
470     return true;
471   // Branch insns are handled as necessary by relaxation.
472   if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
473       (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
474        HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
475       (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&
476        HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
477     return false;
478   // Otherwise loop instructions and other CR insts are handled by relaxation
479   else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
480            (MCI.getOpcode() != Hexagon::C4_addipc))
481     return false;
482 
483   assert(!MO.isImm());
484   if (isa<HexagonMCExpr>(MO.getExpr()) &&
485       HexagonMCInstrInfo::mustNotExtend(*MO.getExpr()))
486     return false;
487   int64_t Value;
488   if (!MO.getExpr()->evaluateAsAbsolute(Value))
489     return true;
490   int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
491   int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
492   return (MinValue > Value || Value > MaxValue);
493 }
494 
495 bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
496                                       MCInst const &MCI) {
497   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
498   return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
499 }
500 
501 bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
502                                     MCInst const &MCI) {
503   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
504   return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
505 }
506 
507 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
508   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
509   return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
510 }
511 
512 bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
513   auto Op = MCI.getOpcode();
514   return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
515           Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
516 }
517 
518 bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
519   assert(isBundle(MCI));
520   int64_t Flags = MCI.getOperand(0).getImm();
521   return (Flags & innerLoopMask) != 0;
522 }
523 
524 bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
525   return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
526 }
527 
528 bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
529   return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
530           (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
531 }
532 
533 // Return whether the insn is a new-value consumer.
534 bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
535                                     MCInst const &MCI) {
536   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
537   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
538 }
539 
540 // Return whether the operand can be constant extended.
541 bool HexagonMCInstrInfo::isOperandExtended(MCInstrInfo const &MCII,
542                                            MCInst const &MCI,
543                                            unsigned short OperandNum) {
544   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
545   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
546          OperandNum;
547 }
548 
549 bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
550   assert(isBundle(MCI));
551   int64_t Flags = MCI.getOperand(0).getImm();
552   return (Flags & outerLoopMask) != 0;
553 }
554 
555 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
556                                       MCInst const &MCI) {
557   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
558   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
559 }
560 
561 bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
562                                          MCInst const &MCI) {
563   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
564   return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
565 }
566 
567 /// Return whether the insn is newly predicated.
568 bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
569                                          MCInst const &MCI) {
570   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
571   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
572 }
573 
574 bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
575                                           MCInst const &MCI) {
576   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
577   return (
578       !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
579 }
580 
581 bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
582   return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
583 }
584 
585 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
586   return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX);
587 }
588 
589 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
590   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
591   return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
592 }
593 
594 bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
595   assert(isBundle(MCI));
596   auto Flags = MCI.getOperand(0).getImm();
597   return (Flags & memReorderDisabledMask) != 0;
598 }
599 
600 bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) {
601   assert(isBundle(MCI));
602   auto Flags = MCI.getOperand(0).getImm();
603   return (Flags & memStoreReorderEnabledMask) != 0;
604 }
605 
606 bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
607   switch (MCI.getOpcode()) {
608   default:
609     return false;
610   case Hexagon::SA1_addi:
611   case Hexagon::SA1_addrx:
612   case Hexagon::SA1_addsp:
613   case Hexagon::SA1_and1:
614   case Hexagon::SA1_clrf:
615   case Hexagon::SA1_clrfnew:
616   case Hexagon::SA1_clrt:
617   case Hexagon::SA1_clrtnew:
618   case Hexagon::SA1_cmpeqi:
619   case Hexagon::SA1_combine0i:
620   case Hexagon::SA1_combine1i:
621   case Hexagon::SA1_combine2i:
622   case Hexagon::SA1_combine3i:
623   case Hexagon::SA1_combinerz:
624   case Hexagon::SA1_combinezr:
625   case Hexagon::SA1_dec:
626   case Hexagon::SA1_inc:
627   case Hexagon::SA1_seti:
628   case Hexagon::SA1_setin1:
629   case Hexagon::SA1_sxtb:
630   case Hexagon::SA1_sxth:
631   case Hexagon::SA1_tfr:
632   case Hexagon::SA1_zxtb:
633   case Hexagon::SA1_zxth:
634   case Hexagon::SL1_loadri_io:
635   case Hexagon::SL1_loadrub_io:
636   case Hexagon::SL2_deallocframe:
637   case Hexagon::SL2_jumpr31:
638   case Hexagon::SL2_jumpr31_f:
639   case Hexagon::SL2_jumpr31_fnew:
640   case Hexagon::SL2_jumpr31_t:
641   case Hexagon::SL2_jumpr31_tnew:
642   case Hexagon::SL2_loadrb_io:
643   case Hexagon::SL2_loadrd_sp:
644   case Hexagon::SL2_loadrh_io:
645   case Hexagon::SL2_loadri_sp:
646   case Hexagon::SL2_loadruh_io:
647   case Hexagon::SL2_return:
648   case Hexagon::SL2_return_f:
649   case Hexagon::SL2_return_fnew:
650   case Hexagon::SL2_return_t:
651   case Hexagon::SL2_return_tnew:
652   case Hexagon::SS1_storeb_io:
653   case Hexagon::SS1_storew_io:
654   case Hexagon::SS2_allocframe:
655   case Hexagon::SS2_storebi0:
656   case Hexagon::SS2_storebi1:
657   case Hexagon::SS2_stored_sp:
658   case Hexagon::SS2_storeh_io:
659   case Hexagon::SS2_storew_sp:
660   case Hexagon::SS2_storewi0:
661   case Hexagon::SS2_storewi1:
662     return true;
663   }
664 }
665 
666 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
667   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
668   return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
669 }
670 
671 bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII,
672                                     MCInst const &MCI) {
673   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
674   return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask);
675 }
676 
677 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
678   if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
679       (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
680     return true;
681   return false;
682 }
683 
684 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
685   auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
686                   << 8;
687   if (MCI.size() <= Index)
688     return Sentinal;
689   MCOperand const &MCO = MCI.getOperand(Index);
690   if (!MCO.isExpr())
691     return Sentinal;
692   int64_t Value;
693   if (!MCO.getExpr()->evaluateAsAbsolute(Value))
694     return Sentinal;
695   return Value;
696 }
697 
698 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
699   HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
700   HExpr.setMustExtend(Val);
701 }
702 
703 bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) {
704   HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
705   return HExpr.mustExtend();
706 }
707 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
708   HexagonMCExpr &HExpr =
709       const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
710   HExpr.setMustNotExtend(Val);
711 }
712 bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
713   HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
714   return HExpr.mustNotExtend();
715 }
716 
717 void HexagonMCInstrInfo::padEndloop(MCContext &Context, MCInst &MCB) {
718   MCInst Nop;
719   Nop.setOpcode(Hexagon::A2_nop);
720   assert(isBundle(MCB));
721   while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
722           (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE)) ||
723          ((HexagonMCInstrInfo::isOuterLoop(MCB) &&
724            (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE))))
725     MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
726 }
727 
728 bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
729                                       MCInst const &MCI) {
730   if (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR)
731     return false;
732 
733   unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
734   switch (SchedClass) {
735   case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
736   case Hexagon::Sched::ALU64_tc_2_SLOT23:
737   case Hexagon::Sched::ALU64_tc_3x_SLOT23:
738   case Hexagon::Sched::M_tc_2_SLOT23:
739   case Hexagon::Sched::M_tc_3x_SLOT23:
740   case Hexagon::Sched::S_2op_tc_2_SLOT23:
741   case Hexagon::Sched::S_3op_tc_2_SLOT23:
742   case Hexagon::Sched::S_3op_tc_3x_SLOT23:
743     return true;
744   }
745   return false;
746 }
747 
748 void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
749                                        DuplexCandidate Candidate) {
750   assert(Candidate.packetIndexI < MCB.size());
751   assert(Candidate.packetIndexJ < MCB.size());
752   assert(isBundle(MCB));
753   MCInst *Duplex =
754       deriveDuplex(Context, Candidate.iClass,
755                    *MCB.getOperand(Candidate.packetIndexJ).getInst(),
756                    *MCB.getOperand(Candidate.packetIndexI).getInst());
757   assert(Duplex != nullptr);
758   MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
759   MCB.erase(MCB.begin() + Candidate.packetIndexJ);
760 }
761 
762 void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
763   assert(isBundle(MCI));
764   MCOperand &Operand = MCI.getOperand(0);
765   Operand.setImm(Operand.getImm() | innerLoopMask);
766 }
767 
768 void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
769   assert(isBundle(MCI));
770   MCOperand &Operand = MCI.getOperand(0);
771   Operand.setImm(Operand.getImm() | memReorderDisabledMask);
772   assert(isMemReorderDisabled(MCI));
773 }
774 
775 void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {
776   assert(isBundle(MCI));
777   MCOperand &Operand = MCI.getOperand(0);
778   Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
779   assert(isMemStoreReorderEnabled(MCI));
780 }
781 void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) {
782   HexagonMCExpr &HExpr =
783       const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
784   HExpr.setS23_2_reloc(Val);
785 }
786 bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) {
787   HexagonMCExpr const &HExpr = *llvm::cast<HexagonMCExpr>(&Expr);
788   return HExpr.s23_2_reloc();
789 }
790 
791 void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
792   assert(isBundle(MCI));
793   MCOperand &Operand = MCI.getOperand(0);
794   Operand.setImm(Operand.getImm() | outerLoopMask);
795 }
796 
797 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
798                                             unsigned Producer,
799                                             unsigned Producer2) {
800   // If we're a single vector consumer of a double producer, set subreg bit
801   // based on if we're accessing the lower or upper register component
802   if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
803     if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
804       return (Consumer - Hexagon::V0) & 0x1;
805   if (Consumer == Producer2)
806     return 0x1;
807   return 0;
808 }
809 }
810