1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Hexagon.h" 11 #include "MCTargetDesc/HexagonBaseInfo.h" 12 #include "MCTargetDesc/HexagonFixupKinds.h" 13 #include "MCTargetDesc/HexagonMCCodeEmitter.h" 14 #include "MCTargetDesc/HexagonMCInstrInfo.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/MC/MCCodeEmitter.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/EndianStream.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 #define DEBUG_TYPE "mccodeemitter" 29 30 using namespace llvm; 31 using namespace Hexagon; 32 33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 34 35 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, 36 MCContext &aMCT) 37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)), 38 Extended(new bool(false)), CurrentBundle(new MCInst const *) {} 39 40 uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last, 41 MCInst const &MCB, 42 MCInst const &MCI) const { 43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); 44 if (Instruction == 0) { 45 if (HexagonMCInstrInfo::isInnerLoop(MCB)) { 46 assert(!Duplex); 47 assert(Instruction != Last); 48 return HexagonII::INST_PARSE_LOOP_END; 49 } 50 } 51 if (Instruction == 1) { 52 if (HexagonMCInstrInfo::isOuterLoop(MCB)) { 53 assert(!Duplex); 54 assert(Instruction != Last); 55 return HexagonII::INST_PARSE_LOOP_END; 56 } 57 } 58 if (Duplex) { 59 assert(Instruction == Last); 60 return HexagonII::INST_PARSE_DUPLEX; 61 } 62 if(Instruction == Last) 63 return HexagonII::INST_PARSE_PACKET_END; 64 return HexagonII::INST_PARSE_NOT_END; 65 } 66 67 void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, 68 SmallVectorImpl<MCFixup> &Fixups, 69 MCSubtargetInfo const &STI) const { 70 MCInst &HMB = const_cast<MCInst &>(MI); 71 72 assert(HexagonMCInstrInfo::isBundle(HMB)); 73 DEBUG(dbgs() << "Encoding bundle\n";); 74 *Addend = 0; 75 *Extended = false; 76 *CurrentBundle = &MI; 77 size_t Instruction = 0; 78 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1; 79 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) { 80 MCInst &HMI = const_cast<MCInst &>(*I.getInst()); 81 EncodeSingleInstruction(HMI, OS, Fixups, STI, 82 parseBits(Instruction, Last, HMB, HMI), 83 Instruction); 84 *Extended = HexagonMCInstrInfo::isImmext(HMI); 85 *Addend += HEXAGON_INSTR_SIZE; 86 ++Instruction; 87 } 88 return; 89 } 90 91 /// EncodeSingleInstruction - Emit a single 92 void HexagonMCCodeEmitter::EncodeSingleInstruction( 93 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, 94 const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const { 95 MCInst HMB = MI; 96 assert(!HexagonMCInstrInfo::isBundle(HMB)); 97 uint64_t Binary; 98 99 // Compound instructions are limited to using registers 0-7 and 16-23 100 // and here we make a map 16-23 to 8-15 so they can be correctly encoded. 101 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10, 102 Hexagon::R11, Hexagon::R12, Hexagon::R13, 103 Hexagon::R14, Hexagon::R15}; 104 105 // Pseudo instructions don't get encoded and shouldn't be here 106 // in the first place! 107 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() && 108 "pseudo-instruction found"); 109 DEBUG(dbgs() << "Encoding insn" 110 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" 111 "\n"); 112 113 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { 114 for (unsigned i = 0; i < HMB.getNumOperands(); ++i) 115 if (HMB.getOperand(i).isReg()) { 116 unsigned Reg = 117 MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg()); 118 if ((Reg <= 23) && (Reg >= 16)) 119 HMB.getOperand(i).setReg(RegMap[Reg - 16]); 120 } 121 } 122 123 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) { 124 // Calculate the new value distance to the associated producer 125 MCOperand &MCO = 126 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB)); 127 unsigned SOffset = 0; 128 unsigned Register = MCO.getReg(); 129 unsigned Register1; 130 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 131 auto i = Instructions.begin() + Index - 1; 132 for (;; --i) { 133 assert(i != Instructions.begin() - 1 && "Couldn't find producer"); 134 MCInst const &Inst = *i->getInst(); 135 if (HexagonMCInstrInfo::isImmext(Inst)) 136 continue; 137 ++SOffset; 138 Register1 = 139 HexagonMCInstrInfo::hasNewValue(MCII, Inst) 140 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() 141 : static_cast<unsigned>(Hexagon::NoRegister); 142 if (Register != Register1) 143 // This isn't the register we're looking for 144 continue; 145 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) 146 // Producer is unpredicated 147 break; 148 assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) && 149 "Unpredicated consumer depending on predicated producer"); 150 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == 151 HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB)) 152 // Producer predicate sense matched ours 153 break; 154 } 155 // Hexagon PRM 10.11 Construct Nt from distance 156 unsigned Offset = SOffset; 157 Offset <<= 1; 158 MCO.setReg(Offset + Hexagon::R0); 159 } 160 161 Binary = getBinaryCodeForInstr(HMB, Fixups, STI); 162 // Check for unimplemented instructions. Immediate extenders 163 // are encoded as zero, so they need to be accounted for. 164 if ((!Binary) && 165 ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) && 166 (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) && 167 (HMB.getOpcode() != A4_ext_g))) { 168 // Use a A2_nop for unimplemented instructions. 169 DEBUG(dbgs() << "Unimplemented inst: " 170 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" 171 "\n"); 172 llvm_unreachable("Unimplemented Instruction"); 173 } 174 Binary |= Parse; 175 176 // if we need to emit a duplexed instruction 177 if (HMB.getOpcode() >= Hexagon::DuplexIClass0 && 178 HMB.getOpcode() <= Hexagon::DuplexIClassF) { 179 assert(Parse == HexagonII::INST_PARSE_DUPLEX && 180 "Emitting duplex without duplex parse bits"); 181 unsigned dupIClass; 182 switch (HMB.getOpcode()) { 183 case Hexagon::DuplexIClass0: 184 dupIClass = 0; 185 break; 186 case Hexagon::DuplexIClass1: 187 dupIClass = 1; 188 break; 189 case Hexagon::DuplexIClass2: 190 dupIClass = 2; 191 break; 192 case Hexagon::DuplexIClass3: 193 dupIClass = 3; 194 break; 195 case Hexagon::DuplexIClass4: 196 dupIClass = 4; 197 break; 198 case Hexagon::DuplexIClass5: 199 dupIClass = 5; 200 break; 201 case Hexagon::DuplexIClass6: 202 dupIClass = 6; 203 break; 204 case Hexagon::DuplexIClass7: 205 dupIClass = 7; 206 break; 207 case Hexagon::DuplexIClass8: 208 dupIClass = 8; 209 break; 210 case Hexagon::DuplexIClass9: 211 dupIClass = 9; 212 break; 213 case Hexagon::DuplexIClassA: 214 dupIClass = 10; 215 break; 216 case Hexagon::DuplexIClassB: 217 dupIClass = 11; 218 break; 219 case Hexagon::DuplexIClassC: 220 dupIClass = 12; 221 break; 222 case Hexagon::DuplexIClassD: 223 dupIClass = 13; 224 break; 225 case Hexagon::DuplexIClassE: 226 dupIClass = 14; 227 break; 228 case Hexagon::DuplexIClassF: 229 dupIClass = 15; 230 break; 231 default: 232 llvm_unreachable("Unimplemented DuplexIClass"); 233 break; 234 } 235 // 29 is the bit position. 236 // 0b1110 =0xE bits are masked off and down shifted by 1 bit. 237 // Last bit is moved to bit position 13 238 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13); 239 240 const MCInst *subInst0 = HMB.getOperand(0).getInst(); 241 const MCInst *subInst1 = HMB.getOperand(1).getInst(); 242 243 // get subinstruction slot 0 244 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI); 245 // get subinstruction slot 1 246 unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI); 247 248 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16); 249 } 250 support::endian::Writer<support::little>(OS).write<uint32_t>(Binary); 251 ++MCNumEmitted; 252 } 253 254 namespace { 255 void raise_relocation_error(unsigned bits, unsigned kind) { 256 std::string Text; 257 { 258 llvm::raw_string_ostream Stream(Text); 259 Stream << "Unrecognized relocation combination bits: " << bits 260 << " kind: " << kind; 261 } 262 report_fatal_error(Text); 263 } 264 } 265 266 /// getFixupNoBits - Some insns are not extended and thus have no 267 /// bits. These cases require a more brute force method for determining 268 /// the correct relocation. 269 namespace { 270 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, 271 const MCOperand &MO, 272 const MCSymbolRefExpr::VariantKind kind) { 273 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 274 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI); 275 276 if (insnType == HexagonII::TypePREFIX) { 277 switch (kind) { 278 case MCSymbolRefExpr::VK_GOTREL: 279 return Hexagon::fixup_Hexagon_GOTREL_32_6_X; 280 case MCSymbolRefExpr::VK_GOT: 281 return Hexagon::fixup_Hexagon_GOT_32_6_X; 282 case MCSymbolRefExpr::VK_TPREL: 283 return Hexagon::fixup_Hexagon_TPREL_32_6_X; 284 case MCSymbolRefExpr::VK_DTPREL: 285 return Hexagon::fixup_Hexagon_DTPREL_32_6_X; 286 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 287 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X; 288 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 289 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X; 290 case MCSymbolRefExpr::VK_Hexagon_IE: 291 return Hexagon::fixup_Hexagon_IE_32_6_X; 292 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 293 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X; 294 case MCSymbolRefExpr::VK_Hexagon_PCREL: 295 case MCSymbolRefExpr::VK_None: 296 if (MCID.isBranch()) 297 return Hexagon::fixup_Hexagon_B32_PCREL_X; 298 else 299 return Hexagon::fixup_Hexagon_32_6_X; 300 default: 301 raise_relocation_error(0, kind); 302 } 303 } else if (MCID.isBranch()) 304 return Hexagon::fixup_Hexagon_B13_PCREL; 305 306 switch (MCID.getOpcode()) { 307 case Hexagon::HI: 308 case Hexagon::A2_tfrih: 309 switch (kind) { 310 case MCSymbolRefExpr::VK_GOT: 311 return Hexagon::fixup_Hexagon_GOT_HI16; 312 case MCSymbolRefExpr::VK_GOTREL: 313 return Hexagon::fixup_Hexagon_GOTREL_HI16; 314 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 315 return Hexagon::fixup_Hexagon_GD_GOT_HI16; 316 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 317 return Hexagon::fixup_Hexagon_LD_GOT_HI16; 318 case MCSymbolRefExpr::VK_Hexagon_IE: 319 return Hexagon::fixup_Hexagon_IE_HI16; 320 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 321 return Hexagon::fixup_Hexagon_IE_GOT_HI16; 322 case MCSymbolRefExpr::VK_TPREL: 323 return Hexagon::fixup_Hexagon_TPREL_HI16; 324 case MCSymbolRefExpr::VK_DTPREL: 325 return Hexagon::fixup_Hexagon_DTPREL_HI16; 326 case MCSymbolRefExpr::VK_None: 327 return Hexagon::fixup_Hexagon_HI16; 328 default: 329 raise_relocation_error(0, kind); 330 } 331 332 case Hexagon::LO: 333 case Hexagon::A2_tfril: 334 switch (kind) { 335 case MCSymbolRefExpr::VK_GOT: 336 return Hexagon::fixup_Hexagon_GOT_LO16; 337 case MCSymbolRefExpr::VK_GOTREL: 338 return Hexagon::fixup_Hexagon_GOTREL_LO16; 339 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 340 return Hexagon::fixup_Hexagon_GD_GOT_LO16; 341 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 342 return Hexagon::fixup_Hexagon_LD_GOT_LO16; 343 case MCSymbolRefExpr::VK_Hexagon_IE: 344 return Hexagon::fixup_Hexagon_IE_LO16; 345 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 346 return Hexagon::fixup_Hexagon_IE_GOT_LO16; 347 case MCSymbolRefExpr::VK_TPREL: 348 return Hexagon::fixup_Hexagon_TPREL_LO16; 349 case MCSymbolRefExpr::VK_DTPREL: 350 return Hexagon::fixup_Hexagon_DTPREL_LO16; 351 case MCSymbolRefExpr::VK_None: 352 return Hexagon::fixup_Hexagon_LO16; 353 default: 354 raise_relocation_error(0, kind); 355 } 356 357 // The only relocs left should be GP relative: 358 default: 359 if (MCID.mayStore() || MCID.mayLoad()) { 360 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; 361 ++ImpUses) { 362 if (*ImpUses != Hexagon::GP) 363 continue; 364 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) { 365 case HexagonII::MemAccessSize::ByteAccess: 366 return fixup_Hexagon_GPREL16_0; 367 case HexagonII::MemAccessSize::HalfWordAccess: 368 return fixup_Hexagon_GPREL16_1; 369 case HexagonII::MemAccessSize::WordAccess: 370 return fixup_Hexagon_GPREL16_2; 371 case HexagonII::MemAccessSize::DoubleWordAccess: 372 return fixup_Hexagon_GPREL16_3; 373 default: 374 raise_relocation_error(0, kind); 375 } 376 } 377 } 378 raise_relocation_error(0, kind); 379 } 380 llvm_unreachable("Relocation exit not taken"); 381 } 382 } 383 384 namespace llvm { 385 extern const MCInstrDesc HexagonInsts[]; 386 } 387 388 namespace { 389 bool isPCRel (unsigned Kind) { 390 switch(Kind){ 391 case fixup_Hexagon_B22_PCREL: 392 case fixup_Hexagon_B15_PCREL: 393 case fixup_Hexagon_B7_PCREL: 394 case fixup_Hexagon_B13_PCREL: 395 case fixup_Hexagon_B9_PCREL: 396 case fixup_Hexagon_B32_PCREL_X: 397 case fixup_Hexagon_B22_PCREL_X: 398 case fixup_Hexagon_B15_PCREL_X: 399 case fixup_Hexagon_B13_PCREL_X: 400 case fixup_Hexagon_B9_PCREL_X: 401 case fixup_Hexagon_B7_PCREL_X: 402 case fixup_Hexagon_32_PCREL: 403 case fixup_Hexagon_PLT_B22_PCREL: 404 case fixup_Hexagon_GD_PLT_B22_PCREL: 405 case fixup_Hexagon_LD_PLT_B22_PCREL: 406 case fixup_Hexagon_6_PCREL_X: 407 return true; 408 default: 409 return false; 410 } 411 } 412 } 413 414 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, 415 const MCOperand &MO, 416 const MCExpr *ME, 417 SmallVectorImpl<MCFixup> &Fixups, 418 const MCSubtargetInfo &STI) const 419 420 { 421 if (isa<HexagonMCExpr>(ME)) 422 ME = &HexagonMCInstrInfo::getExpr(*ME); 423 int64_t Value; 424 if (ME->evaluateAsAbsolute(Value)) 425 return Value; 426 assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() == MCExpr::Binary); 427 if (ME->getKind() == MCExpr::Binary) { 428 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME); 429 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI); 430 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI); 431 return 0; 432 } 433 Hexagon::Fixups FixupKind = 434 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16); 435 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME); 436 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 437 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) - 438 HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 439 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind(); 440 441 DEBUG(dbgs() << "----------------------------------------\n"); 442 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) 443 << "\n"); 444 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n"); 445 DEBUG(dbgs() << "Relocation bits: " << bits << "\n"); 446 DEBUG(dbgs() << "Addend: " << *Addend << "\n"); 447 DEBUG(dbgs() << "----------------------------------------\n"); 448 449 switch (bits) { 450 default: 451 raise_relocation_error(bits, kind); 452 case 32: 453 switch (kind) { 454 case MCSymbolRefExpr::VK_DTPREL: 455 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X 456 : Hexagon::fixup_Hexagon_DTPREL_32; 457 break; 458 case MCSymbolRefExpr::VK_GOT: 459 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X 460 : Hexagon::fixup_Hexagon_GOT_32; 461 break; 462 case MCSymbolRefExpr::VK_GOTREL: 463 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X 464 : Hexagon::fixup_Hexagon_GOTREL_32; 465 break; 466 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 467 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X 468 : Hexagon::fixup_Hexagon_GD_GOT_32; 469 break; 470 case MCSymbolRefExpr::VK_Hexagon_IE: 471 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X 472 : Hexagon::fixup_Hexagon_IE_32; 473 break; 474 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 475 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X 476 : Hexagon::fixup_Hexagon_IE_GOT_32; 477 break; 478 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 479 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X 480 : Hexagon::fixup_Hexagon_LD_GOT_32; 481 break; 482 case MCSymbolRefExpr::VK_Hexagon_PCREL: 483 FixupKind = Hexagon::fixup_Hexagon_32_PCREL; 484 break; 485 case MCSymbolRefExpr::VK_None: 486 FixupKind = 487 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32; 488 break; 489 case MCSymbolRefExpr::VK_TPREL: 490 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X 491 : Hexagon::fixup_Hexagon_TPREL_32; 492 break; 493 default: 494 raise_relocation_error(bits, kind); 495 } 496 break; 497 498 case 22: 499 switch (kind) { 500 case MCSymbolRefExpr::VK_Hexagon_GD_PLT: 501 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL; 502 break; 503 case MCSymbolRefExpr::VK_Hexagon_LD_PLT: 504 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL; 505 break; 506 case MCSymbolRefExpr::VK_None: 507 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X 508 : Hexagon::fixup_Hexagon_B22_PCREL; 509 break; 510 case MCSymbolRefExpr::VK_PLT: 511 FixupKind = Hexagon::fixup_Hexagon_PLT_B22_PCREL; 512 break; 513 default: 514 raise_relocation_error(bits, kind); 515 } 516 break; 517 518 case 16: 519 if (*Extended) { 520 switch (kind) { 521 case MCSymbolRefExpr::VK_DTPREL: 522 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X; 523 break; 524 case MCSymbolRefExpr::VK_GOT: 525 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X; 526 break; 527 case MCSymbolRefExpr::VK_GOTREL: 528 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X; 529 break; 530 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 531 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X; 532 break; 533 case MCSymbolRefExpr::VK_Hexagon_IE: 534 FixupKind = Hexagon::fixup_Hexagon_IE_16_X; 535 break; 536 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 537 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X; 538 break; 539 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 540 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X; 541 break; 542 case MCSymbolRefExpr::VK_None: 543 FixupKind = Hexagon::fixup_Hexagon_16_X; 544 break; 545 case MCSymbolRefExpr::VK_TPREL: 546 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X; 547 break; 548 default: 549 raise_relocation_error(bits, kind); 550 } 551 } else 552 switch (kind) { 553 case MCSymbolRefExpr::VK_None: { 554 if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr())) 555 FixupKind = Hexagon::fixup_Hexagon_23_REG; 556 else 557 raise_relocation_error(bits, kind); 558 break; 559 } 560 case MCSymbolRefExpr::VK_DTPREL: 561 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16; 562 break; 563 case MCSymbolRefExpr::VK_GOTREL: 564 if (MCID.getOpcode() == Hexagon::HI) 565 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16; 566 else 567 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16; 568 break; 569 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 570 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16; 571 break; 572 case MCSymbolRefExpr::VK_Hexagon_GPREL: 573 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0; 574 break; 575 case MCSymbolRefExpr::VK_Hexagon_HI16: 576 FixupKind = Hexagon::fixup_Hexagon_HI16; 577 break; 578 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 579 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16; 580 break; 581 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 582 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16; 583 break; 584 case MCSymbolRefExpr::VK_Hexagon_LO16: 585 FixupKind = Hexagon::fixup_Hexagon_LO16; 586 break; 587 case MCSymbolRefExpr::VK_TPREL: 588 FixupKind = Hexagon::fixup_Hexagon_TPREL_16; 589 break; 590 default: 591 raise_relocation_error(bits, kind); 592 } 593 break; 594 595 case 15: 596 switch (kind) { 597 case MCSymbolRefExpr::VK_None: 598 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X 599 : Hexagon::fixup_Hexagon_B15_PCREL; 600 break; 601 default: 602 raise_relocation_error(bits, kind); 603 } 604 break; 605 606 case 13: 607 switch (kind) { 608 case MCSymbolRefExpr::VK_None: 609 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL; 610 break; 611 default: 612 raise_relocation_error(bits, kind); 613 } 614 break; 615 616 case 12: 617 if (*Extended) 618 switch (kind) { 619 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26 620 case MCSymbolRefExpr::VK_GOT: 621 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X; 622 break; 623 case MCSymbolRefExpr::VK_GOTREL: 624 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X; 625 break; 626 case MCSymbolRefExpr::VK_None: 627 FixupKind = Hexagon::fixup_Hexagon_12_X; 628 break; 629 default: 630 raise_relocation_error(bits, kind); 631 } 632 else 633 raise_relocation_error(bits, kind); 634 break; 635 636 case 11: 637 if (*Extended) 638 switch (kind) { 639 case MCSymbolRefExpr::VK_DTPREL: 640 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X; 641 break; 642 case MCSymbolRefExpr::VK_GOT: 643 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X; 644 break; 645 case MCSymbolRefExpr::VK_GOTREL: 646 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X; 647 break; 648 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 649 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X; 650 break; 651 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 652 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X; 653 break; 654 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 655 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X; 656 break; 657 case MCSymbolRefExpr::VK_None: 658 FixupKind = Hexagon::fixup_Hexagon_11_X; 659 break; 660 case MCSymbolRefExpr::VK_TPREL: 661 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X; 662 break; 663 default: 664 raise_relocation_error(bits, kind); 665 } 666 else { 667 switch (kind) { 668 case MCSymbolRefExpr::VK_TPREL: 669 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X; 670 break; 671 default: 672 raise_relocation_error(bits, kind); 673 } 674 } 675 break; 676 677 case 10: 678 if (*Extended) { 679 switch (kind) { 680 case MCSymbolRefExpr::VK_None: 681 FixupKind = Hexagon::fixup_Hexagon_10_X; 682 break; 683 default: 684 raise_relocation_error(bits, kind); 685 } 686 } else 687 raise_relocation_error(bits, kind); 688 break; 689 690 case 9: 691 if (MCID.isBranch() || 692 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR)) 693 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X 694 : Hexagon::fixup_Hexagon_B9_PCREL; 695 else if (*Extended) 696 FixupKind = Hexagon::fixup_Hexagon_9_X; 697 else 698 raise_relocation_error(bits, kind); 699 break; 700 701 case 8: 702 if (*Extended) 703 FixupKind = Hexagon::fixup_Hexagon_8_X; 704 else 705 raise_relocation_error(bits, kind); 706 break; 707 708 case 7: 709 if (MCID.isBranch() || 710 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR)) 711 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X 712 : Hexagon::fixup_Hexagon_B7_PCREL; 713 else if (*Extended) 714 FixupKind = Hexagon::fixup_Hexagon_7_X; 715 else 716 raise_relocation_error(bits, kind); 717 break; 718 719 case 6: 720 if (*Extended) { 721 switch (kind) { 722 case MCSymbolRefExpr::VK_DTPREL: 723 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X; 724 break; 725 // This is part of an extender, GOT_11 is a 726 // Word32_U6 unsigned/truncated reloc. 727 case MCSymbolRefExpr::VK_GOT: 728 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X; 729 break; 730 case MCSymbolRefExpr::VK_GOTREL: 731 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X; 732 break; 733 case MCSymbolRefExpr::VK_Hexagon_PCREL: 734 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X; 735 break; 736 case MCSymbolRefExpr::VK_TPREL: 737 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X; 738 break; 739 case MCSymbolRefExpr::VK_None: 740 FixupKind = Hexagon::fixup_Hexagon_6_X; 741 break; 742 default: 743 raise_relocation_error(bits, kind); 744 } 745 } else 746 raise_relocation_error(bits, kind); 747 break; 748 749 case 0: 750 FixupKind = getFixupNoBits(MCII, MI, MO, kind); 751 break; 752 } 753 754 MCExpr const *FixupExpression = 755 (*Addend > 0 && isPCRel(FixupKind)) 756 ? MCBinaryExpr::createAdd(MO.getExpr(), 757 MCConstantExpr::create(*Addend, MCT), MCT) 758 : MO.getExpr(); 759 760 MCFixup fixup = MCFixup::create(*Addend, FixupExpression, 761 MCFixupKind(FixupKind), MI.getLoc()); 762 Fixups.push_back(fixup); 763 // All of the information is in the fixup. 764 return 0; 765 } 766 767 unsigned 768 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, 769 SmallVectorImpl<MCFixup> &Fixups, 770 MCSubtargetInfo const &STI) const { 771 assert(!MO.isImm()); 772 if (MO.isReg()) { 773 unsigned Reg = MO.getReg(); 774 if (HexagonMCInstrInfo::isSubInstruction(MI)) 775 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg); 776 switch(MI.getOpcode()){ 777 case Hexagon::A2_tfrrcr: 778 case Hexagon::A2_tfrcrr: 779 if(Reg == Hexagon::M0) 780 Reg = Hexagon::C6; 781 if(Reg == Hexagon::M1) 782 Reg = Hexagon::C7; 783 } 784 return MCT.getRegisterInfo()->getEncodingValue(Reg); 785 } 786 787 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI); 788 } 789 790 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII, 791 MCRegisterInfo const &MRI, 792 MCContext &MCT) { 793 return new HexagonMCCodeEmitter(MII, MCT); 794 } 795 796 #include "HexagonGenMCCodeEmitter.inc" 797