1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Hexagon.h" 11 #include "MCTargetDesc/HexagonBaseInfo.h" 12 #include "MCTargetDesc/HexagonFixupKinds.h" 13 #include "MCTargetDesc/HexagonMCCodeEmitter.h" 14 #include "MCTargetDesc/HexagonMCInstrInfo.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/MC/MCCodeEmitter.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/EndianStream.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 #define DEBUG_TYPE "mccodeemitter" 29 30 using namespace llvm; 31 using namespace Hexagon; 32 33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 34 35 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, 36 MCContext &aMCT) 37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)), 38 Extended(new bool(false)), CurrentBundle(new MCInst const *) {} 39 40 uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last, 41 MCInst const &MCB, 42 MCInst const &MCI) const { 43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); 44 if (Instruction == 0) { 45 if (HexagonMCInstrInfo::isInnerLoop(MCB)) { 46 assert(!Duplex); 47 assert(Instruction != Last); 48 return HexagonII::INST_PARSE_LOOP_END; 49 } 50 } 51 if (Instruction == 1) { 52 if (HexagonMCInstrInfo::isOuterLoop(MCB)) { 53 assert(!Duplex); 54 assert(Instruction != Last); 55 return HexagonII::INST_PARSE_LOOP_END; 56 } 57 } 58 if (Duplex) { 59 assert(Instruction == Last); 60 return HexagonII::INST_PARSE_DUPLEX; 61 } 62 if(Instruction == Last) 63 return HexagonII::INST_PARSE_PACKET_END; 64 return HexagonII::INST_PARSE_NOT_END; 65 } 66 67 void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, 68 SmallVectorImpl<MCFixup> &Fixups, 69 MCSubtargetInfo const &STI) const { 70 MCInst &HMB = const_cast<MCInst &>(MI); 71 72 assert(HexagonMCInstrInfo::isBundle(HMB)); 73 DEBUG(dbgs() << "Encoding bundle\n";); 74 *Addend = 0; 75 *Extended = false; 76 *CurrentBundle = &MI; 77 size_t Instruction = 0; 78 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1; 79 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) { 80 MCInst &HMI = const_cast<MCInst &>(*I.getInst()); 81 verifyInstructionPredicates(HMI, 82 computeAvailableFeatures(STI.getFeatureBits())); 83 84 EncodeSingleInstruction(HMI, OS, Fixups, STI, 85 parseBits(Instruction, Last, HMB, HMI), 86 Instruction); 87 *Extended = HexagonMCInstrInfo::isImmext(HMI); 88 *Addend += HEXAGON_INSTR_SIZE; 89 ++Instruction; 90 } 91 return; 92 } 93 94 static bool RegisterMatches(unsigned Consumer, unsigned Producer, 95 unsigned Producer2) { 96 if (Consumer == Producer) 97 return true; 98 if (Consumer == Producer2) 99 return true; 100 // Calculate if we're a single vector consumer referencing a double producer 101 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 102 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31) 103 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0); 104 return false; 105 } 106 107 /// EncodeSingleInstruction - Emit a single 108 void HexagonMCCodeEmitter::EncodeSingleInstruction( 109 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const { 111 MCInst HMB = MI; 112 assert(!HexagonMCInstrInfo::isBundle(HMB)); 113 uint64_t Binary; 114 115 // Compound instructions are limited to using registers 0-7 and 16-23 116 // and here we make a map 16-23 to 8-15 so they can be correctly encoded. 117 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10, 118 Hexagon::R11, Hexagon::R12, Hexagon::R13, 119 Hexagon::R14, Hexagon::R15}; 120 121 // Pseudo instructions don't get encoded and shouldn't be here 122 // in the first place! 123 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() && 124 "pseudo-instruction found"); 125 DEBUG(dbgs() << "Encoding insn" 126 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" 127 "\n"); 128 129 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { 130 for (unsigned i = 0; i < HMB.getNumOperands(); ++i) 131 if (HMB.getOperand(i).isReg()) { 132 unsigned Reg = 133 MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg()); 134 if ((Reg <= 23) && (Reg >= 16)) 135 HMB.getOperand(i).setReg(RegMap[Reg - 16]); 136 } 137 } 138 139 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) { 140 // Calculate the new value distance to the associated producer 141 MCOperand &MCO = 142 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB)); 143 unsigned SOffset = 0; 144 unsigned VOffset = 0; 145 unsigned Register = MCO.getReg(); 146 unsigned Register1; 147 unsigned Register2; 148 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 149 auto i = Instructions.begin() + Index - 1; 150 for (;; --i) { 151 assert(i != Instructions.begin() - 1 && "Couldn't find producer"); 152 MCInst const &Inst = *i->getInst(); 153 if (HexagonMCInstrInfo::isImmext(Inst)) 154 continue; 155 ++SOffset; 156 if (HexagonMCInstrInfo::isVector(MCII, Inst)) 157 // Vector instructions don't count scalars 158 ++VOffset; 159 Register1 = 160 HexagonMCInstrInfo::hasNewValue(MCII, Inst) 161 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() 162 : static_cast<unsigned>(Hexagon::NoRegister); 163 Register2 = 164 HexagonMCInstrInfo::hasNewValue2(MCII, Inst) 165 ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg() 166 : static_cast<unsigned>(Hexagon::NoRegister); 167 if (!RegisterMatches(Register, Register1, Register2)) 168 // This isn't the register we're looking for 169 continue; 170 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) 171 // Producer is unpredicated 172 break; 173 assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) && 174 "Unpredicated consumer depending on predicated producer"); 175 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == 176 HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB)) 177 // Producer predicate sense matched ours 178 break; 179 } 180 // Hexagon PRM 10.11 Construct Nt from distance 181 unsigned Offset = 182 HexagonMCInstrInfo::isVector(MCII, HMB) ? VOffset : SOffset; 183 Offset <<= 1; 184 Offset |= 185 HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2); 186 MCO.setReg(Offset + Hexagon::R0); 187 } 188 189 Binary = getBinaryCodeForInstr(HMB, Fixups, STI); 190 // Check for unimplemented instructions. Immediate extenders 191 // are encoded as zero, so they need to be accounted for. 192 if ((!Binary) && 193 ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) && 194 (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) && 195 (HMB.getOpcode() != A4_ext_g))) { 196 DEBUG(dbgs() << "Unimplemented inst: " 197 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" 198 "\n"); 199 llvm_unreachable("Unimplemented Instruction"); 200 } 201 Binary |= Parse; 202 203 // if we need to emit a duplexed instruction 204 if (HMB.getOpcode() >= Hexagon::DuplexIClass0 && 205 HMB.getOpcode() <= Hexagon::DuplexIClassF) { 206 assert(Parse == HexagonII::INST_PARSE_DUPLEX && 207 "Emitting duplex without duplex parse bits"); 208 unsigned dupIClass; 209 switch (HMB.getOpcode()) { 210 case Hexagon::DuplexIClass0: 211 dupIClass = 0; 212 break; 213 case Hexagon::DuplexIClass1: 214 dupIClass = 1; 215 break; 216 case Hexagon::DuplexIClass2: 217 dupIClass = 2; 218 break; 219 case Hexagon::DuplexIClass3: 220 dupIClass = 3; 221 break; 222 case Hexagon::DuplexIClass4: 223 dupIClass = 4; 224 break; 225 case Hexagon::DuplexIClass5: 226 dupIClass = 5; 227 break; 228 case Hexagon::DuplexIClass6: 229 dupIClass = 6; 230 break; 231 case Hexagon::DuplexIClass7: 232 dupIClass = 7; 233 break; 234 case Hexagon::DuplexIClass8: 235 dupIClass = 8; 236 break; 237 case Hexagon::DuplexIClass9: 238 dupIClass = 9; 239 break; 240 case Hexagon::DuplexIClassA: 241 dupIClass = 10; 242 break; 243 case Hexagon::DuplexIClassB: 244 dupIClass = 11; 245 break; 246 case Hexagon::DuplexIClassC: 247 dupIClass = 12; 248 break; 249 case Hexagon::DuplexIClassD: 250 dupIClass = 13; 251 break; 252 case Hexagon::DuplexIClassE: 253 dupIClass = 14; 254 break; 255 case Hexagon::DuplexIClassF: 256 dupIClass = 15; 257 break; 258 default: 259 llvm_unreachable("Unimplemented DuplexIClass"); 260 break; 261 } 262 // 29 is the bit position. 263 // 0b1110 =0xE bits are masked off and down shifted by 1 bit. 264 // Last bit is moved to bit position 13 265 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13); 266 267 const MCInst *subInst0 = HMB.getOperand(0).getInst(); 268 const MCInst *subInst1 = HMB.getOperand(1).getInst(); 269 270 // get subinstruction slot 0 271 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI); 272 // get subinstruction slot 1 273 unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI); 274 275 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16); 276 } 277 support::endian::Writer<support::little>(OS).write<uint32_t>(Binary); 278 ++MCNumEmitted; 279 } 280 281 namespace { 282 void raise_relocation_error(unsigned bits, unsigned kind) { 283 std::string Text; 284 { 285 llvm::raw_string_ostream Stream(Text); 286 Stream << "Unrecognized relocation combination bits: " << bits 287 << " kind: " << kind; 288 } 289 report_fatal_error(Text); 290 } 291 } 292 293 /// getFixupNoBits - Some insns are not extended and thus have no 294 /// bits. These cases require a more brute force method for determining 295 /// the correct relocation. 296 namespace { 297 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, 298 const MCOperand &MO, 299 const MCSymbolRefExpr::VariantKind kind) { 300 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 301 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI); 302 303 if (insnType == HexagonII::TypePREFIX) { 304 switch (kind) { 305 case MCSymbolRefExpr::VK_GOTREL: 306 return Hexagon::fixup_Hexagon_GOTREL_32_6_X; 307 case MCSymbolRefExpr::VK_GOT: 308 return Hexagon::fixup_Hexagon_GOT_32_6_X; 309 case MCSymbolRefExpr::VK_TPREL: 310 return Hexagon::fixup_Hexagon_TPREL_32_6_X; 311 case MCSymbolRefExpr::VK_DTPREL: 312 return Hexagon::fixup_Hexagon_DTPREL_32_6_X; 313 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 314 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X; 315 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 316 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X; 317 case MCSymbolRefExpr::VK_Hexagon_IE: 318 return Hexagon::fixup_Hexagon_IE_32_6_X; 319 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 320 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X; 321 case MCSymbolRefExpr::VK_Hexagon_PCREL: 322 case MCSymbolRefExpr::VK_None: 323 if (MCID.isBranch()) 324 return Hexagon::fixup_Hexagon_B32_PCREL_X; 325 else 326 return Hexagon::fixup_Hexagon_32_6_X; 327 default: 328 raise_relocation_error(0, kind); 329 } 330 } else if (MCID.isBranch()) 331 return Hexagon::fixup_Hexagon_B13_PCREL; 332 333 switch (MCID.getOpcode()) { 334 case Hexagon::HI: 335 case Hexagon::A2_tfrih: 336 switch (kind) { 337 case MCSymbolRefExpr::VK_GOT: 338 return Hexagon::fixup_Hexagon_GOT_HI16; 339 case MCSymbolRefExpr::VK_GOTREL: 340 return Hexagon::fixup_Hexagon_GOTREL_HI16; 341 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 342 return Hexagon::fixup_Hexagon_GD_GOT_HI16; 343 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 344 return Hexagon::fixup_Hexagon_LD_GOT_HI16; 345 case MCSymbolRefExpr::VK_Hexagon_IE: 346 return Hexagon::fixup_Hexagon_IE_HI16; 347 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 348 return Hexagon::fixup_Hexagon_IE_GOT_HI16; 349 case MCSymbolRefExpr::VK_TPREL: 350 return Hexagon::fixup_Hexagon_TPREL_HI16; 351 case MCSymbolRefExpr::VK_DTPREL: 352 return Hexagon::fixup_Hexagon_DTPREL_HI16; 353 case MCSymbolRefExpr::VK_None: 354 return Hexagon::fixup_Hexagon_HI16; 355 default: 356 raise_relocation_error(0, kind); 357 } 358 359 case Hexagon::LO: 360 case Hexagon::A2_tfril: 361 switch (kind) { 362 case MCSymbolRefExpr::VK_GOT: 363 return Hexagon::fixup_Hexagon_GOT_LO16; 364 case MCSymbolRefExpr::VK_GOTREL: 365 return Hexagon::fixup_Hexagon_GOTREL_LO16; 366 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 367 return Hexagon::fixup_Hexagon_GD_GOT_LO16; 368 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 369 return Hexagon::fixup_Hexagon_LD_GOT_LO16; 370 case MCSymbolRefExpr::VK_Hexagon_IE: 371 return Hexagon::fixup_Hexagon_IE_LO16; 372 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 373 return Hexagon::fixup_Hexagon_IE_GOT_LO16; 374 case MCSymbolRefExpr::VK_TPREL: 375 return Hexagon::fixup_Hexagon_TPREL_LO16; 376 case MCSymbolRefExpr::VK_DTPREL: 377 return Hexagon::fixup_Hexagon_DTPREL_LO16; 378 case MCSymbolRefExpr::VK_None: 379 return Hexagon::fixup_Hexagon_LO16; 380 default: 381 raise_relocation_error(0, kind); 382 } 383 384 // The only relocs left should be GP relative: 385 default: 386 if (MCID.mayStore() || MCID.mayLoad()) { 387 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; 388 ++ImpUses) { 389 if (*ImpUses != Hexagon::GP) 390 continue; 391 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) { 392 case HexagonII::MemAccessSize::ByteAccess: 393 return fixup_Hexagon_GPREL16_0; 394 case HexagonII::MemAccessSize::HalfWordAccess: 395 return fixup_Hexagon_GPREL16_1; 396 case HexagonII::MemAccessSize::WordAccess: 397 return fixup_Hexagon_GPREL16_2; 398 case HexagonII::MemAccessSize::DoubleWordAccess: 399 return fixup_Hexagon_GPREL16_3; 400 default: 401 raise_relocation_error(0, kind); 402 } 403 } 404 } 405 raise_relocation_error(0, kind); 406 } 407 llvm_unreachable("Relocation exit not taken"); 408 } 409 } 410 411 namespace llvm { 412 extern const MCInstrDesc HexagonInsts[]; 413 } 414 415 namespace { 416 bool isPCRel (unsigned Kind) { 417 switch(Kind){ 418 case fixup_Hexagon_B22_PCREL: 419 case fixup_Hexagon_B15_PCREL: 420 case fixup_Hexagon_B7_PCREL: 421 case fixup_Hexagon_B13_PCREL: 422 case fixup_Hexagon_B9_PCREL: 423 case fixup_Hexagon_B32_PCREL_X: 424 case fixup_Hexagon_B22_PCREL_X: 425 case fixup_Hexagon_B15_PCREL_X: 426 case fixup_Hexagon_B13_PCREL_X: 427 case fixup_Hexagon_B9_PCREL_X: 428 case fixup_Hexagon_B7_PCREL_X: 429 case fixup_Hexagon_32_PCREL: 430 case fixup_Hexagon_PLT_B22_PCREL: 431 case fixup_Hexagon_GD_PLT_B22_PCREL: 432 case fixup_Hexagon_LD_PLT_B22_PCREL: 433 case fixup_Hexagon_6_PCREL_X: 434 return true; 435 default: 436 return false; 437 } 438 } 439 } 440 441 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, 442 const MCOperand &MO, 443 const MCExpr *ME, 444 SmallVectorImpl<MCFixup> &Fixups, 445 const MCSubtargetInfo &STI) const 446 447 { 448 if (isa<HexagonMCExpr>(ME)) 449 ME = &HexagonMCInstrInfo::getExpr(*ME); 450 int64_t Value; 451 if (ME->evaluateAsAbsolute(Value)) 452 return Value; 453 assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() == MCExpr::Binary); 454 if (ME->getKind() == MCExpr::Binary) { 455 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME); 456 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI); 457 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI); 458 return 0; 459 } 460 Hexagon::Fixups FixupKind = 461 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16); 462 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME); 463 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 464 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) - 465 HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 466 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind(); 467 468 DEBUG(dbgs() << "----------------------------------------\n"); 469 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) 470 << "\n"); 471 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n"); 472 DEBUG(dbgs() << "Relocation bits: " << bits << "\n"); 473 DEBUG(dbgs() << "Addend: " << *Addend << "\n"); 474 DEBUG(dbgs() << "----------------------------------------\n"); 475 476 switch (bits) { 477 default: 478 raise_relocation_error(bits, kind); 479 case 32: 480 switch (kind) { 481 case MCSymbolRefExpr::VK_DTPREL: 482 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X 483 : Hexagon::fixup_Hexagon_DTPREL_32; 484 break; 485 case MCSymbolRefExpr::VK_GOT: 486 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X 487 : Hexagon::fixup_Hexagon_GOT_32; 488 break; 489 case MCSymbolRefExpr::VK_GOTREL: 490 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X 491 : Hexagon::fixup_Hexagon_GOTREL_32; 492 break; 493 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 494 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X 495 : Hexagon::fixup_Hexagon_GD_GOT_32; 496 break; 497 case MCSymbolRefExpr::VK_Hexagon_IE: 498 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X 499 : Hexagon::fixup_Hexagon_IE_32; 500 break; 501 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 502 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X 503 : Hexagon::fixup_Hexagon_IE_GOT_32; 504 break; 505 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 506 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X 507 : Hexagon::fixup_Hexagon_LD_GOT_32; 508 break; 509 case MCSymbolRefExpr::VK_Hexagon_PCREL: 510 FixupKind = Hexagon::fixup_Hexagon_32_PCREL; 511 break; 512 case MCSymbolRefExpr::VK_None: 513 FixupKind = 514 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32; 515 break; 516 case MCSymbolRefExpr::VK_TPREL: 517 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X 518 : Hexagon::fixup_Hexagon_TPREL_32; 519 break; 520 default: 521 raise_relocation_error(bits, kind); 522 } 523 break; 524 525 case 22: 526 switch (kind) { 527 case MCSymbolRefExpr::VK_Hexagon_GD_PLT: 528 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL; 529 break; 530 case MCSymbolRefExpr::VK_Hexagon_LD_PLT: 531 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL; 532 break; 533 case MCSymbolRefExpr::VK_None: 534 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X 535 : Hexagon::fixup_Hexagon_B22_PCREL; 536 break; 537 case MCSymbolRefExpr::VK_PLT: 538 FixupKind = Hexagon::fixup_Hexagon_PLT_B22_PCREL; 539 break; 540 default: 541 raise_relocation_error(bits, kind); 542 } 543 break; 544 545 case 16: 546 if (*Extended) { 547 switch (kind) { 548 case MCSymbolRefExpr::VK_DTPREL: 549 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X; 550 break; 551 case MCSymbolRefExpr::VK_GOT: 552 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X; 553 break; 554 case MCSymbolRefExpr::VK_GOTREL: 555 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X; 556 break; 557 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 558 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X; 559 break; 560 case MCSymbolRefExpr::VK_Hexagon_IE: 561 FixupKind = Hexagon::fixup_Hexagon_IE_16_X; 562 break; 563 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 564 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X; 565 break; 566 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 567 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X; 568 break; 569 case MCSymbolRefExpr::VK_None: 570 FixupKind = Hexagon::fixup_Hexagon_16_X; 571 break; 572 case MCSymbolRefExpr::VK_TPREL: 573 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X; 574 break; 575 default: 576 raise_relocation_error(bits, kind); 577 } 578 } else 579 switch (kind) { 580 case MCSymbolRefExpr::VK_None: { 581 if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr())) 582 FixupKind = Hexagon::fixup_Hexagon_23_REG; 583 else 584 raise_relocation_error(bits, kind); 585 break; 586 } 587 case MCSymbolRefExpr::VK_DTPREL: 588 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16; 589 break; 590 case MCSymbolRefExpr::VK_GOTREL: 591 if (MCID.getOpcode() == Hexagon::HI) 592 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16; 593 else 594 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16; 595 break; 596 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 597 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16; 598 break; 599 case MCSymbolRefExpr::VK_Hexagon_GPREL: 600 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0; 601 break; 602 case MCSymbolRefExpr::VK_Hexagon_HI16: 603 FixupKind = Hexagon::fixup_Hexagon_HI16; 604 break; 605 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 606 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16; 607 break; 608 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 609 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16; 610 break; 611 case MCSymbolRefExpr::VK_Hexagon_LO16: 612 FixupKind = Hexagon::fixup_Hexagon_LO16; 613 break; 614 case MCSymbolRefExpr::VK_TPREL: 615 FixupKind = Hexagon::fixup_Hexagon_TPREL_16; 616 break; 617 default: 618 raise_relocation_error(bits, kind); 619 } 620 break; 621 622 case 15: 623 switch (kind) { 624 case MCSymbolRefExpr::VK_None: 625 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X 626 : Hexagon::fixup_Hexagon_B15_PCREL; 627 break; 628 default: 629 raise_relocation_error(bits, kind); 630 } 631 break; 632 633 case 13: 634 switch (kind) { 635 case MCSymbolRefExpr::VK_None: 636 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL; 637 break; 638 default: 639 raise_relocation_error(bits, kind); 640 } 641 break; 642 643 case 12: 644 if (*Extended) 645 switch (kind) { 646 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26 647 case MCSymbolRefExpr::VK_GOT: 648 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X; 649 break; 650 case MCSymbolRefExpr::VK_GOTREL: 651 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X; 652 break; 653 case MCSymbolRefExpr::VK_None: 654 FixupKind = Hexagon::fixup_Hexagon_12_X; 655 break; 656 default: 657 raise_relocation_error(bits, kind); 658 } 659 else 660 raise_relocation_error(bits, kind); 661 break; 662 663 case 11: 664 if (*Extended) 665 switch (kind) { 666 case MCSymbolRefExpr::VK_DTPREL: 667 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X; 668 break; 669 case MCSymbolRefExpr::VK_GOT: 670 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X; 671 break; 672 case MCSymbolRefExpr::VK_GOTREL: 673 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X; 674 break; 675 case MCSymbolRefExpr::VK_Hexagon_GD_GOT: 676 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X; 677 break; 678 case MCSymbolRefExpr::VK_Hexagon_IE_GOT: 679 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X; 680 break; 681 case MCSymbolRefExpr::VK_Hexagon_LD_GOT: 682 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X; 683 break; 684 case MCSymbolRefExpr::VK_None: 685 FixupKind = Hexagon::fixup_Hexagon_11_X; 686 break; 687 case MCSymbolRefExpr::VK_TPREL: 688 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X; 689 break; 690 default: 691 raise_relocation_error(bits, kind); 692 } 693 else { 694 switch (kind) { 695 case MCSymbolRefExpr::VK_TPREL: 696 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X; 697 break; 698 default: 699 raise_relocation_error(bits, kind); 700 } 701 } 702 break; 703 704 case 10: 705 if (*Extended) { 706 switch (kind) { 707 case MCSymbolRefExpr::VK_None: 708 FixupKind = Hexagon::fixup_Hexagon_10_X; 709 break; 710 default: 711 raise_relocation_error(bits, kind); 712 } 713 } else 714 raise_relocation_error(bits, kind); 715 break; 716 717 case 9: 718 if (MCID.isBranch() || 719 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR)) 720 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X 721 : Hexagon::fixup_Hexagon_B9_PCREL; 722 else if (*Extended) 723 FixupKind = Hexagon::fixup_Hexagon_9_X; 724 else 725 raise_relocation_error(bits, kind); 726 break; 727 728 case 8: 729 if (*Extended) 730 FixupKind = Hexagon::fixup_Hexagon_8_X; 731 else 732 raise_relocation_error(bits, kind); 733 break; 734 735 case 7: 736 if (MCID.isBranch() || 737 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR)) 738 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X 739 : Hexagon::fixup_Hexagon_B7_PCREL; 740 else if (*Extended) 741 FixupKind = Hexagon::fixup_Hexagon_7_X; 742 else 743 raise_relocation_error(bits, kind); 744 break; 745 746 case 6: 747 if (*Extended) { 748 switch (kind) { 749 case MCSymbolRefExpr::VK_DTPREL: 750 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X; 751 break; 752 // This is part of an extender, GOT_11 is a 753 // Word32_U6 unsigned/truncated reloc. 754 case MCSymbolRefExpr::VK_GOT: 755 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X; 756 break; 757 case MCSymbolRefExpr::VK_GOTREL: 758 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X; 759 break; 760 case MCSymbolRefExpr::VK_Hexagon_PCREL: 761 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X; 762 break; 763 case MCSymbolRefExpr::VK_TPREL: 764 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X; 765 break; 766 case MCSymbolRefExpr::VK_None: 767 FixupKind = Hexagon::fixup_Hexagon_6_X; 768 break; 769 default: 770 raise_relocation_error(bits, kind); 771 } 772 } else 773 raise_relocation_error(bits, kind); 774 break; 775 776 case 0: 777 FixupKind = getFixupNoBits(MCII, MI, MO, kind); 778 break; 779 } 780 781 MCExpr const *FixupExpression = 782 (*Addend > 0 && isPCRel(FixupKind)) 783 ? MCBinaryExpr::createAdd(MO.getExpr(), 784 MCConstantExpr::create(*Addend, MCT), MCT) 785 : MO.getExpr(); 786 787 MCFixup fixup = MCFixup::create(*Addend, FixupExpression, 788 MCFixupKind(FixupKind), MI.getLoc()); 789 Fixups.push_back(fixup); 790 // All of the information is in the fixup. 791 return 0; 792 } 793 794 unsigned 795 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, 796 SmallVectorImpl<MCFixup> &Fixups, 797 MCSubtargetInfo const &STI) const { 798 assert(!MO.isImm()); 799 if (MO.isReg()) { 800 unsigned Reg = MO.getReg(); 801 if (HexagonMCInstrInfo::isSubInstruction(MI)) 802 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg); 803 switch(MI.getOpcode()){ 804 case Hexagon::A2_tfrrcr: 805 case Hexagon::A2_tfrcrr: 806 if(Reg == Hexagon::M0) 807 Reg = Hexagon::C6; 808 if(Reg == Hexagon::M1) 809 Reg = Hexagon::C7; 810 } 811 return MCT.getRegisterInfo()->getEncodingValue(Reg); 812 } 813 814 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI); 815 } 816 817 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII, 818 MCRegisterInfo const &MRI, 819 MCContext &MCT) { 820 return new HexagonMCCodeEmitter(MII, MCT); 821 } 822 823 #define ENABLE_INSTR_PREDICATE_VERIFIER 824 #include "HexagonGenMCCodeEmitter.inc" 825