1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Hexagon.h" 11 #include "HexagonFixupKinds.h" 12 #include "HexagonMCTargetDesc.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCInstrInfo.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCAsmLayout.h" 17 #include "llvm/MC/MCAssembler.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCFixupKindInfo.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 #include <sstream> 26 27 using namespace llvm; 28 using namespace Hexagon; 29 30 #define DEBUG_TYPE "hexagon-asm-backend" 31 32 static cl::opt<bool> DisableFixup 33 ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon")); 34 35 namespace { 36 37 class HexagonAsmBackend : public MCAsmBackend { 38 uint8_t OSABI; 39 StringRef CPU; 40 mutable uint64_t relaxedCnt; 41 std::unique_ptr <MCInstrInfo> MCII; 42 std::unique_ptr <MCInst *> RelaxTarget; 43 MCInst * Extender; 44 public: 45 HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) : 46 OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *), 47 Extender(nullptr) {} 48 49 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 50 return createHexagonELFObjectWriter(OS, OSABI, CPU); 51 } 52 53 void setExtender(MCContext &Context) const { 54 if (Extender == nullptr) 55 const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst; 56 } 57 58 MCInst *takeExtender() const { 59 assert(Extender != nullptr); 60 MCInst * Result = Extender; 61 const_cast<HexagonAsmBackend *>(this)->Extender = nullptr; 62 return Result; 63 } 64 65 unsigned getNumFixupKinds() const override { 66 return Hexagon::NumTargetFixupKinds; 67 } 68 69 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 70 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = { 71 // This table *must* be in same the order of fixup_* kinds in 72 // HexagonFixupKinds.h. 73 // 74 // namei offset bits flags 75 { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 76 { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 77 { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 78 { "fixup_Hexagon_LO16", 0, 32, 0 }, 79 { "fixup_Hexagon_HI16", 0, 32, 0 }, 80 { "fixup_Hexagon_32", 0, 32, 0 }, 81 { "fixup_Hexagon_16", 0, 32, 0 }, 82 { "fixup_Hexagon_8", 0, 32, 0 }, 83 { "fixup_Hexagon_GPREL16_0", 0, 32, 0 }, 84 { "fixup_Hexagon_GPREL16_1", 0, 32, 0 }, 85 { "fixup_Hexagon_GPREL16_2", 0, 32, 0 }, 86 { "fixup_Hexagon_GPREL16_3", 0, 32, 0 }, 87 { "fixup_Hexagon_HL16", 0, 32, 0 }, 88 { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 89 { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_Hexagon_32_6_X", 0, 32, 0 }, 92 { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 93 { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 94 { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 95 { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 96 { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 97 { "fixup_Hexagon_16_X", 0, 32, 0 }, 98 { "fixup_Hexagon_12_X", 0, 32, 0 }, 99 { "fixup_Hexagon_11_X", 0, 32, 0 }, 100 { "fixup_Hexagon_10_X", 0, 32, 0 }, 101 { "fixup_Hexagon_9_X", 0, 32, 0 }, 102 { "fixup_Hexagon_8_X", 0, 32, 0 }, 103 { "fixup_Hexagon_7_X", 0, 32, 0 }, 104 { "fixup_Hexagon_6_X", 0, 32, 0 }, 105 { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 106 { "fixup_Hexagon_COPY", 0, 32, 0 }, 107 { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 }, 108 { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 }, 109 { "fixup_Hexagon_RELATIVE", 0, 32, 0 }, 110 { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 111 { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 }, 112 { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 }, 113 { "fixup_Hexagon_GOTREL_32", 0, 32, 0 }, 114 { "fixup_Hexagon_GOT_LO16", 0, 32, 0 }, 115 { "fixup_Hexagon_GOT_HI16", 0, 32, 0 }, 116 { "fixup_Hexagon_GOT_32", 0, 32, 0 }, 117 { "fixup_Hexagon_GOT_16", 0, 32, 0 }, 118 { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 }, 119 { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 }, 120 { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 }, 121 { "fixup_Hexagon_DTPREL_32", 0, 32, 0 }, 122 { "fixup_Hexagon_DTPREL_16", 0, 32, 0 }, 123 { "fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 124 { "fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 125 { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 }, 126 { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 }, 127 { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 }, 128 { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 }, 129 { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 }, 130 { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 }, 131 { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 }, 132 { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 }, 133 { "fixup_Hexagon_IE_LO16", 0, 32, 0 }, 134 { "fixup_Hexagon_IE_HI16", 0, 32, 0 }, 135 { "fixup_Hexagon_IE_32", 0, 32, 0 }, 136 { "fixup_Hexagon_IE_16", 0, 32, 0 }, 137 { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 }, 138 { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 }, 139 { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 }, 140 { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 }, 141 { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 }, 142 { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 }, 143 { "fixup_Hexagon_TPREL_32", 0, 32, 0 }, 144 { "fixup_Hexagon_TPREL_16", 0, 32, 0 }, 145 { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 146 { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 }, 147 { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 }, 148 { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 }, 149 { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 }, 150 { "fixup_Hexagon_GOT_16_X", 0, 32, 0 }, 151 { "fixup_Hexagon_GOT_11_X", 0, 32, 0 }, 152 { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 }, 153 { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 }, 154 { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 }, 155 { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 }, 156 { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 }, 157 { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 }, 158 { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 }, 159 { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 }, 160 { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 }, 161 { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 }, 162 { "fixup_Hexagon_IE_16_X", 0, 32, 0 }, 163 { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 }, 164 { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 }, 165 { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 }, 166 { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 }, 167 { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 }, 168 { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 } 169 }; 170 171 if (Kind < FirstTargetFixupKind) 172 return MCAsmBackend::getFixupKindInfo(Kind); 173 174 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 175 "Invalid kind!"); 176 return Infos[Kind - FirstTargetFixupKind]; 177 } 178 179 /// processFixupValue - Target hook to adjust the literal value of a fixup 180 /// if necessary. IsResolved signals whether the caller believes a relocation 181 /// is needed; the target can modify the value. The default does nothing. 182 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 183 const MCFixup &Fixup, const MCFragment *DF, 184 const MCValue &Target, uint64_t &Value, 185 bool &IsResolved) override { 186 MCFixupKind Kind = Fixup.getKind(); 187 188 switch((unsigned)Kind) { 189 default: 190 llvm_unreachable("Unknown Fixup Kind!"); 191 192 case fixup_Hexagon_LO16: 193 case fixup_Hexagon_HI16: 194 case fixup_Hexagon_16: 195 case fixup_Hexagon_8: 196 case fixup_Hexagon_GPREL16_0: 197 case fixup_Hexagon_GPREL16_1: 198 case fixup_Hexagon_GPREL16_2: 199 case fixup_Hexagon_GPREL16_3: 200 case fixup_Hexagon_HL16: 201 case fixup_Hexagon_32_6_X: 202 case fixup_Hexagon_16_X: 203 case fixup_Hexagon_12_X: 204 case fixup_Hexagon_11_X: 205 case fixup_Hexagon_10_X: 206 case fixup_Hexagon_9_X: 207 case fixup_Hexagon_8_X: 208 case fixup_Hexagon_7_X: 209 case fixup_Hexagon_6_X: 210 case fixup_Hexagon_COPY: 211 case fixup_Hexagon_GLOB_DAT: 212 case fixup_Hexagon_JMP_SLOT: 213 case fixup_Hexagon_RELATIVE: 214 case fixup_Hexagon_PLT_B22_PCREL: 215 case fixup_Hexagon_GOTREL_LO16: 216 case fixup_Hexagon_GOTREL_HI16: 217 case fixup_Hexagon_GOTREL_32: 218 case fixup_Hexagon_GOT_LO16: 219 case fixup_Hexagon_GOT_HI16: 220 case fixup_Hexagon_GOT_32: 221 case fixup_Hexagon_GOT_16: 222 case fixup_Hexagon_DTPMOD_32: 223 case fixup_Hexagon_DTPREL_LO16: 224 case fixup_Hexagon_DTPREL_HI16: 225 case fixup_Hexagon_DTPREL_32: 226 case fixup_Hexagon_DTPREL_16: 227 case fixup_Hexagon_GD_PLT_B22_PCREL: 228 case fixup_Hexagon_LD_PLT_B22_PCREL: 229 case fixup_Hexagon_GD_GOT_LO16: 230 case fixup_Hexagon_GD_GOT_HI16: 231 case fixup_Hexagon_GD_GOT_32: 232 case fixup_Hexagon_GD_GOT_16: 233 case fixup_Hexagon_LD_GOT_LO16: 234 case fixup_Hexagon_LD_GOT_HI16: 235 case fixup_Hexagon_LD_GOT_32: 236 case fixup_Hexagon_LD_GOT_16: 237 case fixup_Hexagon_IE_LO16: 238 case fixup_Hexagon_IE_HI16: 239 case fixup_Hexagon_IE_32: 240 case fixup_Hexagon_IE_16: 241 case fixup_Hexagon_IE_GOT_LO16: 242 case fixup_Hexagon_IE_GOT_HI16: 243 case fixup_Hexagon_IE_GOT_32: 244 case fixup_Hexagon_IE_GOT_16: 245 case fixup_Hexagon_TPREL_LO16: 246 case fixup_Hexagon_TPREL_HI16: 247 case fixup_Hexagon_TPREL_32: 248 case fixup_Hexagon_TPREL_16: 249 case fixup_Hexagon_GOTREL_32_6_X: 250 case fixup_Hexagon_GOTREL_16_X: 251 case fixup_Hexagon_GOTREL_11_X: 252 case fixup_Hexagon_GOT_32_6_X: 253 case fixup_Hexagon_GOT_16_X: 254 case fixup_Hexagon_GOT_11_X: 255 case fixup_Hexagon_DTPREL_32_6_X: 256 case fixup_Hexagon_DTPREL_16_X: 257 case fixup_Hexagon_DTPREL_11_X: 258 case fixup_Hexagon_GD_GOT_32_6_X: 259 case fixup_Hexagon_GD_GOT_16_X: 260 case fixup_Hexagon_GD_GOT_11_X: 261 case fixup_Hexagon_LD_GOT_32_6_X: 262 case fixup_Hexagon_LD_GOT_16_X: 263 case fixup_Hexagon_LD_GOT_11_X: 264 case fixup_Hexagon_IE_32_6_X: 265 case fixup_Hexagon_IE_16_X: 266 case fixup_Hexagon_IE_GOT_32_6_X: 267 case fixup_Hexagon_IE_GOT_16_X: 268 case fixup_Hexagon_IE_GOT_11_X: 269 case fixup_Hexagon_TPREL_32_6_X: 270 case fixup_Hexagon_TPREL_16_X: 271 case fixup_Hexagon_TPREL_11_X: 272 case fixup_Hexagon_32_PCREL: 273 case fixup_Hexagon_6_PCREL_X: 274 case fixup_Hexagon_23_REG: 275 // These relocations should always have a relocation recorded 276 IsResolved = false; 277 return; 278 279 case fixup_Hexagon_B22_PCREL: 280 //IsResolved = false; 281 break; 282 283 case fixup_Hexagon_B13_PCREL: 284 case fixup_Hexagon_B13_PCREL_X: 285 case fixup_Hexagon_B32_PCREL_X: 286 case fixup_Hexagon_B22_PCREL_X: 287 case fixup_Hexagon_B15_PCREL: 288 case fixup_Hexagon_B15_PCREL_X: 289 case fixup_Hexagon_B9_PCREL: 290 case fixup_Hexagon_B9_PCREL_X: 291 case fixup_Hexagon_B7_PCREL: 292 case fixup_Hexagon_B7_PCREL_X: 293 if (DisableFixup) 294 IsResolved = false; 295 break; 296 297 case FK_Data_1: 298 case FK_Data_2: 299 case FK_Data_4: 300 case FK_PCRel_4: 301 case fixup_Hexagon_32: 302 // Leave these relocations alone as they are used for EH. 303 return; 304 } 305 } 306 307 /// getFixupKindNumBytes - The number of bytes the fixup may change. 308 static unsigned getFixupKindNumBytes(unsigned Kind) { 309 switch (Kind) { 310 default: 311 return 0; 312 313 case FK_Data_1: 314 return 1; 315 case FK_Data_2: 316 return 2; 317 case FK_Data_4: // this later gets mapped to R_HEX_32 318 case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL 319 case fixup_Hexagon_32: 320 case fixup_Hexagon_B32_PCREL_X: 321 case fixup_Hexagon_B22_PCREL: 322 case fixup_Hexagon_B22_PCREL_X: 323 case fixup_Hexagon_B15_PCREL: 324 case fixup_Hexagon_B15_PCREL_X: 325 case fixup_Hexagon_B13_PCREL: 326 case fixup_Hexagon_B13_PCREL_X: 327 case fixup_Hexagon_B9_PCREL: 328 case fixup_Hexagon_B9_PCREL_X: 329 case fixup_Hexagon_B7_PCREL: 330 case fixup_Hexagon_B7_PCREL_X: 331 return 4; 332 } 333 } 334 335 // Make up for left shift when encoding the operand. 336 static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) { 337 switch((unsigned)Kind) { 338 default: 339 break; 340 341 case fixup_Hexagon_B7_PCREL: 342 case fixup_Hexagon_B9_PCREL: 343 case fixup_Hexagon_B13_PCREL: 344 case fixup_Hexagon_B15_PCREL: 345 case fixup_Hexagon_B22_PCREL: 346 Value >>= 2; 347 break; 348 349 case fixup_Hexagon_B7_PCREL_X: 350 case fixup_Hexagon_B9_PCREL_X: 351 case fixup_Hexagon_B13_PCREL_X: 352 case fixup_Hexagon_B15_PCREL_X: 353 case fixup_Hexagon_B22_PCREL_X: 354 Value &= 0x3f; 355 break; 356 357 case fixup_Hexagon_B32_PCREL_X: 358 Value >>= 6; 359 break; 360 } 361 return (Value); 362 } 363 364 void HandleFixupError(const int bits, const int align_bits, 365 const int64_t FixupValue, const char *fixupStr) const { 366 // Error: value 1124 out of range: -1024-1023 when resolving 367 // symbol in file xprtsock.S 368 const APInt IntMin = APInt::getSignedMinValue(bits+align_bits); 369 const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits); 370 std::stringstream errStr; 371 errStr << "\nError: value " << 372 FixupValue << 373 " out of range: " << 374 IntMin.getSExtValue() << 375 "-" << 376 IntMax.getSExtValue() << 377 " when resolving " << 378 fixupStr << 379 " fixup\n"; 380 llvm_unreachable(errStr.str().c_str()); 381 } 382 383 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided 384 /// data fragment, at the offset specified by the fixup and following the 385 /// fixup kind as appropriate. 386 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 387 uint64_t FixupValue, bool IsPCRel) const override { 388 389 // When FixupValue is 0 the relocation is external and there 390 // is nothing for us to do. 391 if (!FixupValue) return; 392 393 MCFixupKind Kind = Fixup.getKind(); 394 uint64_t Value; 395 uint32_t InstMask; 396 uint32_t Reloc; 397 398 // LLVM gives us an encoded value, we have to convert it back 399 // to a real offset before we can use it. 400 uint32_t Offset = Fixup.getOffset(); 401 unsigned NumBytes = getFixupKindNumBytes(Kind); 402 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 403 char* InstAddr = Data + Offset; 404 405 Value = adjustFixupValue(Kind, FixupValue); 406 if(!Value) 407 return; 408 signed sValue = (signed)Value; 409 410 switch((unsigned)Kind) { 411 default: 412 return; 413 414 case fixup_Hexagon_B7_PCREL: 415 if (!(isIntN(7, sValue))) 416 HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL"); 417 case fixup_Hexagon_B7_PCREL_X: 418 InstMask = 0x00001f18; // Word32_B7 419 Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8 420 ((Value & 0x3) << 3); // Value 1-0 = Target 4-3 421 break; 422 423 case fixup_Hexagon_B9_PCREL: 424 if (!(isIntN(9, sValue))) 425 HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL"); 426 case fixup_Hexagon_B9_PCREL_X: 427 InstMask = 0x003000fe; // Word32_B9 428 Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20 429 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1 430 break; 431 432 // Since the existing branches that use this relocation cannot be 433 // extended, they should only be fixed up if the target is within range. 434 case fixup_Hexagon_B13_PCREL: 435 if (!(isIntN(13, sValue))) 436 HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL"); 437 case fixup_Hexagon_B13_PCREL_X: 438 InstMask = 0x00202ffe; // Word32_B13 439 Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21 440 (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13 441 ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1 442 break; 443 444 case fixup_Hexagon_B15_PCREL: 445 if (!(isIntN(15, sValue))) 446 HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL"); 447 case fixup_Hexagon_B15_PCREL_X: 448 InstMask = 0x00df20fe; // Word32_B15 449 Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22 450 (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16 451 (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13 452 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1 453 break; 454 455 case fixup_Hexagon_B22_PCREL: 456 if (!(isIntN(22, sValue))) 457 HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL"); 458 case fixup_Hexagon_B22_PCREL_X: 459 InstMask = 0x01ff3ffe; // Word32_B22 460 Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16 461 ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1 462 break; 463 464 case fixup_Hexagon_B32_PCREL_X: 465 InstMask = 0x0fff3fff; // Word32_X26 466 Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16 467 (Value & 0x3fff); // Value 13-0 = Target 13-0 468 break; 469 470 case FK_Data_1: 471 case FK_Data_2: 472 case FK_Data_4: 473 case fixup_Hexagon_32: 474 InstMask = 0xffffffff; // Word32 475 Reloc = Value; 476 break; 477 } 478 479 DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" << 480 (unsigned)Kind << ")\n"); 481 DEBUG(uint32_t OldData = 0; 482 for (unsigned i = 0; i < NumBytes; i++) 483 OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); 484 dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << 485 ": AValue=0x"; dbgs().write_hex(FixupValue) << 486 ": Offset=" << Offset << 487 ": Size=" << DataSize << 488 ": OInst=0x"; dbgs().write_hex(OldData) << 489 ": Reloc=0x"; dbgs().write_hex(Reloc);); 490 491 // For each byte of the fragment that the fixup touches, mask in the 492 // bits from the fixup value. The Value has been "split up" into the 493 // appropriate bitfields above. 494 for (unsigned i = 0; i < NumBytes; i++){ 495 InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits 496 InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc 497 } 498 499 DEBUG(uint32_t NewData = 0; 500 for (unsigned i = 0; i < NumBytes; i++) 501 NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); 502 dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); 503 } 504 505 bool isInstRelaxable(MCInst const &HMI) const { 506 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); 507 bool Relaxable = false; 508 // Branches and loop-setup insns are handled as necessary by relaxation. 509 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || 510 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == 511 HexagonII::TypeCOMPOUND && 512 MCID.isBranch()) || 513 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && 514 MCID.isBranch()) || 515 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && 516 HMI.getOpcode() != Hexagon::C4_addipc)) 517 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { 518 Relaxable = true; 519 MCOperand const &Operand = 520 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); 521 if (HexagonMCInstrInfo::mustNotExtend(*Operand.getExpr())) 522 Relaxable = false; 523 } 524 525 return Relaxable; 526 } 527 528 /// MayNeedRelaxation - Check whether the given instruction may need 529 /// relaxation. 530 /// 531 /// \param Inst - The instruction to test. 532 bool mayNeedRelaxation(MCInst const &Inst) const override { 533 assert(HexagonMCInstrInfo::isBundle(Inst)); 534 bool PreviousIsExtender = false; 535 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { 536 auto const &Inst = *I.getInst(); 537 if (!PreviousIsExtender) { 538 if (HexagonMCInstrInfo::isDuplex(*MCII, Inst)) { 539 if (isInstRelaxable(*Inst.getOperand(0).getInst()) || 540 isInstRelaxable(*Inst.getOperand(1).getInst())) 541 return true; 542 } else { 543 if (isInstRelaxable(Inst)) 544 return true; 545 } 546 } 547 PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst); 548 } 549 return false; 550 } 551 552 /// fixupNeedsRelaxation - Target specific predicate for whether a given 553 /// fixup requires the associated instruction to be relaxed. 554 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, 555 uint64_t Value, 556 const MCRelaxableFragment *DF, 557 const MCAsmLayout &Layout) const override { 558 MCInst const &MCB = DF->getInst(); 559 assert(HexagonMCInstrInfo::isBundle(MCB)); 560 561 *RelaxTarget = nullptr; 562 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction( 563 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE)); 564 bool Relaxable = isInstRelaxable(MCI); 565 if (Relaxable == false) 566 return false; 567 // If we cannot resolve the fixup value, it requires relaxation. 568 if (!Resolved) { 569 switch ((unsigned)Fixup.getKind()) { 570 case fixup_Hexagon_B22_PCREL: 571 // GetFixupCount assumes B22 won't relax 572 // Fallthrough 573 default: 574 return false; 575 break; 576 case fixup_Hexagon_B13_PCREL: 577 case fixup_Hexagon_B15_PCREL: 578 case fixup_Hexagon_B9_PCREL: 579 case fixup_Hexagon_B7_PCREL: { 580 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) { 581 ++relaxedCnt; 582 *RelaxTarget = &MCI; 583 setExtender(Layout.getAssembler().getContext()); 584 return true; 585 } else { 586 return false; 587 } 588 break; 589 } 590 } 591 } 592 593 MCFixupKind Kind = Fixup.getKind(); 594 int64_t sValue = Value; 595 int64_t maxValue; 596 597 switch ((unsigned)Kind) { 598 case fixup_Hexagon_B7_PCREL: 599 maxValue = 1 << 8; 600 break; 601 case fixup_Hexagon_B9_PCREL: 602 maxValue = 1 << 10; 603 break; 604 case fixup_Hexagon_B15_PCREL: 605 maxValue = 1 << 16; 606 break; 607 case fixup_Hexagon_B22_PCREL: 608 maxValue = 1 << 23; 609 break; 610 default: 611 maxValue = INT64_MAX; 612 break; 613 } 614 615 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1; 616 617 if (isFarAway) { 618 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) { 619 ++relaxedCnt; 620 *RelaxTarget = &MCI; 621 setExtender(Layout.getAssembler().getContext()); 622 return true; 623 } 624 } 625 626 return false; 627 } 628 629 /// Simple predicate for targets where !Resolved implies requiring relaxation 630 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 631 const MCRelaxableFragment *DF, 632 const MCAsmLayout &Layout) const override { 633 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); 634 } 635 636 void relaxInstruction(MCInst const & Inst, 637 MCInst & Res) const override { 638 assert(HexagonMCInstrInfo::isBundle(Inst) && 639 "Hexagon relaxInstruction only works on bundles"); 640 641 Res = HexagonMCInstrInfo::createBundle(); 642 // Copy the results into the bundle. 643 bool Update = false; 644 for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { 645 MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst()); 646 647 // if immediate extender needed, add it in 648 if (*RelaxTarget == &CrntHMI) { 649 Update = true; 650 assert((HexagonMCInstrInfo::bundleSize(Res) < HEXAGON_PACKET_SIZE) && 651 "No room to insert extender for relaxation"); 652 653 MCInst *HMIx = takeExtender(); 654 *HMIx = HexagonMCInstrInfo::deriveExtender( 655 *MCII, CrntHMI, 656 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI)); 657 Res.addOperand(MCOperand::createInst(HMIx)); 658 *RelaxTarget = nullptr; 659 } 660 // now copy over the original instruction(the one we may have extended) 661 Res.addOperand(MCOperand::createInst(I.getInst())); 662 } 663 (void)Update; 664 assert(Update && "Didn't find relaxation target"); 665 } 666 667 bool writeNopData(uint64_t Count, 668 MCObjectWriter * OW) const override { 669 static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP. 670 ParseIn = 0x00004000, // In packet parse-bits. 671 ParseEnd = 0x0000c000; // End of packet parse-bits. 672 673 while(Count % HEXAGON_INSTR_SIZE) { 674 DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << 675 Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); 676 --Count; 677 OW->write8(0); 678 } 679 680 while(Count) { 681 Count -= HEXAGON_INSTR_SIZE; 682 // Close the packet whenever a multiple of the maximum packet size remains 683 uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))? 684 ParseIn: ParseEnd; 685 OW->write32(Nopcode | ParseBits); 686 } 687 return true; 688 } 689 }; 690 } // end anonymous namespace 691 692 namespace llvm { 693 MCAsmBackend *createHexagonAsmBackend(Target const &T, 694 MCRegisterInfo const & /*MRI*/, 695 const Triple &TT, StringRef CPU) { 696 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 697 return new HexagonAsmBackend(T, OSABI, CPU); 698 } 699 } 700