1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Hexagon.h" 11 #include "HexagonFixupKinds.h" 12 #include "MCTargetDesc/HexagonBaseInfo.h" 13 #include "MCTargetDesc/HexagonMCChecker.h" 14 #include "MCTargetDesc/HexagonMCCodeEmitter.h" 15 #include "MCTargetDesc/HexagonMCInstrInfo.h" 16 #include "MCTargetDesc/HexagonMCShuffler.h" 17 #include "MCTargetDesc/HexagonMCTargetDesc.h" 18 #include "llvm/MC/MCAsmBackend.h" 19 #include "llvm/MC/MCAsmLayout.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCELFObjectWriter.h" 23 #include "llvm/MC/MCFixupKindInfo.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/TargetRegistry.h" 28 29 #include <sstream> 30 31 using namespace llvm; 32 using namespace Hexagon; 33 34 #define DEBUG_TYPE "hexagon-asm-backend" 35 36 static cl::opt<bool> DisableFixup 37 ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon")); 38 39 namespace { 40 41 class HexagonAsmBackend : public MCAsmBackend { 42 uint8_t OSABI; 43 StringRef CPU; 44 mutable uint64_t relaxedCnt; 45 std::unique_ptr <MCInstrInfo> MCII; 46 std::unique_ptr <MCInst *> RelaxTarget; 47 MCInst * Extender; 48 49 void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF, 50 MCInst &HMB) const { 51 SmallVector<MCFixup, 4> Fixups; 52 SmallString<256> Code; 53 raw_svector_ostream VecOS(Code); 54 E.encodeInstruction(HMB, VecOS, Fixups, RF.getSubtargetInfo()); 55 56 // Update the fragment. 57 RF.setInst(HMB); 58 RF.getContents() = Code; 59 RF.getFixups() = Fixups; 60 } 61 62 public: 63 HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI, 64 StringRef CPU) : 65 OSABI(OSABI), CPU(CPU), MCII(T.createMCInstrInfo()), 66 RelaxTarget(new MCInst *), Extender(nullptr) {} 67 68 std::unique_ptr<MCObjectWriter> 69 createObjectWriter(raw_pwrite_stream &OS) const override { 70 return createHexagonELFObjectWriter(OS, OSABI, CPU); 71 } 72 73 void setExtender(MCContext &Context) const { 74 if (Extender == nullptr) 75 const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst; 76 } 77 78 MCInst *takeExtender() const { 79 assert(Extender != nullptr); 80 MCInst * Result = Extender; 81 const_cast<HexagonAsmBackend *>(this)->Extender = nullptr; 82 return Result; 83 } 84 85 unsigned getNumFixupKinds() const override { 86 return Hexagon::NumTargetFixupKinds; 87 } 88 89 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 90 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = { 91 // This table *must* be in same the order of fixup_* kinds in 92 // HexagonFixupKinds.h. 93 // 94 // namei offset bits flags 95 { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 96 { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 97 { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 98 { "fixup_Hexagon_LO16", 0, 32, 0 }, 99 { "fixup_Hexagon_HI16", 0, 32, 0 }, 100 { "fixup_Hexagon_32", 0, 32, 0 }, 101 { "fixup_Hexagon_16", 0, 32, 0 }, 102 { "fixup_Hexagon_8", 0, 32, 0 }, 103 { "fixup_Hexagon_GPREL16_0", 0, 32, 0 }, 104 { "fixup_Hexagon_GPREL16_1", 0, 32, 0 }, 105 { "fixup_Hexagon_GPREL16_2", 0, 32, 0 }, 106 { "fixup_Hexagon_GPREL16_3", 0, 32, 0 }, 107 { "fixup_Hexagon_HL16", 0, 32, 0 }, 108 { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 109 { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 110 { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 111 { "fixup_Hexagon_32_6_X", 0, 32, 0 }, 112 { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 113 { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 114 { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 115 { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 116 { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 117 { "fixup_Hexagon_16_X", 0, 32, 0 }, 118 { "fixup_Hexagon_12_X", 0, 32, 0 }, 119 { "fixup_Hexagon_11_X", 0, 32, 0 }, 120 { "fixup_Hexagon_10_X", 0, 32, 0 }, 121 { "fixup_Hexagon_9_X", 0, 32, 0 }, 122 { "fixup_Hexagon_8_X", 0, 32, 0 }, 123 { "fixup_Hexagon_7_X", 0, 32, 0 }, 124 { "fixup_Hexagon_6_X", 0, 32, 0 }, 125 { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 126 { "fixup_Hexagon_COPY", 0, 32, 0 }, 127 { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 }, 128 { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 }, 129 { "fixup_Hexagon_RELATIVE", 0, 32, 0 }, 130 { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 131 { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 }, 132 { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 }, 133 { "fixup_Hexagon_GOTREL_32", 0, 32, 0 }, 134 { "fixup_Hexagon_GOT_LO16", 0, 32, 0 }, 135 { "fixup_Hexagon_GOT_HI16", 0, 32, 0 }, 136 { "fixup_Hexagon_GOT_32", 0, 32, 0 }, 137 { "fixup_Hexagon_GOT_16", 0, 32, 0 }, 138 { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 }, 139 { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 }, 140 { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 }, 141 { "fixup_Hexagon_DTPREL_32", 0, 32, 0 }, 142 { "fixup_Hexagon_DTPREL_16", 0, 32, 0 }, 143 { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel }, 144 { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel }, 145 { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 }, 146 { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 }, 147 { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 }, 148 { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 }, 149 { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 }, 150 { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 }, 151 { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 }, 152 { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 }, 153 { "fixup_Hexagon_IE_LO16", 0, 32, 0 }, 154 { "fixup_Hexagon_IE_HI16", 0, 32, 0 }, 155 { "fixup_Hexagon_IE_32", 0, 32, 0 }, 156 { "fixup_Hexagon_IE_16", 0, 32, 0 }, 157 { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 }, 158 { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 }, 159 { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 }, 160 { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 }, 161 { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 }, 162 { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 }, 163 { "fixup_Hexagon_TPREL_32", 0, 32, 0 }, 164 { "fixup_Hexagon_TPREL_16", 0, 32, 0 }, 165 { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 166 { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 }, 167 { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 }, 168 { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 }, 169 { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 }, 170 { "fixup_Hexagon_GOT_16_X", 0, 32, 0 }, 171 { "fixup_Hexagon_GOT_11_X", 0, 32, 0 }, 172 { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 }, 173 { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 }, 174 { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 }, 175 { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 }, 176 { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 }, 177 { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 }, 178 { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 }, 179 { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 }, 180 { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 }, 181 { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 }, 182 { "fixup_Hexagon_IE_16_X", 0, 32, 0 }, 183 { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 }, 184 { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 }, 185 { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 }, 186 { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 }, 187 { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 }, 188 { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }, 189 { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }, 190 { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }, 191 { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }, 192 { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel } 193 }; 194 195 if (Kind < FirstTargetFixupKind) 196 return MCAsmBackend::getFixupKindInfo(Kind); 197 198 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 199 "Invalid kind!"); 200 return Infos[Kind - FirstTargetFixupKind]; 201 } 202 203 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 204 const MCValue &Target) override { 205 MCFixupKind Kind = Fixup.getKind(); 206 207 switch((unsigned)Kind) { 208 default: 209 llvm_unreachable("Unknown Fixup Kind!"); 210 211 case fixup_Hexagon_LO16: 212 case fixup_Hexagon_HI16: 213 case fixup_Hexagon_16: 214 case fixup_Hexagon_8: 215 case fixup_Hexagon_GPREL16_0: 216 case fixup_Hexagon_GPREL16_1: 217 case fixup_Hexagon_GPREL16_2: 218 case fixup_Hexagon_GPREL16_3: 219 case fixup_Hexagon_HL16: 220 case fixup_Hexagon_32_6_X: 221 case fixup_Hexagon_16_X: 222 case fixup_Hexagon_12_X: 223 case fixup_Hexagon_11_X: 224 case fixup_Hexagon_10_X: 225 case fixup_Hexagon_9_X: 226 case fixup_Hexagon_8_X: 227 case fixup_Hexagon_7_X: 228 case fixup_Hexagon_6_X: 229 case fixup_Hexagon_COPY: 230 case fixup_Hexagon_GLOB_DAT: 231 case fixup_Hexagon_JMP_SLOT: 232 case fixup_Hexagon_RELATIVE: 233 case fixup_Hexagon_PLT_B22_PCREL: 234 case fixup_Hexagon_GOTREL_LO16: 235 case fixup_Hexagon_GOTREL_HI16: 236 case fixup_Hexagon_GOTREL_32: 237 case fixup_Hexagon_GOT_LO16: 238 case fixup_Hexagon_GOT_HI16: 239 case fixup_Hexagon_GOT_32: 240 case fixup_Hexagon_GOT_16: 241 case fixup_Hexagon_DTPMOD_32: 242 case fixup_Hexagon_DTPREL_LO16: 243 case fixup_Hexagon_DTPREL_HI16: 244 case fixup_Hexagon_DTPREL_32: 245 case fixup_Hexagon_DTPREL_16: 246 case fixup_Hexagon_GD_PLT_B22_PCREL: 247 case fixup_Hexagon_LD_PLT_B22_PCREL: 248 case fixup_Hexagon_GD_GOT_LO16: 249 case fixup_Hexagon_GD_GOT_HI16: 250 case fixup_Hexagon_GD_GOT_32: 251 case fixup_Hexagon_GD_GOT_16: 252 case fixup_Hexagon_LD_GOT_LO16: 253 case fixup_Hexagon_LD_GOT_HI16: 254 case fixup_Hexagon_LD_GOT_32: 255 case fixup_Hexagon_LD_GOT_16: 256 case fixup_Hexagon_IE_LO16: 257 case fixup_Hexagon_IE_HI16: 258 case fixup_Hexagon_IE_32: 259 case fixup_Hexagon_IE_16: 260 case fixup_Hexagon_IE_GOT_LO16: 261 case fixup_Hexagon_IE_GOT_HI16: 262 case fixup_Hexagon_IE_GOT_32: 263 case fixup_Hexagon_IE_GOT_16: 264 case fixup_Hexagon_TPREL_LO16: 265 case fixup_Hexagon_TPREL_HI16: 266 case fixup_Hexagon_TPREL_32: 267 case fixup_Hexagon_TPREL_16: 268 case fixup_Hexagon_GOTREL_32_6_X: 269 case fixup_Hexagon_GOTREL_16_X: 270 case fixup_Hexagon_GOTREL_11_X: 271 case fixup_Hexagon_GOT_32_6_X: 272 case fixup_Hexagon_GOT_16_X: 273 case fixup_Hexagon_GOT_11_X: 274 case fixup_Hexagon_DTPREL_32_6_X: 275 case fixup_Hexagon_DTPREL_16_X: 276 case fixup_Hexagon_DTPREL_11_X: 277 case fixup_Hexagon_GD_GOT_32_6_X: 278 case fixup_Hexagon_GD_GOT_16_X: 279 case fixup_Hexagon_GD_GOT_11_X: 280 case fixup_Hexagon_LD_GOT_32_6_X: 281 case fixup_Hexagon_LD_GOT_16_X: 282 case fixup_Hexagon_LD_GOT_11_X: 283 case fixup_Hexagon_IE_32_6_X: 284 case fixup_Hexagon_IE_16_X: 285 case fixup_Hexagon_IE_GOT_32_6_X: 286 case fixup_Hexagon_IE_GOT_16_X: 287 case fixup_Hexagon_IE_GOT_11_X: 288 case fixup_Hexagon_TPREL_32_6_X: 289 case fixup_Hexagon_TPREL_16_X: 290 case fixup_Hexagon_TPREL_11_X: 291 case fixup_Hexagon_32_PCREL: 292 case fixup_Hexagon_6_PCREL_X: 293 case fixup_Hexagon_23_REG: 294 case fixup_Hexagon_27_REG: 295 case fixup_Hexagon_GD_PLT_B22_PCREL_X: 296 case fixup_Hexagon_GD_PLT_B32_PCREL_X: 297 case fixup_Hexagon_LD_PLT_B22_PCREL_X: 298 case fixup_Hexagon_LD_PLT_B32_PCREL_X: 299 // These relocations should always have a relocation recorded 300 return true; 301 302 case fixup_Hexagon_B22_PCREL: 303 //IsResolved = false; 304 break; 305 306 case fixup_Hexagon_B13_PCREL: 307 case fixup_Hexagon_B13_PCREL_X: 308 case fixup_Hexagon_B32_PCREL_X: 309 case fixup_Hexagon_B22_PCREL_X: 310 case fixup_Hexagon_B15_PCREL: 311 case fixup_Hexagon_B15_PCREL_X: 312 case fixup_Hexagon_B9_PCREL: 313 case fixup_Hexagon_B9_PCREL_X: 314 case fixup_Hexagon_B7_PCREL: 315 case fixup_Hexagon_B7_PCREL_X: 316 if (DisableFixup) 317 return true; 318 break; 319 320 case FK_Data_1: 321 case FK_Data_2: 322 case FK_Data_4: 323 case FK_PCRel_4: 324 case fixup_Hexagon_32: 325 // Leave these relocations alone as they are used for EH. 326 return false; 327 } 328 return false; 329 } 330 331 /// getFixupKindNumBytes - The number of bytes the fixup may change. 332 static unsigned getFixupKindNumBytes(unsigned Kind) { 333 switch (Kind) { 334 default: 335 return 0; 336 337 case FK_Data_1: 338 return 1; 339 case FK_Data_2: 340 return 2; 341 case FK_Data_4: // this later gets mapped to R_HEX_32 342 case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL 343 case fixup_Hexagon_32: 344 case fixup_Hexagon_B32_PCREL_X: 345 case fixup_Hexagon_B22_PCREL: 346 case fixup_Hexagon_B22_PCREL_X: 347 case fixup_Hexagon_B15_PCREL: 348 case fixup_Hexagon_B15_PCREL_X: 349 case fixup_Hexagon_B13_PCREL: 350 case fixup_Hexagon_B13_PCREL_X: 351 case fixup_Hexagon_B9_PCREL: 352 case fixup_Hexagon_B9_PCREL_X: 353 case fixup_Hexagon_B7_PCREL: 354 case fixup_Hexagon_B7_PCREL_X: 355 case fixup_Hexagon_GD_PLT_B32_PCREL_X: 356 case fixup_Hexagon_LD_PLT_B32_PCREL_X: 357 return 4; 358 } 359 } 360 361 // Make up for left shift when encoding the operand. 362 static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) { 363 switch((unsigned)Kind) { 364 default: 365 break; 366 367 case fixup_Hexagon_B7_PCREL: 368 case fixup_Hexagon_B9_PCREL: 369 case fixup_Hexagon_B13_PCREL: 370 case fixup_Hexagon_B15_PCREL: 371 case fixup_Hexagon_B22_PCREL: 372 Value >>= 2; 373 break; 374 375 case fixup_Hexagon_B7_PCREL_X: 376 case fixup_Hexagon_B9_PCREL_X: 377 case fixup_Hexagon_B13_PCREL_X: 378 case fixup_Hexagon_B15_PCREL_X: 379 case fixup_Hexagon_B22_PCREL_X: 380 Value &= 0x3f; 381 break; 382 383 case fixup_Hexagon_B32_PCREL_X: 384 case fixup_Hexagon_GD_PLT_B32_PCREL_X: 385 case fixup_Hexagon_LD_PLT_B32_PCREL_X: 386 Value >>= 6; 387 break; 388 } 389 return (Value); 390 } 391 392 void HandleFixupError(const int bits, const int align_bits, 393 const int64_t FixupValue, const char *fixupStr) const { 394 // Error: value 1124 out of range: -1024-1023 when resolving 395 // symbol in file xprtsock.S 396 const APInt IntMin = APInt::getSignedMinValue(bits+align_bits); 397 const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits); 398 std::stringstream errStr; 399 errStr << "\nError: value " << 400 FixupValue << 401 " out of range: " << 402 IntMin.getSExtValue() << 403 "-" << 404 IntMax.getSExtValue() << 405 " when resolving " << 406 fixupStr << 407 " fixup\n"; 408 llvm_unreachable(errStr.str().c_str()); 409 } 410 411 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided 412 /// data fragment, at the offset specified by the fixup and following the 413 /// fixup kind as appropriate. 414 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 415 const MCValue &Target, MutableArrayRef<char> Data, 416 uint64_t FixupValue, bool IsResolved) const override { 417 418 // When FixupValue is 0 the relocation is external and there 419 // is nothing for us to do. 420 if (!FixupValue) return; 421 422 MCFixupKind Kind = Fixup.getKind(); 423 uint64_t Value; 424 uint32_t InstMask; 425 uint32_t Reloc; 426 427 // LLVM gives us an encoded value, we have to convert it back 428 // to a real offset before we can use it. 429 uint32_t Offset = Fixup.getOffset(); 430 unsigned NumBytes = getFixupKindNumBytes(Kind); 431 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 432 char *InstAddr = Data.data() + Offset; 433 434 Value = adjustFixupValue(Kind, FixupValue); 435 if(!Value) 436 return; 437 int sValue = (int)Value; 438 439 switch((unsigned)Kind) { 440 default: 441 return; 442 443 case fixup_Hexagon_B7_PCREL: 444 if (!(isIntN(7, sValue))) 445 HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL"); 446 LLVM_FALLTHROUGH; 447 case fixup_Hexagon_B7_PCREL_X: 448 InstMask = 0x00001f18; // Word32_B7 449 Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8 450 ((Value & 0x3) << 3); // Value 1-0 = Target 4-3 451 break; 452 453 case fixup_Hexagon_B9_PCREL: 454 if (!(isIntN(9, sValue))) 455 HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL"); 456 LLVM_FALLTHROUGH; 457 case fixup_Hexagon_B9_PCREL_X: 458 InstMask = 0x003000fe; // Word32_B9 459 Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20 460 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1 461 break; 462 463 // Since the existing branches that use this relocation cannot be 464 // extended, they should only be fixed up if the target is within range. 465 case fixup_Hexagon_B13_PCREL: 466 if (!(isIntN(13, sValue))) 467 HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL"); 468 LLVM_FALLTHROUGH; 469 case fixup_Hexagon_B13_PCREL_X: 470 InstMask = 0x00202ffe; // Word32_B13 471 Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21 472 (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13 473 ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1 474 break; 475 476 case fixup_Hexagon_B15_PCREL: 477 if (!(isIntN(15, sValue))) 478 HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL"); 479 LLVM_FALLTHROUGH; 480 case fixup_Hexagon_B15_PCREL_X: 481 InstMask = 0x00df20fe; // Word32_B15 482 Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22 483 (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16 484 (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13 485 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1 486 break; 487 488 case fixup_Hexagon_B22_PCREL: 489 if (!(isIntN(22, sValue))) 490 HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL"); 491 LLVM_FALLTHROUGH; 492 case fixup_Hexagon_B22_PCREL_X: 493 InstMask = 0x01ff3ffe; // Word32_B22 494 Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16 495 ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1 496 break; 497 498 case fixup_Hexagon_B32_PCREL_X: 499 InstMask = 0x0fff3fff; // Word32_X26 500 Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16 501 (Value & 0x3fff); // Value 13-0 = Target 13-0 502 break; 503 504 case FK_Data_1: 505 case FK_Data_2: 506 case FK_Data_4: 507 case fixup_Hexagon_32: 508 InstMask = 0xffffffff; // Word32 509 Reloc = Value; 510 break; 511 } 512 513 DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" << 514 (unsigned)Kind << ")\n"); 515 DEBUG(uint32_t OldData = 0; 516 for (unsigned i = 0; i < NumBytes; i++) 517 OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); 518 dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << 519 ": AValue=0x"; dbgs().write_hex(FixupValue) << 520 ": Offset=" << Offset << 521 ": Size=" << Data.size() << 522 ": OInst=0x"; dbgs().write_hex(OldData) << 523 ": Reloc=0x"; dbgs().write_hex(Reloc);); 524 525 // For each byte of the fragment that the fixup touches, mask in the 526 // bits from the fixup value. The Value has been "split up" into the 527 // appropriate bitfields above. 528 for (unsigned i = 0; i < NumBytes; i++){ 529 InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits 530 InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc 531 } 532 533 DEBUG(uint32_t NewData = 0; 534 for (unsigned i = 0; i < NumBytes; i++) 535 NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); 536 dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); 537 } 538 539 bool isInstRelaxable(MCInst const &HMI) const { 540 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); 541 bool Relaxable = false; 542 // Branches and loop-setup insns are handled as necessary by relaxation. 543 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || 544 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && 545 MCID.isBranch()) || 546 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ && 547 MCID.isBranch()) || 548 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && 549 HMI.getOpcode() != Hexagon::C4_addipc)) 550 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { 551 Relaxable = true; 552 MCOperand const &Operand = 553 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); 554 if (HexagonMCInstrInfo::mustNotExtend(*Operand.getExpr())) 555 Relaxable = false; 556 } 557 558 return Relaxable; 559 } 560 561 /// MayNeedRelaxation - Check whether the given instruction may need 562 /// relaxation. 563 /// 564 /// \param Inst - The instruction to test. 565 bool mayNeedRelaxation(MCInst const &Inst) const override { 566 return true; 567 } 568 569 /// fixupNeedsRelaxation - Target specific predicate for whether a given 570 /// fixup requires the associated instruction to be relaxed. 571 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, 572 uint64_t Value, 573 const MCRelaxableFragment *DF, 574 const MCAsmLayout &Layout) const override { 575 MCInst const &MCB = DF->getInst(); 576 assert(HexagonMCInstrInfo::isBundle(MCB)); 577 578 *RelaxTarget = nullptr; 579 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction( 580 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE)); 581 bool Relaxable = isInstRelaxable(MCI); 582 if (Relaxable == false) 583 return false; 584 // If we cannot resolve the fixup value, it requires relaxation. 585 if (!Resolved) { 586 switch ((unsigned)Fixup.getKind()) { 587 case fixup_Hexagon_B22_PCREL: 588 // GetFixupCount assumes B22 won't relax 589 LLVM_FALLTHROUGH; 590 default: 591 return false; 592 break; 593 case fixup_Hexagon_B13_PCREL: 594 case fixup_Hexagon_B15_PCREL: 595 case fixup_Hexagon_B9_PCREL: 596 case fixup_Hexagon_B7_PCREL: { 597 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) { 598 ++relaxedCnt; 599 *RelaxTarget = &MCI; 600 setExtender(Layout.getAssembler().getContext()); 601 return true; 602 } else { 603 return false; 604 } 605 break; 606 } 607 } 608 } 609 610 MCFixupKind Kind = Fixup.getKind(); 611 int64_t sValue = Value; 612 int64_t maxValue; 613 614 switch ((unsigned)Kind) { 615 case fixup_Hexagon_B7_PCREL: 616 maxValue = 1 << 8; 617 break; 618 case fixup_Hexagon_B9_PCREL: 619 maxValue = 1 << 10; 620 break; 621 case fixup_Hexagon_B15_PCREL: 622 maxValue = 1 << 16; 623 break; 624 case fixup_Hexagon_B22_PCREL: 625 maxValue = 1 << 23; 626 break; 627 default: 628 maxValue = INT64_MAX; 629 break; 630 } 631 632 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1; 633 634 if (isFarAway) { 635 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) { 636 ++relaxedCnt; 637 *RelaxTarget = &MCI; 638 setExtender(Layout.getAssembler().getContext()); 639 return true; 640 } 641 } 642 643 return false; 644 } 645 646 /// Simple predicate for targets where !Resolved implies requiring relaxation 647 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 648 const MCRelaxableFragment *DF, 649 const MCAsmLayout &Layout) const override { 650 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); 651 } 652 653 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 654 MCInst &Res) const override { 655 assert(HexagonMCInstrInfo::isBundle(Inst) && 656 "Hexagon relaxInstruction only works on bundles"); 657 658 Res = HexagonMCInstrInfo::createBundle(); 659 // Copy the results into the bundle. 660 bool Update = false; 661 for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { 662 MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst()); 663 664 // if immediate extender needed, add it in 665 if (*RelaxTarget == &CrntHMI) { 666 Update = true; 667 assert((HexagonMCInstrInfo::bundleSize(Res) < HEXAGON_PACKET_SIZE) && 668 "No room to insert extender for relaxation"); 669 670 MCInst *HMIx = takeExtender(); 671 *HMIx = HexagonMCInstrInfo::deriveExtender( 672 *MCII, CrntHMI, 673 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI)); 674 Res.addOperand(MCOperand::createInst(HMIx)); 675 *RelaxTarget = nullptr; 676 } 677 // now copy over the original instruction(the one we may have extended) 678 Res.addOperand(MCOperand::createInst(I.getInst())); 679 } 680 (void)Update; 681 assert(Update && "Didn't find relaxation target"); 682 } 683 684 bool writeNopData(uint64_t Count, 685 MCObjectWriter * OW) const override { 686 static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP. 687 ParseIn = 0x00004000, // In packet parse-bits. 688 ParseEnd = 0x0000c000; // End of packet parse-bits. 689 690 while(Count % HEXAGON_INSTR_SIZE) { 691 DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << 692 Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); 693 --Count; 694 OW->write8(0); 695 } 696 697 while(Count) { 698 Count -= HEXAGON_INSTR_SIZE; 699 // Close the packet whenever a multiple of the maximum packet size remains 700 uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))? 701 ParseIn: ParseEnd; 702 OW->write32(Nopcode | ParseBits); 703 } 704 return true; 705 } 706 707 void finishLayout(MCAssembler const &Asm, 708 MCAsmLayout &Layout) const override { 709 for (auto I : Layout.getSectionOrder()) { 710 auto &Fragments = I->getFragmentList(); 711 for (auto &J : Fragments) { 712 switch (J.getKind()) { 713 default: 714 break; 715 case MCFragment::FT_Align: { 716 auto Size = Asm.computeFragmentSize(Layout, J); 717 for (auto K = J.getIterator(); 718 K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) { 719 --K; 720 switch (K->getKind()) { 721 default: 722 break; 723 case MCFragment::FT_Align: { 724 // Don't pad before other alignments 725 Size = 0; 726 break; 727 } 728 case MCFragment::FT_Relaxable: { 729 MCContext &Context = Asm.getContext(); 730 auto &RF = cast<MCRelaxableFragment>(*K); 731 auto &Inst = const_cast<MCInst &>(RF.getInst()); 732 while (Size > 0 && HexagonMCInstrInfo::bundleSize(Inst) < 4) { 733 MCInst *Nop = new (Context) MCInst; 734 Nop->setOpcode(Hexagon::A2_nop); 735 Inst.addOperand(MCOperand::createInst(Nop)); 736 Size -= 4; 737 if (!HexagonMCChecker( 738 Context, *MCII, RF.getSubtargetInfo(), Inst, 739 *Context.getRegisterInfo(), false) 740 .check()) { 741 Inst.erase(Inst.end() - 1); 742 Size = 0; 743 } 744 } 745 bool Error = HexagonMCShuffle(Context, true, *MCII, 746 RF.getSubtargetInfo(), Inst); 747 //assert(!Error); 748 (void)Error; 749 ReplaceInstruction(Asm.getEmitter(), RF, Inst); 750 Layout.invalidateFragmentsFrom(&RF); 751 Size = 0; // Only look back one instruction 752 break; 753 } 754 } 755 } 756 } 757 } 758 } 759 } 760 } 761 }; // class HexagonAsmBackend 762 763 } // namespace 764 765 // MCAsmBackend 766 MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T, 767 MCRegisterInfo const & /*MRI*/, 768 const Triple &TT, StringRef CPU, 769 const MCTargetOptions &Options) { 770 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 771 772 StringRef CPUString = Hexagon_MC::selectHexagonCPU(TT, CPU); 773 return new HexagonAsmBackend(T, TT, OSABI, CPUString); 774 } 775