1 //===-- HexagonVectorPrint.cpp - Generate vector printing instructions -===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass adds the capability to generate pseudo vector/predicate register
11 // printing instructions. These pseudo instructions should be used with the
12 // simulator, NEVER on hardware.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #define DEBUG_TYPE "hexagon-vector-print"
17 
18 #include "HexagonTargetMachine.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 
21 using namespace llvm;
22 
23 static cl::opt<bool> TraceHexVectorStoresOnly("trace-hex-vector-stores-only",
24   cl::Hidden, cl::ZeroOrMore, cl::init(false),
25   cl::desc("Enables tracing of vector stores"));
26 
27 namespace llvm {
28   FunctionPass *createHexagonVectorPrint();
29   void initializeHexagonVectorPrintPass(PassRegistry&);
30 }
31 
32 
33 namespace {
34 
35 class HexagonVectorPrint : public MachineFunctionPass {
36     const HexagonSubtarget     *QST;
37     const HexagonInstrInfo     *QII;
38     const HexagonRegisterInfo  *QRI;
39 
40  public:
41     static char ID;
42     HexagonVectorPrint() : MachineFunctionPass(ID),
43       QST(0), QII(0), QRI(0) {
44       initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
45     }
46 
47     StringRef getPassName() const override {
48       return "Hexagon VectorPrint pass";
49     }
50     bool runOnMachineFunction(MachineFunction &Fn) override;
51 };
52 
53 char HexagonVectorPrint::ID = 0;
54 
55 static bool isVecReg(unsigned Reg) {
56   return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
57       || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15)
58       || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
59 }
60 
61 std::string getStringReg(unsigned R) {
62   if (R >= Hexagon::V0 && R <= Hexagon::V31) {
63     static const char* S[] = { "20", "21", "22", "23", "24", "25", "26", "27",
64                         "28", "29", "2a", "2b", "2c", "2d", "2e", "2f",
65                         "30", "31", "32", "33", "34", "35", "36", "37",
66                         "38", "39", "3a", "3b", "3c", "3d", "3e", "3f"};
67     return S[R-Hexagon::V0];
68   }
69   if (R >= Hexagon::Q0 && R <= Hexagon::Q3) {
70     static const char* S[] = { "00", "01", "02", "03"};
71     return S[R-Hexagon::Q0];
72 
73   }
74   llvm_unreachable("valid vreg");
75 }
76 
77 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg,
78                         MachineBasicBlock::instr_iterator I,
79                         const DebugLoc &DL, const HexagonInstrInfo *QII,
80                         MachineFunction &Fn) {
81 
82   std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);
83   const char *cstr = Fn.createExternalSymbolName(VDescStr);
84   unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects;
85   BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
86     .addExternalSymbol(cstr)
87     .addImm(ExtraInfo);
88 }
89 
90 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) {
91   if (MI.getNumOperands() < 1) return false;
92   // Vec load or compute.
93   if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
94     Reg = MI.getOperand(0).getReg();
95     if (isVecReg(Reg))
96       return !TraceHexVectorStoresOnly;
97   }
98   // Vec store.
99   if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
100     Reg = MI.getOperand(2).getReg();
101     if (isVecReg(Reg))
102       return true;
103   }
104   // Vec store post increment.
105   if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) {
106     Reg = MI.getOperand(3).getReg();
107     if (isVecReg(Reg))
108       return true;
109   }
110   return false;
111 }
112 
113 bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) {
114   bool Changed = false;
115   QST = &Fn.getSubtarget<HexagonSubtarget>();
116   QRI = QST->getRegisterInfo();
117   QII = QST->getInstrInfo();
118   std::vector<MachineInstr *> VecPrintList;
119   for (auto &MBB : Fn)
120     for (auto &MI : MBB) {
121       if (MI.isBundle()) {
122         MachineBasicBlock::instr_iterator MII = MI.getIterator();
123         for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) {
124           if (MII->getNumOperands() < 1)
125             continue;
126           unsigned Reg = 0;
127           if (getInstrVecReg(*MII, Reg)) {
128             VecPrintList.push_back((&*MII));
129             DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump());
130           }
131         }
132       } else {
133         unsigned Reg = 0;
134         if (getInstrVecReg(MI, Reg)) {
135           VecPrintList.push_back(&MI);
136           DEBUG(dbgs() << "Found vector reg \n"; MI.dump());
137         }
138       }
139     }
140 
141   Changed = VecPrintList.size() > 0;
142   if (!Changed)
143     return Changed;
144 
145   for (auto *I : VecPrintList) {
146     DebugLoc DL = I->getDebugLoc();
147     MachineBasicBlock *MBB = I->getParent();
148     DEBUG(dbgs() << "Evaluating V MI\n"; I->dump());
149     unsigned Reg = 0;
150     if (!getInstrVecReg(*I, Reg))
151       llvm_unreachable("Need a vector reg");
152     MachineBasicBlock::instr_iterator MII = I->getIterator();
153     if (I->isInsideBundle()) {
154       DEBUG(dbgs() << "add to end of bundle\n"; I->dump());
155       while (MBB->instr_end() != MII && MII->isInsideBundle())
156         MII++;
157     } else {
158       DEBUG(dbgs() << "add after instruction\n"; I->dump());
159       MII++;
160     }
161     if (MBB->instr_end() == MII)
162       continue;
163 
164     if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
165       DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n');
166       addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
167     } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
168       DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n');
169       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
170                   MII, DL, QII, Fn);
171       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
172                    MII, DL, QII, Fn);
173     } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) {
174       DEBUG(dbgs() << "adding dump for Q" << Reg-Hexagon::Q0 << '\n');
175       addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
176     } else
177       llvm_unreachable("Bad Vector reg");
178   }
179   return Changed;
180 }
181 
182 }
183 //===----------------------------------------------------------------------===//
184 //                         Public Constructor Functions
185 //===----------------------------------------------------------------------===//
186 INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print",
187   "Hexagon VectorPrint pass", false, false)
188 
189 FunctionPass *llvm::createHexagonVectorPrint() {
190   return new HexagonVectorPrint();
191 }
192