1 //===-- HexagonVectorPrint.cpp - Generate vector printing instructions -===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass adds the capability to generate pseudo vector/predicate register
11 // printing instructions. These pseudo instructions should be used with the
12 // simulator, NEVER on hardware.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #define DEBUG_TYPE "hexagon-vector-print"
17 
18 #include "HexagonInstrInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/Pass.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include <string>
35 #include <vector>
36 
37 using namespace llvm;
38 
39 static cl::opt<bool> TraceHexVectorStoresOnly("trace-hex-vector-stores-only",
40   cl::Hidden, cl::ZeroOrMore, cl::init(false),
41   cl::desc("Enables tracing of vector stores"));
42 
43 namespace llvm {
44 
45   FunctionPass *createHexagonVectorPrint();
46   void initializeHexagonVectorPrintPass(PassRegistry&);
47 
48 } // end namespace llvm
49 
50 namespace {
51 
52 class HexagonVectorPrint : public MachineFunctionPass {
53   const HexagonSubtarget *QST;
54   const HexagonInstrInfo *QII;
55   const HexagonRegisterInfo *QRI;
56 
57 public:
58   static char ID;
59 
60   HexagonVectorPrint()
61       : MachineFunctionPass(ID), QST(nullptr), QII(nullptr), QRI(nullptr) {
62     initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
63   }
64 
65   StringRef getPassName() const override { return "Hexagon VectorPrint pass"; }
66 
67   bool runOnMachineFunction(MachineFunction &Fn) override;
68 };
69 
70 char HexagonVectorPrint::ID = 0;
71 
72 } // end anonymous namespace
73 
74 static bool isVecReg(unsigned Reg) {
75   return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
76       || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15)
77       || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
78 }
79 
80 static std::string getStringReg(unsigned R) {
81   if (R >= Hexagon::V0 && R <= Hexagon::V31) {
82     static const char* S[] = { "20", "21", "22", "23", "24", "25", "26", "27",
83                         "28", "29", "2a", "2b", "2c", "2d", "2e", "2f",
84                         "30", "31", "32", "33", "34", "35", "36", "37",
85                         "38", "39", "3a", "3b", "3c", "3d", "3e", "3f"};
86     return S[R-Hexagon::V0];
87   }
88   if (R >= Hexagon::Q0 && R <= Hexagon::Q3) {
89     static const char* S[] = { "00", "01", "02", "03"};
90     return S[R-Hexagon::Q0];
91 
92   }
93   llvm_unreachable("valid vreg");
94 }
95 
96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg,
97                         MachineBasicBlock::instr_iterator I,
98                         const DebugLoc &DL, const HexagonInstrInfo *QII,
99                         MachineFunction &Fn) {
100 
101   std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);
102   const char *cstr = Fn.createExternalSymbolName(VDescStr);
103   unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects;
104   BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
105     .addExternalSymbol(cstr)
106     .addImm(ExtraInfo);
107 }
108 
109 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) {
110   if (MI.getNumOperands() < 1) return false;
111   // Vec load or compute.
112   if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
113     Reg = MI.getOperand(0).getReg();
114     if (isVecReg(Reg))
115       return !TraceHexVectorStoresOnly;
116   }
117   // Vec store.
118   if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
119     Reg = MI.getOperand(2).getReg();
120     if (isVecReg(Reg))
121       return true;
122   }
123   // Vec store post increment.
124   if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) {
125     Reg = MI.getOperand(3).getReg();
126     if (isVecReg(Reg))
127       return true;
128   }
129   return false;
130 }
131 
132 bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) {
133   bool Changed = false;
134   QST = &Fn.getSubtarget<HexagonSubtarget>();
135   QRI = QST->getRegisterInfo();
136   QII = QST->getInstrInfo();
137   std::vector<MachineInstr *> VecPrintList;
138   for (auto &MBB : Fn)
139     for (auto &MI : MBB) {
140       if (MI.isBundle()) {
141         MachineBasicBlock::instr_iterator MII = MI.getIterator();
142         for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) {
143           if (MII->getNumOperands() < 1)
144             continue;
145           unsigned Reg = 0;
146           if (getInstrVecReg(*MII, Reg)) {
147             VecPrintList.push_back((&*MII));
148             DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump());
149           }
150         }
151       } else {
152         unsigned Reg = 0;
153         if (getInstrVecReg(MI, Reg)) {
154           VecPrintList.push_back(&MI);
155           DEBUG(dbgs() << "Found vector reg \n"; MI.dump());
156         }
157       }
158     }
159 
160   Changed = !VecPrintList.empty();
161   if (!Changed)
162     return Changed;
163 
164   for (auto *I : VecPrintList) {
165     DebugLoc DL = I->getDebugLoc();
166     MachineBasicBlock *MBB = I->getParent();
167     DEBUG(dbgs() << "Evaluating V MI\n"; I->dump());
168     unsigned Reg = 0;
169     if (!getInstrVecReg(*I, Reg))
170       llvm_unreachable("Need a vector reg");
171     MachineBasicBlock::instr_iterator MII = I->getIterator();
172     if (I->isInsideBundle()) {
173       DEBUG(dbgs() << "add to end of bundle\n"; I->dump());
174       while (MBB->instr_end() != MII && MII->isInsideBundle())
175         MII++;
176     } else {
177       DEBUG(dbgs() << "add after instruction\n"; I->dump());
178       MII++;
179     }
180     if (MBB->instr_end() == MII)
181       continue;
182 
183     if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
184       DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n');
185       addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
186     } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
187       DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n');
188       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
189                   MII, DL, QII, Fn);
190       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
191                    MII, DL, QII, Fn);
192     } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) {
193       DEBUG(dbgs() << "adding dump for Q" << Reg-Hexagon::Q0 << '\n');
194       addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
195     } else
196       llvm_unreachable("Bad Vector reg");
197   }
198   return Changed;
199 }
200 
201 //===----------------------------------------------------------------------===//
202 //                         Public Constructor Functions
203 //===----------------------------------------------------------------------===//
204 INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print",
205   "Hexagon VectorPrint pass", false, false)
206 
207 FunctionPass *llvm::createHexagonVectorPrint() {
208   return new HexagonVectorPrint();
209 }
210