1 //===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 /// This file implements a TargetTransformInfo analysis pass specific to the
9 /// Hexagon target machine. It uses the target's detailed information to provide
10 /// more precise answers to certain TTI queries, while letting the target
11 /// independent and default TTI implementations handle the rest.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonTargetTransformInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "llvm/Analysis/TargetTransformInfo.h"
18 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/IR/InstrTypes.h"
20 #include "llvm/IR/Instructions.h"
21 #include "llvm/IR/User.h"
22 #include "llvm/Support/Casting.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Transforms/Utils/LoopPeel.h"
25 #include "llvm/Transforms/Utils/UnrollLoop.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "hexagontti"
30 
31 static cl::opt<bool> HexagonAutoHVX("hexagon-autohvx", cl::init(false),
32   cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
33 
34 static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
35   cl::init(true), cl::Hidden,
36   cl::desc("Control lookup table emission on Hexagon target"));
37 
38 static cl::opt<bool> HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true),
39   cl::Hidden, cl::desc("Enable masked loads/stores for HVX"));
40 
41 // Constant "cost factor" to make floating point operations more expensive
42 // in terms of vectorization cost. This isn't the best way, but it should
43 // do. Ultimately, the cost should use cycles.
44 static const unsigned FloatFactor = 4;
45 
46 bool HexagonTTIImpl::useHVX() const {
47   return ST.useHVXOps() && HexagonAutoHVX;
48 }
49 
50 unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
51   if (auto *VTy = dyn_cast<FixedVectorType>(Ty))
52     return VTy->getNumElements();
53   assert((Ty->isIntegerTy() || Ty->isFloatingPointTy()) &&
54          "Expecting scalar type");
55   return 1;
56 }
57 
58 TargetTransformInfo::PopcntSupportKind
59 HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
60   // Return fast hardware support as every input < 64 bits will be promoted
61   // to 64 bits.
62   return TargetTransformInfo::PSK_FastHardware;
63 }
64 
65 // The Hexagon target can unroll loops with run-time trip counts.
66 void HexagonTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
67                                              TTI::UnrollingPreferences &UP) {
68   UP.Runtime = UP.Partial = true;
69 }
70 
71 void HexagonTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
72                                            TTI::PeelingPreferences &PP) {
73   BaseT::getPeelingPreferences(L, SE, PP);
74   // Only try to peel innermost loops with small runtime trip counts.
75   if (L && L->isInnermost() && canPeel(L) &&
76       SE.getSmallConstantTripCount(L) == 0 &&
77       SE.getSmallConstantMaxTripCount(L) > 0 &&
78       SE.getSmallConstantMaxTripCount(L) <= 5) {
79     PP.PeelCount = 2;
80   }
81 }
82 
83 TTI::AddressingModeKind
84 HexagonTTIImpl::getPreferredAddressingMode(const Loop *L,
85                                            ScalarEvolution *SE) const {
86   return TTI::AMK_PostIndexed;
87 }
88 
89 /// --- Vector TTI begin ---
90 
91 unsigned HexagonTTIImpl::getNumberOfRegisters(bool Vector) const {
92   if (Vector)
93     return useHVX() ? 32 : 0;
94   return 32;
95 }
96 
97 unsigned HexagonTTIImpl::getMaxInterleaveFactor(unsigned VF) {
98   return useHVX() ? 2 : 1;
99 }
100 
101 unsigned HexagonTTIImpl::getRegisterBitWidth(bool Vector) const {
102   return Vector ? getMinVectorRegisterBitWidth() : 32;
103 }
104 
105 unsigned HexagonTTIImpl::getMinVectorRegisterBitWidth() const {
106   return useHVX() ? ST.getVectorLength()*8 : 32;
107 }
108 
109 ElementCount HexagonTTIImpl::getMinimumVF(unsigned ElemWidth,
110                                           bool IsScalable) const {
111   assert(!IsScalable && "Scalable VFs are not supported for Hexagon");
112   return ElementCount::getFixed((8 * ST.getVectorLength()) / ElemWidth);
113 }
114 
115 unsigned HexagonTTIImpl::getScalarizationOverhead(VectorType *Ty,
116                                                   const APInt &DemandedElts,
117                                                   bool Insert, bool Extract) {
118   return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
119 }
120 
121 unsigned HexagonTTIImpl::getOperandsScalarizationOverhead(
122       ArrayRef<const Value*> Args, unsigned VF) {
123   return BaseT::getOperandsScalarizationOverhead(Args, VF);
124 }
125 
126 unsigned HexagonTTIImpl::getCallInstrCost(Function *F, Type *RetTy,
127       ArrayRef<Type*> Tys, TTI::TargetCostKind CostKind) {
128   return BaseT::getCallInstrCost(F, RetTy, Tys, CostKind);
129 }
130 
131 unsigned
132 HexagonTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
133                                       TTI::TargetCostKind CostKind) {
134   if (ICA.getID() == Intrinsic::bswap) {
135     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, ICA.getReturnType());
136     return LT.first + 2;
137   }
138   return BaseT::getIntrinsicInstrCost(ICA, CostKind);
139 }
140 
141 unsigned HexagonTTIImpl::getAddressComputationCost(Type *Tp,
142       ScalarEvolution *SE, const SCEV *S) {
143   return 0;
144 }
145 
146 unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
147                                          MaybeAlign Alignment,
148                                          unsigned AddressSpace,
149                                          TTI::TargetCostKind CostKind,
150                                          const Instruction *I) {
151   assert(Opcode == Instruction::Load || Opcode == Instruction::Store);
152   // TODO: Handle other cost kinds.
153   if (CostKind != TTI::TCK_RecipThroughput)
154     return 1;
155 
156   if (Opcode == Instruction::Store)
157     return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
158                                   CostKind, I);
159 
160   if (Src->isVectorTy()) {
161     VectorType *VecTy = cast<VectorType>(Src);
162     unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
163     if (useHVX() && ST.isTypeForHVX(VecTy)) {
164       unsigned RegWidth = getRegisterBitWidth(true);
165       assert(RegWidth && "Non-zero vector register width expected");
166       // Cost of HVX loads.
167       if (VecWidth % RegWidth == 0)
168         return VecWidth / RegWidth;
169       // Cost of constructing HVX vector from scalar loads
170       const Align RegAlign(RegWidth / 8);
171       if (!Alignment || *Alignment > RegAlign)
172         Alignment = RegAlign;
173       assert(Alignment);
174       unsigned AlignWidth = 8 * Alignment->value();
175       unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
176       return 3 * NumLoads;
177     }
178 
179     // Non-HVX vectors.
180     // Add extra cost for floating point types.
181     unsigned Cost =
182         VecTy->getElementType()->isFloatingPointTy() ? FloatFactor : 1;
183 
184     // At this point unspecified alignment is considered as Align(1).
185     const Align BoundAlignment = std::min(Alignment.valueOrOne(), Align(8));
186     unsigned AlignWidth = 8 * BoundAlignment.value();
187     unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
188     if (Alignment == Align(4) || Alignment == Align(8))
189       return Cost * NumLoads;
190     // Loads of less than 32 bits will need extra inserts to compose a vector.
191     assert(BoundAlignment <= Align(8));
192     unsigned LogA = Log2(BoundAlignment);
193     return (3 - LogA) * Cost * NumLoads;
194   }
195 
196   return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
197                                 CostKind, I);
198 }
199 
200 unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
201                                                Align Alignment,
202                                                unsigned AddressSpace,
203                                                TTI::TargetCostKind CostKind) {
204   return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
205                                       CostKind);
206 }
207 
208 unsigned HexagonTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp,
209       int Index, Type *SubTp) {
210   return 1;
211 }
212 
213 unsigned HexagonTTIImpl::getGatherScatterOpCost(
214     unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
215     Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
216   return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
217                                        Alignment, CostKind, I);
218 }
219 
220 unsigned HexagonTTIImpl::getInterleavedMemoryOpCost(
221     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
222     Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
223     bool UseMaskForCond, bool UseMaskForGaps) {
224   if (Indices.size() != Factor || UseMaskForCond || UseMaskForGaps)
225     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
226                                              Alignment, AddressSpace,
227                                              CostKind,
228                                              UseMaskForCond, UseMaskForGaps);
229   return getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace,
230                          CostKind);
231 }
232 
233 unsigned HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
234                                             Type *CondTy,
235                                             CmpInst::Predicate VecPred,
236                                             TTI::TargetCostKind CostKind,
237                                             const Instruction *I) {
238   if (ValTy->isVectorTy() && CostKind == TTI::TCK_RecipThroughput) {
239     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, ValTy);
240     if (Opcode == Instruction::FCmp)
241       return LT.first + FloatFactor * getTypeNumElements(ValTy);
242   }
243   return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
244 }
245 
246 unsigned HexagonTTIImpl::getArithmeticInstrCost(
247     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
248     TTI::OperandValueKind Opd1Info,
249     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
250     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
251     const Instruction *CxtI) {
252   // TODO: Handle more cost kinds.
253   if (CostKind != TTI::TCK_RecipThroughput)
254     return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
255                                          Opd2Info, Opd1PropInfo,
256                                          Opd2PropInfo, Args, CxtI);
257 
258   if (Ty->isVectorTy()) {
259     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, Ty);
260     if (LT.second.isFloatingPoint())
261       return LT.first + FloatFactor * getTypeNumElements(Ty);
262   }
263   return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
264                                        Opd1PropInfo, Opd2PropInfo, Args, CxtI);
265 }
266 
267 unsigned HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy,
268                                           Type *SrcTy, TTI::CastContextHint CCH,
269                                           TTI::TargetCostKind CostKind,
270                                           const Instruction *I) {
271   if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) {
272     unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0;
273     unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0;
274 
275     std::pair<int, MVT> SrcLT = TLI.getTypeLegalizationCost(DL, SrcTy);
276     std::pair<int, MVT> DstLT = TLI.getTypeLegalizationCost(DL, DstTy);
277     unsigned Cost = std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN);
278     // TODO: Allow non-throughput costs that aren't binary.
279     if (CostKind != TTI::TCK_RecipThroughput)
280       return Cost == 0 ? 0 : 1;
281     return Cost;
282   }
283   return 1;
284 }
285 
286 unsigned HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
287       unsigned Index) {
288   Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType()
289                                    : Val;
290   if (Opcode == Instruction::InsertElement) {
291     // Need two rotations for non-zero index.
292     unsigned Cost = (Index != 0) ? 2 : 0;
293     if (ElemTy->isIntegerTy(32))
294       return Cost;
295     // If it's not a 32-bit value, there will need to be an extract.
296     return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index);
297   }
298 
299   if (Opcode == Instruction::ExtractElement)
300     return 2;
301 
302   return 1;
303 }
304 
305 bool HexagonTTIImpl::isLegalMaskedStore(Type *DataType, Align /*Alignment*/) {
306   return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
307 }
308 
309 bool HexagonTTIImpl::isLegalMaskedLoad(Type *DataType, Align /*Alignment*/) {
310   return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
311 }
312 
313 /// --- Vector TTI end ---
314 
315 unsigned HexagonTTIImpl::getPrefetchDistance() const {
316   return ST.getL1PrefetchDistance();
317 }
318 
319 unsigned HexagonTTIImpl::getCacheLineSize() const {
320   return ST.getL1CacheLineSize();
321 }
322 
323 int
324 HexagonTTIImpl::getUserCost(const User *U,
325                             ArrayRef<const Value *> Operands,
326                             TTI::TargetCostKind CostKind) {
327   auto isCastFoldedIntoLoad = [this](const CastInst *CI) -> bool {
328     if (!CI->isIntegerCast())
329       return false;
330     // Only extensions from an integer type shorter than 32-bit to i32
331     // can be folded into the load.
332     const DataLayout &DL = getDataLayout();
333     unsigned SBW = DL.getTypeSizeInBits(CI->getSrcTy());
334     unsigned DBW = DL.getTypeSizeInBits(CI->getDestTy());
335     if (DBW != 32 || SBW >= DBW)
336       return false;
337 
338     const LoadInst *LI = dyn_cast<const LoadInst>(CI->getOperand(0));
339     // Technically, this code could allow multiple uses of the load, and
340     // check if all the uses are the same extension operation, but this
341     // should be sufficient for most cases.
342     return LI && LI->hasOneUse();
343   };
344 
345   if (const CastInst *CI = dyn_cast<const CastInst>(U))
346     if (isCastFoldedIntoLoad(CI))
347       return TargetTransformInfo::TCC_Free;
348   return BaseT::getUserCost(U, Operands, CostKind);
349 }
350 
351 bool HexagonTTIImpl::shouldBuildLookupTables() const {
352   return EmitLookupTables;
353 }
354