1 //===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 /// This file implements a TargetTransformInfo analysis pass specific to the
9 /// Hexagon target machine. It uses the target's detailed information to provide
10 /// more precise answers to certain TTI queries, while letting the target
11 /// independent and default TTI implementations handle the rest.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonTargetTransformInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "llvm/Analysis/TargetTransformInfo.h"
18 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/IR/InstrTypes.h"
20 #include "llvm/IR/Instructions.h"
21 #include "llvm/IR/User.h"
22 #include "llvm/Support/Casting.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Transforms/Utils/UnrollLoop.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "hexagontti"
29 
30 static cl::opt<bool> HexagonAutoHVX("hexagon-autohvx", cl::init(false),
31   cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
32 
33 static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
34   cl::init(true), cl::Hidden,
35   cl::desc("Control lookup table emission on Hexagon target"));
36 
37 // Constant "cost factor" to make floating point operations more expensive
38 // in terms of vectorization cost. This isn't the best way, but it should
39 // do. Ultimately, the cost should use cycles.
40 static const unsigned FloatFactor = 4;
41 
42 bool HexagonTTIImpl::useHVX() const {
43   return ST.useHVXOps() && HexagonAutoHVX;
44 }
45 
46 bool HexagonTTIImpl::isTypeForHVX(Type *VecTy) const {
47   assert(VecTy->isVectorTy());
48   if (isa<ScalableVectorType>(VecTy))
49     return false;
50   // Avoid types like <2 x i32*>.
51   if (!cast<VectorType>(VecTy)->getElementType()->isIntegerTy())
52     return false;
53   EVT VecVT = EVT::getEVT(VecTy);
54   if (!VecVT.isSimple() || VecVT.getSizeInBits() <= 64)
55     return false;
56   if (ST.isHVXVectorType(VecVT.getSimpleVT()))
57     return true;
58   auto Action = TLI.getPreferredVectorAction(VecVT.getSimpleVT());
59   return Action == TargetLoweringBase::TypeWidenVector;
60 }
61 
62 unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
63   if (auto *VTy = dyn_cast<FixedVectorType>(Ty))
64     return VTy->getNumElements();
65   assert((Ty->isIntegerTy() || Ty->isFloatingPointTy()) &&
66          "Expecting scalar type");
67   return 1;
68 }
69 
70 TargetTransformInfo::PopcntSupportKind
71 HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
72   // Return fast hardware support as every input < 64 bits will be promoted
73   // to 64 bits.
74   return TargetTransformInfo::PSK_FastHardware;
75 }
76 
77 // The Hexagon target can unroll loops with run-time trip counts.
78 void HexagonTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
79                                              TTI::UnrollingPreferences &UP) {
80   UP.Runtime = UP.Partial = true;
81   // Only try to peel innermost loops with small runtime trip counts.
82   if (L && L->empty() && canPeel(L) &&
83       SE.getSmallConstantTripCount(L) == 0 &&
84       SE.getSmallConstantMaxTripCount(L) > 0 &&
85       SE.getSmallConstantMaxTripCount(L) <= 5) {
86     UP.PeelCount = 2;
87   }
88 }
89 
90 bool HexagonTTIImpl::shouldFavorPostInc() const {
91   return true;
92 }
93 
94 /// --- Vector TTI begin ---
95 
96 unsigned HexagonTTIImpl::getNumberOfRegisters(bool Vector) const {
97   if (Vector)
98     return useHVX() ? 32 : 0;
99   return 32;
100 }
101 
102 unsigned HexagonTTIImpl::getMaxInterleaveFactor(unsigned VF) {
103   return useHVX() ? 2 : 0;
104 }
105 
106 unsigned HexagonTTIImpl::getRegisterBitWidth(bool Vector) const {
107   return Vector ? getMinVectorRegisterBitWidth() : 32;
108 }
109 
110 unsigned HexagonTTIImpl::getMinVectorRegisterBitWidth() const {
111   return useHVX() ? ST.getVectorLength()*8 : 0;
112 }
113 
114 unsigned HexagonTTIImpl::getMinimumVF(unsigned ElemWidth) const {
115   return (8 * ST.getVectorLength()) / ElemWidth;
116 }
117 
118 unsigned HexagonTTIImpl::getScalarizationOverhead(VectorType *Ty,
119                                                   const APInt &DemandedElts,
120                                                   bool Insert, bool Extract) {
121   return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
122 }
123 
124 unsigned HexagonTTIImpl::getOperandsScalarizationOverhead(
125       ArrayRef<const Value*> Args, unsigned VF) {
126   return BaseT::getOperandsScalarizationOverhead(Args, VF);
127 }
128 
129 unsigned HexagonTTIImpl::getCallInstrCost(Function *F, Type *RetTy,
130       ArrayRef<Type*> Tys, TTI::TargetCostKind CostKind) {
131   return BaseT::getCallInstrCost(F, RetTy, Tys, CostKind);
132 }
133 
134 unsigned
135 HexagonTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
136                                       TTI::TargetCostKind CostKind) {
137   if (ICA.getID() == Intrinsic::bswap) {
138     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, ICA.getReturnType());
139     return LT.first + 2;
140   }
141   return BaseT::getIntrinsicInstrCost(ICA, CostKind);
142 }
143 
144 unsigned HexagonTTIImpl::getAddressComputationCost(Type *Tp,
145       ScalarEvolution *SE, const SCEV *S) {
146   return 0;
147 }
148 
149 unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
150                                          MaybeAlign Alignment,
151                                          unsigned AddressSpace,
152                                          TTI::TargetCostKind CostKind,
153                                          const Instruction *I) {
154   assert(Opcode == Instruction::Load || Opcode == Instruction::Store);
155   if (Opcode == Instruction::Store)
156     return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
157                                   CostKind, I);
158 
159   if (Src->isVectorTy()) {
160     VectorType *VecTy = cast<VectorType>(Src);
161     unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
162     if (useHVX() && isTypeForHVX(VecTy)) {
163       unsigned RegWidth = getRegisterBitWidth(true);
164       assert(RegWidth && "Non-zero vector register width expected");
165       // Cost of HVX loads.
166       if (VecWidth % RegWidth == 0)
167         return VecWidth / RegWidth;
168       // Cost of constructing HVX vector from scalar loads
169       const Align RegAlign(RegWidth / 8);
170       if (!Alignment || *Alignment > RegAlign)
171         Alignment = RegAlign;
172       assert(Alignment);
173       unsigned AlignWidth = 8 * Alignment->value();
174       unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
175       return 3 * NumLoads;
176     }
177 
178     // Non-HVX vectors.
179     // Add extra cost for floating point types.
180     unsigned Cost =
181         VecTy->getElementType()->isFloatingPointTy() ? FloatFactor : 1;
182 
183     // At this point unspecified alignment is considered as Align(1).
184     const Align BoundAlignment = std::min(Alignment.valueOrOne(), Align(8));
185     unsigned AlignWidth = 8 * BoundAlignment.value();
186     unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
187     if (Alignment == Align(4) || Alignment == Align(8))
188       return Cost * NumLoads;
189     // Loads of less than 32 bits will need extra inserts to compose a vector.
190     assert(BoundAlignment <= Align(8));
191     unsigned LogA = Log2(BoundAlignment);
192     return (3 - LogA) * Cost * NumLoads;
193   }
194 
195   return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
196                                 CostKind, I);
197 }
198 
199 unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode,
200       Type *Src, unsigned Alignment, unsigned AddressSpace,
201       TTI::TargetCostKind CostKind) {
202   return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
203                                       CostKind);
204 }
205 
206 unsigned HexagonTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp,
207       int Index, Type *SubTp) {
208   return 1;
209 }
210 
211 unsigned HexagonTTIImpl::getGatherScatterOpCost(
212     unsigned Opcode, Type *DataTy, Value *Ptr, bool VariableMask,
213     unsigned Alignment, TTI::TargetCostKind CostKind,
214     const Instruction *I) {
215   return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
216                                        Alignment, CostKind, I);
217 }
218 
219 unsigned HexagonTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode,
220       Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
221       unsigned Alignment, unsigned AddressSpace,
222       TTI::TargetCostKind CostKind, bool UseMaskForCond,
223       bool UseMaskForGaps) {
224   if (Indices.size() != Factor || UseMaskForCond || UseMaskForGaps)
225     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
226                                              Alignment, AddressSpace,
227                                              CostKind,
228                                              UseMaskForCond, UseMaskForGaps);
229   return getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace,
230                          CostKind);
231 }
232 
233 unsigned HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
234       Type *CondTy, TTI::TargetCostKind CostKind, const Instruction *I) {
235   if (ValTy->isVectorTy()) {
236     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, ValTy);
237     if (Opcode == Instruction::FCmp)
238       return LT.first + FloatFactor * getTypeNumElements(ValTy);
239   }
240   return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I);
241 }
242 
243 unsigned HexagonTTIImpl::getArithmeticInstrCost(
244     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
245     TTI::OperandValueKind Opd1Info,
246     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
247     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
248     const Instruction *CxtI) {
249   if (Ty->isVectorTy()) {
250     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, Ty);
251     if (LT.second.isFloatingPoint())
252       return LT.first + FloatFactor * getTypeNumElements(Ty);
253   }
254   return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
255                                        Opd1PropInfo, Opd2PropInfo, Args, CxtI);
256 }
257 
258 unsigned HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy,
259       Type *SrcTy, TTI::TargetCostKind CostKind, const Instruction *I) {
260   if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) {
261     unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0;
262     unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0;
263 
264     std::pair<int, MVT> SrcLT = TLI.getTypeLegalizationCost(DL, SrcTy);
265     std::pair<int, MVT> DstLT = TLI.getTypeLegalizationCost(DL, DstTy);
266     return std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN);
267   }
268   return 1;
269 }
270 
271 unsigned HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
272       unsigned Index) {
273   Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType()
274                                    : Val;
275   if (Opcode == Instruction::InsertElement) {
276     // Need two rotations for non-zero index.
277     unsigned Cost = (Index != 0) ? 2 : 0;
278     if (ElemTy->isIntegerTy(32))
279       return Cost;
280     // If it's not a 32-bit value, there will need to be an extract.
281     return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index);
282   }
283 
284   if (Opcode == Instruction::ExtractElement)
285     return 2;
286 
287   return 1;
288 }
289 
290 /// --- Vector TTI end ---
291 
292 unsigned HexagonTTIImpl::getPrefetchDistance() const {
293   return ST.getL1PrefetchDistance();
294 }
295 
296 unsigned HexagonTTIImpl::getCacheLineSize() const {
297   return ST.getL1CacheLineSize();
298 }
299 
300 int
301 HexagonTTIImpl::getUserCost(const User *U,
302                             ArrayRef<const Value *> Operands,
303                             TTI::TargetCostKind CostKind) {
304   auto isCastFoldedIntoLoad = [this](const CastInst *CI) -> bool {
305     if (!CI->isIntegerCast())
306       return false;
307     // Only extensions from an integer type shorter than 32-bit to i32
308     // can be folded into the load.
309     const DataLayout &DL = getDataLayout();
310     unsigned SBW = DL.getTypeSizeInBits(CI->getSrcTy());
311     unsigned DBW = DL.getTypeSizeInBits(CI->getDestTy());
312     if (DBW != 32 || SBW >= DBW)
313       return false;
314 
315     const LoadInst *LI = dyn_cast<const LoadInst>(CI->getOperand(0));
316     // Technically, this code could allow multiple uses of the load, and
317     // check if all the uses are the same extension operation, but this
318     // should be sufficient for most cases.
319     return LI && LI->hasOneUse();
320   };
321 
322   if (const CastInst *CI = dyn_cast<const CastInst>(U))
323     if (isCastFoldedIntoLoad(CI))
324       return TargetTransformInfo::TCC_Free;
325   return BaseT::getUserCost(U, Operands, CostKind);
326 }
327 
328 bool HexagonTTIImpl::shouldBuildLookupTables() const {
329   return EmitLookupTables;
330 }
331