1 //===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 /// This file implements a TargetTransformInfo analysis pass specific to the
9 /// Hexagon target machine. It uses the target's detailed information to provide
10 /// more precise answers to certain TTI queries, while letting the target
11 /// independent and default TTI implementations handle the rest.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonTargetTransformInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "llvm/Analysis/TargetTransformInfo.h"
18 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/IR/InstrTypes.h"
20 #include "llvm/IR/Instructions.h"
21 #include "llvm/IR/User.h"
22 #include "llvm/Support/Casting.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Transforms/Utils/UnrollLoop.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "hexagontti"
29 
30 static cl::opt<bool> HexagonAutoHVX("hexagon-autohvx", cl::init(false),
31   cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
32 
33 static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
34   cl::init(true), cl::Hidden,
35   cl::desc("Control lookup table emission on Hexagon target"));
36 
37 // Constant "cost factor" to make floating point operations more expensive
38 // in terms of vectorization cost. This isn't the best way, but it should
39 // do. Ultimately, the cost should use cycles.
40 static const unsigned FloatFactor = 4;
41 
42 bool HexagonTTIImpl::useHVX() const {
43   return ST.useHVXOps() && HexagonAutoHVX;
44 }
45 
46 bool HexagonTTIImpl::isTypeForHVX(Type *VecTy) const {
47   assert(VecTy->isVectorTy());
48   if (cast<VectorType>(VecTy)->isScalable())
49     return false;
50   // Avoid types like <2 x i32*>.
51   if (!cast<VectorType>(VecTy)->getElementType()->isIntegerTy())
52     return false;
53   EVT VecVT = EVT::getEVT(VecTy);
54   if (!VecVT.isSimple() || VecVT.getSizeInBits() <= 64)
55     return false;
56   if (ST.isHVXVectorType(VecVT.getSimpleVT()))
57     return true;
58   auto Action = TLI.getPreferredVectorAction(VecVT.getSimpleVT());
59   return Action == TargetLoweringBase::TypeWidenVector;
60 }
61 
62 unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
63   if (auto *VTy = dyn_cast<VectorType>(Ty))
64     return VTy->getNumElements();
65   assert((Ty->isIntegerTy() || Ty->isFloatingPointTy()) &&
66          "Expecting scalar type");
67   return 1;
68 }
69 
70 TargetTransformInfo::PopcntSupportKind
71 HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
72   // Return fast hardware support as every input < 64 bits will be promoted
73   // to 64 bits.
74   return TargetTransformInfo::PSK_FastHardware;
75 }
76 
77 // The Hexagon target can unroll loops with run-time trip counts.
78 void HexagonTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
79                                              TTI::UnrollingPreferences &UP) {
80   UP.Runtime = UP.Partial = true;
81   // Only try to peel innermost loops with small runtime trip counts.
82   if (L && L->empty() && canPeel(L) &&
83       SE.getSmallConstantTripCount(L) == 0 &&
84       SE.getSmallConstantMaxTripCount(L) > 0 &&
85       SE.getSmallConstantMaxTripCount(L) <= 5) {
86     UP.PeelCount = 2;
87   }
88 }
89 
90 bool HexagonTTIImpl::shouldFavorPostInc() const {
91   return true;
92 }
93 
94 /// --- Vector TTI begin ---
95 
96 unsigned HexagonTTIImpl::getNumberOfRegisters(bool Vector) const {
97   if (Vector)
98     return useHVX() ? 32 : 0;
99   return 32;
100 }
101 
102 unsigned HexagonTTIImpl::getMaxInterleaveFactor(unsigned VF) {
103   return useHVX() ? 2 : 0;
104 }
105 
106 unsigned HexagonTTIImpl::getRegisterBitWidth(bool Vector) const {
107   return Vector ? getMinVectorRegisterBitWidth() : 32;
108 }
109 
110 unsigned HexagonTTIImpl::getMinVectorRegisterBitWidth() const {
111   return useHVX() ? ST.getVectorLength()*8 : 0;
112 }
113 
114 unsigned HexagonTTIImpl::getMinimumVF(unsigned ElemWidth) const {
115   return (8 * ST.getVectorLength()) / ElemWidth;
116 }
117 
118 unsigned HexagonTTIImpl::getScalarizationOverhead(Type *Ty, bool Insert,
119       bool Extract) {
120   return BaseT::getScalarizationOverhead(Ty, Insert, Extract);
121 }
122 
123 unsigned HexagonTTIImpl::getOperandsScalarizationOverhead(
124       ArrayRef<const Value*> Args, unsigned VF) {
125   return BaseT::getOperandsScalarizationOverhead(Args, VF);
126 }
127 
128 unsigned HexagonTTIImpl::getCallInstrCost(Function *F, Type *RetTy,
129       ArrayRef<Type*> Tys) {
130   return BaseT::getCallInstrCost(F, RetTy, Tys);
131 }
132 
133 unsigned HexagonTTIImpl::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
134                                                ArrayRef<Value *> Args,
135                                                FastMathFlags FMF, unsigned VF,
136                                                const Instruction *I) {
137   return BaseT::getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF, I);
138 }
139 
140 unsigned HexagonTTIImpl::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
141                                                ArrayRef<Type *> Tys,
142                                                FastMathFlags FMF,
143                                                unsigned ScalarizationCostPassed,
144                                                const Instruction *I) {
145   if (ID == Intrinsic::bswap) {
146     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, RetTy);
147     return LT.first + 2;
148   }
149   return BaseT::getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
150                                       ScalarizationCostPassed, I);
151 }
152 
153 unsigned HexagonTTIImpl::getAddressComputationCost(Type *Tp,
154       ScalarEvolution *SE, const SCEV *S) {
155   return 0;
156 }
157 
158 unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
159                                          MaybeAlign Alignment,
160                                          unsigned AddressSpace,
161                                          const Instruction *I) {
162   assert(Opcode == Instruction::Load || Opcode == Instruction::Store);
163   if (Opcode == Instruction::Store)
164     return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
165 
166   if (Src->isVectorTy()) {
167     VectorType *VecTy = cast<VectorType>(Src);
168     unsigned VecWidth = VecTy->getBitWidth();
169     if (useHVX() && isTypeForHVX(VecTy)) {
170       unsigned RegWidth = getRegisterBitWidth(true);
171       assert(RegWidth && "Non-zero vector register width expected");
172       // Cost of HVX loads.
173       if (VecWidth % RegWidth == 0)
174         return VecWidth / RegWidth;
175       // Cost of constructing HVX vector from scalar loads
176       const Align RegAlign(RegWidth / 8);
177       if (!Alignment || *Alignment > RegAlign)
178         Alignment = RegAlign;
179       assert(Alignment);
180       unsigned AlignWidth = 8 * Alignment->value();
181       unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
182       return 3 * NumLoads;
183     }
184 
185     // Non-HVX vectors.
186     // Add extra cost for floating point types.
187     unsigned Cost =
188         VecTy->getElementType()->isFloatingPointTy() ? FloatFactor : 1;
189 
190     // At this point unspecified alignment is considered as Align(1).
191     const Align BoundAlignment = std::min(Alignment.valueOrOne(), Align(8));
192     unsigned AlignWidth = 8 * BoundAlignment.value();
193     unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
194     if (Alignment == Align(4) || Alignment == Align(8))
195       return Cost * NumLoads;
196     // Loads of less than 32 bits will need extra inserts to compose a vector.
197     assert(BoundAlignment <= Align(8));
198     unsigned LogA = Log2(BoundAlignment);
199     return (3 - LogA) * Cost * NumLoads;
200   }
201 
202   return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
203 }
204 
205 unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode,
206       Type *Src, unsigned Alignment, unsigned AddressSpace) {
207   return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
208 }
209 
210 unsigned HexagonTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp,
211       int Index, Type *SubTp) {
212   return 1;
213 }
214 
215 unsigned HexagonTTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
216                                                 Value *Ptr, bool VariableMask,
217                                                 unsigned Alignment,
218                                                 const Instruction *I) {
219   return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
220                                        Alignment, I);
221 }
222 
223 unsigned HexagonTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode,
224       Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
225       unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
226       bool UseMaskForGaps) {
227   if (Indices.size() != Factor || UseMaskForCond || UseMaskForGaps)
228     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
229                                              Alignment, AddressSpace,
230                                              UseMaskForCond, UseMaskForGaps);
231   return getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace,
232                          nullptr);
233 }
234 
235 unsigned HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
236       Type *CondTy, const Instruction *I) {
237   if (ValTy->isVectorTy()) {
238     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, ValTy);
239     if (Opcode == Instruction::FCmp)
240       return LT.first + FloatFactor * getTypeNumElements(ValTy);
241   }
242   return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
243 }
244 
245 unsigned HexagonTTIImpl::getArithmeticInstrCost(
246     unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
247     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
248     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
249     const Instruction *CxtI) {
250   if (Ty->isVectorTy()) {
251     std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, Ty);
252     if (LT.second.isFloatingPoint())
253       return LT.first + FloatFactor * getTypeNumElements(Ty);
254   }
255   return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
256                                        Opd1PropInfo, Opd2PropInfo, Args, CxtI);
257 }
258 
259 unsigned HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy,
260       Type *SrcTy, const Instruction *I) {
261   if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) {
262     unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0;
263     unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0;
264 
265     std::pair<int, MVT> SrcLT = TLI.getTypeLegalizationCost(DL, SrcTy);
266     std::pair<int, MVT> DstLT = TLI.getTypeLegalizationCost(DL, DstTy);
267     return std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN);
268   }
269   return 1;
270 }
271 
272 unsigned HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
273       unsigned Index) {
274   Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType()
275                                    : Val;
276   if (Opcode == Instruction::InsertElement) {
277     // Need two rotations for non-zero index.
278     unsigned Cost = (Index != 0) ? 2 : 0;
279     if (ElemTy->isIntegerTy(32))
280       return Cost;
281     // If it's not a 32-bit value, there will need to be an extract.
282     return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index);
283   }
284 
285   if (Opcode == Instruction::ExtractElement)
286     return 2;
287 
288   return 1;
289 }
290 
291 /// --- Vector TTI end ---
292 
293 unsigned HexagonTTIImpl::getPrefetchDistance() const {
294   return ST.getL1PrefetchDistance();
295 }
296 
297 unsigned HexagonTTIImpl::getCacheLineSize() const {
298   return ST.getL1CacheLineSize();
299 }
300 
301 int HexagonTTIImpl::getUserCost(const User *U,
302                                 ArrayRef<const Value *> Operands) {
303   auto isCastFoldedIntoLoad = [this](const CastInst *CI) -> bool {
304     if (!CI->isIntegerCast())
305       return false;
306     // Only extensions from an integer type shorter than 32-bit to i32
307     // can be folded into the load.
308     const DataLayout &DL = getDataLayout();
309     unsigned SBW = DL.getTypeSizeInBits(CI->getSrcTy());
310     unsigned DBW = DL.getTypeSizeInBits(CI->getDestTy());
311     if (DBW != 32 || SBW >= DBW)
312       return false;
313 
314     const LoadInst *LI = dyn_cast<const LoadInst>(CI->getOperand(0));
315     // Technically, this code could allow multiple uses of the load, and
316     // check if all the uses are the same extension operation, but this
317     // should be sufficient for most cases.
318     return LI && LI->hasOneUse();
319   };
320 
321   if (const CastInst *CI = dyn_cast<const CastInst>(U))
322     if (isCastFoldedIntoLoad(CI))
323       return TargetTransformInfo::TCC_Free;
324   return BaseT::getUserCost(U, Operands);
325 }
326 
327 bool HexagonTTIImpl::shouldBuildLookupTables() const {
328   return EmitLookupTables;
329 }
330