1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineScheduler.h"
17 #include "HexagonTargetObjectFile.h"
18 #include "HexagonTargetTransformInfo.h"
19 #include "HexagonVectorLoopCarriedReuse.h"
20 #include "TargetInfo/HexagonTargetInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/IR/LegacyPassManager.h"
24 #include "llvm/IR/Module.h"
25 #include "llvm/Passes/PassBuilder.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
29 #include "llvm/Transforms/Scalar.h"
30 
31 using namespace llvm;
32 
33 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
34   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
35 
36 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
37   cl::init(true), cl::desc("Enable RDF-based optimizations"));
38 
39 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
40   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
41 
42 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
43   cl::Hidden, cl::ZeroOrMore, cl::init(false),
44   cl::desc("Disable Hexagon Addressing Mode Optimization"));
45 
46 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
47   cl::Hidden, cl::ZeroOrMore, cl::init(false),
48   cl::desc("Disable Hexagon CFG Optimization"));
49 
50 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
51   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
52 
53 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
54   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
55 
56 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
57   cl::init(true), cl::Hidden, cl::ZeroOrMore,
58   cl::desc("Early expansion of MUX"));
59 
60 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
61   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
62 
63 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
64   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
65 
66 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
67   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
68 
69 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
70   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
71 
72 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
73   cl::desc("Enable converting conditional transfers into MUX instructions"));
74 
75 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
76   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
77   "predicate instructions"));
78 
79 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
80   cl::init(false), cl::Hidden, cl::ZeroOrMore,
81   cl::desc("Enable loop data prefetch on Hexagon"));
82 
83 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
84   cl::desc("Disable splitting double registers"));
85 
86 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
87   cl::Hidden, cl::desc("Bit simplification"));
88 
89 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
90   cl::Hidden, cl::desc("Loop rescheduling"));
91 
92 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
93   cl::Hidden, cl::desc("Disable backend optimizations"));
94 
95 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
96   cl::Hidden, cl::ZeroOrMore, cl::init(false),
97   cl::desc("Enable Hexagon Vector print instr pass"));
98 
99 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
100   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
101 
102 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
103   cl::Hidden, cl::ZeroOrMore, cl::init(true),
104   cl::desc("Simplify the CFG after atomic expansion pass"));
105 
106 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
107                                         cl::ZeroOrMore, cl::init(true),
108                                         cl::desc("Enable instsimplify"));
109 
110 /// HexagonTargetMachineModule - Note that this is used on hosts that
111 /// cannot link in a library unless there are references into the
112 /// library.  In particular, it seems that it is not possible to get
113 /// things to work on Win32 without this.  Though it is unused, do not
114 /// remove it.
115 extern "C" int HexagonTargetMachineModule;
116 int HexagonTargetMachineModule = 0;
117 
118 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
119   ScheduleDAGMILive *DAG =
120     new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
121   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
122   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
123   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
124   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
125   return DAG;
126 }
127 
128 static MachineSchedRegistry
129 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
130                     createVLIWMachineSched);
131 
132 namespace llvm {
133   extern char &HexagonExpandCondsetsID;
134   void initializeHexagonBitSimplifyPass(PassRegistry&);
135   void initializeHexagonConstExtendersPass(PassRegistry&);
136   void initializeHexagonConstPropagationPass(PassRegistry&);
137   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
138   void initializeHexagonExpandCondsetsPass(PassRegistry&);
139   void initializeHexagonGenMuxPass(PassRegistry&);
140   void initializeHexagonHardwareLoopsPass(PassRegistry&);
141   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
142   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
143   void initializeHexagonNewValueJumpPass(PassRegistry&);
144   void initializeHexagonOptAddrModePass(PassRegistry&);
145   void initializeHexagonPacketizerPass(PassRegistry&);
146   void initializeHexagonRDFOptPass(PassRegistry&);
147   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
148   void initializeHexagonVExtractPass(PassRegistry&);
149   Pass *createHexagonLoopIdiomPass();
150   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
151 
152   FunctionPass *createHexagonBitSimplify();
153   FunctionPass *createHexagonBranchRelaxation();
154   FunctionPass *createHexagonCallFrameInformation();
155   FunctionPass *createHexagonCFGOptimizer();
156   FunctionPass *createHexagonCommonGEP();
157   FunctionPass *createHexagonConstExtenders();
158   FunctionPass *createHexagonConstPropagationPass();
159   FunctionPass *createHexagonCopyToCombine();
160   FunctionPass *createHexagonEarlyIfConversion();
161   FunctionPass *createHexagonFixupHwLoops();
162   FunctionPass *createHexagonGenExtract();
163   FunctionPass *createHexagonGenInsert();
164   FunctionPass *createHexagonGenMux();
165   FunctionPass *createHexagonGenPredicate();
166   FunctionPass *createHexagonHardwareLoops();
167   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
168                                      CodeGenOpt::Level OptLevel);
169   FunctionPass *createHexagonLoopRescheduling();
170   FunctionPass *createHexagonNewValueJump();
171   FunctionPass *createHexagonOptimizeSZextends();
172   FunctionPass *createHexagonOptAddrMode();
173   FunctionPass *createHexagonPacketizer(bool Minimal);
174   FunctionPass *createHexagonPeephole();
175   FunctionPass *createHexagonRDFOpt();
176   FunctionPass *createHexagonSplitConst32AndConst64();
177   FunctionPass *createHexagonSplitDoubleRegs();
178   FunctionPass *createHexagonStoreWidening();
179   FunctionPass *createHexagonVectorPrint();
180   FunctionPass *createHexagonVExtract();
181 } // end namespace llvm;
182 
183 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
184   if (!RM.hasValue())
185     return Reloc::Static;
186   return *RM;
187 }
188 
189 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
190   // Register the target.
191   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
192 
193   PassRegistry &PR = *PassRegistry::getPassRegistry();
194   initializeHexagonBitSimplifyPass(PR);
195   initializeHexagonConstExtendersPass(PR);
196   initializeHexagonConstPropagationPass(PR);
197   initializeHexagonEarlyIfConversionPass(PR);
198   initializeHexagonGenMuxPass(PR);
199   initializeHexagonHardwareLoopsPass(PR);
200   initializeHexagonLoopIdiomRecognizePass(PR);
201   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
202   initializeHexagonNewValueJumpPass(PR);
203   initializeHexagonOptAddrModePass(PR);
204   initializeHexagonPacketizerPass(PR);
205   initializeHexagonRDFOptPass(PR);
206   initializeHexagonSplitDoubleRegsPass(PR);
207   initializeHexagonVExtractPass(PR);
208 }
209 
210 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
211                                            StringRef CPU, StringRef FS,
212                                            const TargetOptions &Options,
213                                            Optional<Reloc::Model> RM,
214                                            Optional<CodeModel::Model> CM,
215                                            CodeGenOpt::Level OL, bool JIT)
216     // Specify the vector alignment explicitly. For v512x1, the calculated
217     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
218     // the required minimum of 64 bytes.
219     : LLVMTargetMachine(
220           T,
221           "e-m:e-p:32:32:32-a:0-n16:32-"
222           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
223           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
224           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
225           getEffectiveCodeModel(CM, CodeModel::Small),
226           (HexagonNoOpt ? CodeGenOpt::None : OL)),
227       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
228   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
229   initAsmInfo();
230 }
231 
232 const HexagonSubtarget *
233 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
234   AttributeList FnAttrs = F.getAttributes();
235   Attribute CPUAttr =
236       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
237   Attribute FSAttr =
238       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
239 
240   std::string CPU =
241       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
242   std::string FS =
243       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
244   // Append the preexisting target features last, so that +mattr overrides
245   // the "unsafe-fp-math" function attribute.
246   // Creating a separate target feature is not strictly necessary, it only
247   // exists to make "unsafe-fp-math" force creating a new subtarget.
248 
249   if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
250       F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
251     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
252 
253   auto &I = SubtargetMap[CPU + FS];
254   if (!I) {
255     // This needs to be done before we create a new subtarget since any
256     // creation will depend on the TM and the code generation flags on the
257     // function that reside in TargetOptions.
258     resetTargetOptions(F);
259     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
260   }
261   return I.get();
262 }
263 
264 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
265   PMB.addExtension(
266     PassManagerBuilder::EP_LateLoopOptimizations,
267     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
268       PM.add(createHexagonLoopIdiomPass());
269     });
270   PMB.addExtension(
271       PassManagerBuilder::EP_LoopOptimizerEnd,
272       [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
273         PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
274       });
275 }
276 
277 void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
278                                                         bool DebugPassManager) {
279   PB.registerOptimizerLastEPCallback(
280       [=](ModulePassManager &MPM, PassBuilder::OptimizationLevel Level) {
281         LoopPassManager LPM(DebugPassManager);
282         FunctionPassManager FPM(DebugPassManager);
283         LPM.addPass(HexagonVectorLoopCarriedReusePass());
284         FPM.addPass(createFunctionToLoopPassAdaptor(std::move(LPM)));
285         MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
286       });
287 }
288 
289 TargetTransformInfo
290 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
291   return TargetTransformInfo(HexagonTTIImpl(this, F));
292 }
293 
294 
295 HexagonTargetMachine::~HexagonTargetMachine() {}
296 
297 namespace {
298 /// Hexagon Code Generator Pass Configuration Options.
299 class HexagonPassConfig : public TargetPassConfig {
300 public:
301   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
302     : TargetPassConfig(TM, PM) {}
303 
304   HexagonTargetMachine &getHexagonTargetMachine() const {
305     return getTM<HexagonTargetMachine>();
306   }
307 
308   ScheduleDAGInstrs *
309   createMachineScheduler(MachineSchedContext *C) const override {
310     return createVLIWMachineSched(C);
311   }
312 
313   void addIRPasses() override;
314   bool addInstSelector() override;
315   void addPreRegAlloc() override;
316   void addPostRegAlloc() override;
317   void addPreSched2() override;
318   void addPreEmitPass() override;
319 };
320 } // namespace
321 
322 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
323   return new HexagonPassConfig(*this, PM);
324 }
325 
326 void HexagonPassConfig::addIRPasses() {
327   TargetPassConfig::addIRPasses();
328   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
329 
330   if (!NoOpt) {
331     if (EnableInstSimplify)
332       addPass(createInstSimplifyLegacyPass());
333     addPass(createDeadCodeEliminationPass());
334   }
335 
336   addPass(createAtomicExpandPass());
337 
338   if (!NoOpt) {
339     if (EnableInitialCFGCleanup)
340       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
341                                               .forwardSwitchCondToPhi(true)
342                                               .convertSwitchToLookupTable(true)
343                                               .needCanonicalLoops(false)
344                                               .hoistCommonInsts(true)
345                                               .sinkCommonInsts(true)));
346     if (EnableLoopPrefetch)
347       addPass(createLoopDataPrefetchPass());
348     if (EnableCommGEP)
349       addPass(createHexagonCommonGEP());
350     // Replace certain combinations of shifts and ands with extracts.
351     if (EnableGenExtract)
352       addPass(createHexagonGenExtract());
353   }
354 }
355 
356 bool HexagonPassConfig::addInstSelector() {
357   HexagonTargetMachine &TM = getHexagonTargetMachine();
358   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
359 
360   if (!NoOpt)
361     addPass(createHexagonOptimizeSZextends());
362 
363   addPass(createHexagonISelDag(TM, getOptLevel()));
364 
365   if (!NoOpt) {
366     if (EnableVExtractOpt)
367       addPass(createHexagonVExtract());
368     // Create logical operations on predicate registers.
369     if (EnableGenPred)
370       addPass(createHexagonGenPredicate());
371     // Rotate loops to expose bit-simplification opportunities.
372     if (EnableLoopResched)
373       addPass(createHexagonLoopRescheduling());
374     // Split double registers.
375     if (!DisableHSDR)
376       addPass(createHexagonSplitDoubleRegs());
377     // Bit simplification.
378     if (EnableBitSimplify)
379       addPass(createHexagonBitSimplify());
380     addPass(createHexagonPeephole());
381     // Constant propagation.
382     if (!DisableHCP) {
383       addPass(createHexagonConstPropagationPass());
384       addPass(&UnreachableMachineBlockElimID);
385     }
386     if (EnableGenInsert)
387       addPass(createHexagonGenInsert());
388     if (EnableEarlyIf)
389       addPass(createHexagonEarlyIfConversion());
390   }
391 
392   return false;
393 }
394 
395 void HexagonPassConfig::addPreRegAlloc() {
396   if (getOptLevel() != CodeGenOpt::None) {
397     if (EnableCExtOpt)
398       addPass(createHexagonConstExtenders());
399     if (EnableExpandCondsets)
400       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
401     if (!DisableStoreWidening)
402       addPass(createHexagonStoreWidening());
403     if (!DisableHardwareLoops)
404       addPass(createHexagonHardwareLoops());
405   }
406   if (TM->getOptLevel() >= CodeGenOpt::Default)
407     addPass(&MachinePipelinerID);
408 }
409 
410 void HexagonPassConfig::addPostRegAlloc() {
411   if (getOptLevel() != CodeGenOpt::None) {
412     if (EnableRDFOpt)
413       addPass(createHexagonRDFOpt());
414     if (!DisableHexagonCFGOpt)
415       addPass(createHexagonCFGOptimizer());
416     if (!DisableAModeOpt)
417       addPass(createHexagonOptAddrMode());
418   }
419 }
420 
421 void HexagonPassConfig::addPreSched2() {
422   addPass(createHexagonCopyToCombine());
423   if (getOptLevel() != CodeGenOpt::None)
424     addPass(&IfConverterID);
425   addPass(createHexagonSplitConst32AndConst64());
426 }
427 
428 void HexagonPassConfig::addPreEmitPass() {
429   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
430 
431   if (!NoOpt)
432     addPass(createHexagonNewValueJump());
433 
434   addPass(createHexagonBranchRelaxation());
435 
436   if (!NoOpt) {
437     if (!DisableHardwareLoops)
438       addPass(createHexagonFixupHwLoops());
439     // Generate MUX from pairs of conditional transfers.
440     if (EnableGenMux)
441       addPass(createHexagonGenMux());
442   }
443 
444   // Packetization is mandatory: it handles gather/scatter at all opt levels.
445   addPass(createHexagonPacketizer(NoOpt), false);
446 
447   if (EnableVectorPrint)
448     addPass(createHexagonVectorPrint(), false);
449 
450   // Add CFI instructions if necessary.
451   addPass(createHexagonCallFrameInformation(), false);
452 }
453