1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonLoopIdiomRecognition.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "HexagonVectorLoopCarriedReuse.h"
21 #include "TargetInfo/HexagonTargetInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/LegacyPassManager.h"
25 #include "llvm/IR/Module.h"
26 #include "llvm/Passes/PassBuilder.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
30 #include "llvm/Transforms/Scalar.h"
31 
32 using namespace llvm;
33 
34 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
36 
37 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
38   cl::init(true), cl::desc("Enable RDF-based optimizations"));
39 
40 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
41   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
42 
43 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
44   cl::Hidden, cl::ZeroOrMore, cl::init(false),
45   cl::desc("Disable Hexagon Addressing Mode Optimization"));
46 
47 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
48   cl::Hidden, cl::ZeroOrMore, cl::init(false),
49   cl::desc("Disable Hexagon CFG Optimization"));
50 
51 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
52   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
53 
54 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
55   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
56 
57 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
58   cl::init(true), cl::Hidden, cl::ZeroOrMore,
59   cl::desc("Early expansion of MUX"));
60 
61 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
62   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
63 
64 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
66 
67 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
68   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
69 
70 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
71   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
72 
73 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
74   cl::desc("Enable converting conditional transfers into MUX instructions"));
75 
76 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
77   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
78   "predicate instructions"));
79 
80 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
81   cl::init(false), cl::Hidden, cl::ZeroOrMore,
82   cl::desc("Enable loop data prefetch on Hexagon"));
83 
84 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
85   cl::desc("Disable splitting double registers"));
86 
87 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
88   cl::Hidden, cl::desc("Bit simplification"));
89 
90 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
91   cl::Hidden, cl::desc("Loop rescheduling"));
92 
93 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
94   cl::Hidden, cl::desc("Disable backend optimizations"));
95 
96 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
97   cl::Hidden, cl::ZeroOrMore, cl::init(false),
98   cl::desc("Enable Hexagon Vector print instr pass"));
99 
100 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
101   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
102 
103 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
104   cl::Hidden, cl::ZeroOrMore, cl::init(true),
105   cl::desc("Simplify the CFG after atomic expansion pass"));
106 
107 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
108                                         cl::ZeroOrMore, cl::init(true),
109                                         cl::desc("Enable instsimplify"));
110 
111 /// HexagonTargetMachineModule - Note that this is used on hosts that
112 /// cannot link in a library unless there are references into the
113 /// library.  In particular, it seems that it is not possible to get
114 /// things to work on Win32 without this.  Though it is unused, do not
115 /// remove it.
116 extern "C" int HexagonTargetMachineModule;
117 int HexagonTargetMachineModule = 0;
118 
119 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
120   ScheduleDAGMILive *DAG =
121     new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
122   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
123   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
124   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
125   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
126   return DAG;
127 }
128 
129 static MachineSchedRegistry
130 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
131                     createVLIWMachineSched);
132 
133 namespace llvm {
134   extern char &HexagonExpandCondsetsID;
135   void initializeHexagonBitSimplifyPass(PassRegistry&);
136   void initializeHexagonConstExtendersPass(PassRegistry&);
137   void initializeHexagonConstPropagationPass(PassRegistry&);
138   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
139   void initializeHexagonExpandCondsetsPass(PassRegistry&);
140   void initializeHexagonGenMuxPass(PassRegistry&);
141   void initializeHexagonHardwareLoopsPass(PassRegistry&);
142   void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
143   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
144   void initializeHexagonNewValueJumpPass(PassRegistry&);
145   void initializeHexagonOptAddrModePass(PassRegistry&);
146   void initializeHexagonPacketizerPass(PassRegistry&);
147   void initializeHexagonRDFOptPass(PassRegistry&);
148   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
149   void initializeHexagonVExtractPass(PassRegistry&);
150   Pass *createHexagonLoopIdiomPass();
151   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
152 
153   FunctionPass *createHexagonBitSimplify();
154   FunctionPass *createHexagonBranchRelaxation();
155   FunctionPass *createHexagonCallFrameInformation();
156   FunctionPass *createHexagonCFGOptimizer();
157   FunctionPass *createHexagonCommonGEP();
158   FunctionPass *createHexagonConstExtenders();
159   FunctionPass *createHexagonConstPropagationPass();
160   FunctionPass *createHexagonCopyToCombine();
161   FunctionPass *createHexagonEarlyIfConversion();
162   FunctionPass *createHexagonFixupHwLoops();
163   FunctionPass *createHexagonGenExtract();
164   FunctionPass *createHexagonGenInsert();
165   FunctionPass *createHexagonGenMux();
166   FunctionPass *createHexagonGenPredicate();
167   FunctionPass *createHexagonHardwareLoops();
168   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
169                                      CodeGenOpt::Level OptLevel);
170   FunctionPass *createHexagonLoopRescheduling();
171   FunctionPass *createHexagonNewValueJump();
172   FunctionPass *createHexagonOptimizeSZextends();
173   FunctionPass *createHexagonOptAddrMode();
174   FunctionPass *createHexagonPacketizer(bool Minimal);
175   FunctionPass *createHexagonPeephole();
176   FunctionPass *createHexagonRDFOpt();
177   FunctionPass *createHexagonSplitConst32AndConst64();
178   FunctionPass *createHexagonSplitDoubleRegs();
179   FunctionPass *createHexagonStoreWidening();
180   FunctionPass *createHexagonVectorPrint();
181   FunctionPass *createHexagonVExtract();
182 } // end namespace llvm;
183 
184 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
185   if (!RM.hasValue())
186     return Reloc::Static;
187   return *RM;
188 }
189 
190 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
191   // Register the target.
192   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
193 
194   PassRegistry &PR = *PassRegistry::getPassRegistry();
195   initializeHexagonBitSimplifyPass(PR);
196   initializeHexagonConstExtendersPass(PR);
197   initializeHexagonConstPropagationPass(PR);
198   initializeHexagonEarlyIfConversionPass(PR);
199   initializeHexagonGenMuxPass(PR);
200   initializeHexagonHardwareLoopsPass(PR);
201   initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
202   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
203   initializeHexagonNewValueJumpPass(PR);
204   initializeHexagonOptAddrModePass(PR);
205   initializeHexagonPacketizerPass(PR);
206   initializeHexagonRDFOptPass(PR);
207   initializeHexagonSplitDoubleRegsPass(PR);
208   initializeHexagonVExtractPass(PR);
209 }
210 
211 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
212                                            StringRef CPU, StringRef FS,
213                                            const TargetOptions &Options,
214                                            Optional<Reloc::Model> RM,
215                                            Optional<CodeModel::Model> CM,
216                                            CodeGenOpt::Level OL, bool JIT)
217     // Specify the vector alignment explicitly. For v512x1, the calculated
218     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
219     // the required minimum of 64 bytes.
220     : LLVMTargetMachine(
221           T,
222           "e-m:e-p:32:32:32-a:0-n16:32-"
223           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
224           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
225           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
226           getEffectiveCodeModel(CM, CodeModel::Small),
227           (HexagonNoOpt ? CodeGenOpt::None : OL)),
228       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
229   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
230   initAsmInfo();
231 }
232 
233 const HexagonSubtarget *
234 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
235   AttributeList FnAttrs = F.getAttributes();
236   Attribute CPUAttr =
237       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
238   Attribute FSAttr =
239       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
240 
241   std::string CPU =
242       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
243   std::string FS =
244       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
245   // Append the preexisting target features last, so that +mattr overrides
246   // the "unsafe-fp-math" function attribute.
247   // Creating a separate target feature is not strictly necessary, it only
248   // exists to make "unsafe-fp-math" force creating a new subtarget.
249 
250   if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
251       F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
252     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
253 
254   auto &I = SubtargetMap[CPU + FS];
255   if (!I) {
256     // This needs to be done before we create a new subtarget since any
257     // creation will depend on the TM and the code generation flags on the
258     // function that reside in TargetOptions.
259     resetTargetOptions(F);
260     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
261   }
262   return I.get();
263 }
264 
265 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
266   PMB.addExtension(
267     PassManagerBuilder::EP_LateLoopOptimizations,
268     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
269       PM.add(createHexagonLoopIdiomPass());
270     });
271   PMB.addExtension(
272       PassManagerBuilder::EP_LoopOptimizerEnd,
273       [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
274         PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
275       });
276 }
277 
278 void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
279                                                         bool DebugPassManager) {
280   PB.registerLateLoopOptimizationsEPCallback(
281       [=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) {
282         LPM.addPass(HexagonLoopIdiomRecognitionPass());
283       });
284   PB.registerOptimizerLastEPCallback(
285       [=](ModulePassManager &MPM, PassBuilder::OptimizationLevel Level) {
286         LoopPassManager LPM(DebugPassManager);
287         FunctionPassManager FPM(DebugPassManager);
288         LPM.addPass(HexagonVectorLoopCarriedReusePass());
289         FPM.addPass(createFunctionToLoopPassAdaptor(std::move(LPM)));
290         MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
291       });
292 }
293 
294 TargetTransformInfo
295 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
296   return TargetTransformInfo(HexagonTTIImpl(this, F));
297 }
298 
299 
300 HexagonTargetMachine::~HexagonTargetMachine() {}
301 
302 namespace {
303 /// Hexagon Code Generator Pass Configuration Options.
304 class HexagonPassConfig : public TargetPassConfig {
305 public:
306   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
307     : TargetPassConfig(TM, PM) {}
308 
309   HexagonTargetMachine &getHexagonTargetMachine() const {
310     return getTM<HexagonTargetMachine>();
311   }
312 
313   ScheduleDAGInstrs *
314   createMachineScheduler(MachineSchedContext *C) const override {
315     return createVLIWMachineSched(C);
316   }
317 
318   void addIRPasses() override;
319   bool addInstSelector() override;
320   void addPreRegAlloc() override;
321   void addPostRegAlloc() override;
322   void addPreSched2() override;
323   void addPreEmitPass() override;
324 };
325 } // namespace
326 
327 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
328   return new HexagonPassConfig(*this, PM);
329 }
330 
331 void HexagonPassConfig::addIRPasses() {
332   TargetPassConfig::addIRPasses();
333   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
334 
335   if (!NoOpt) {
336     if (EnableInstSimplify)
337       addPass(createInstSimplifyLegacyPass());
338     addPass(createDeadCodeEliminationPass());
339   }
340 
341   addPass(createAtomicExpandPass());
342 
343   if (!NoOpt) {
344     if (EnableInitialCFGCleanup)
345       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
346                                               .forwardSwitchCondToPhi(true)
347                                               .convertSwitchToLookupTable(true)
348                                               .needCanonicalLoops(false)
349                                               .hoistCommonInsts(true)
350                                               .sinkCommonInsts(true)));
351     if (EnableLoopPrefetch)
352       addPass(createLoopDataPrefetchPass());
353     if (EnableCommGEP)
354       addPass(createHexagonCommonGEP());
355     // Replace certain combinations of shifts and ands with extracts.
356     if (EnableGenExtract)
357       addPass(createHexagonGenExtract());
358   }
359 }
360 
361 bool HexagonPassConfig::addInstSelector() {
362   HexagonTargetMachine &TM = getHexagonTargetMachine();
363   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
364 
365   if (!NoOpt)
366     addPass(createHexagonOptimizeSZextends());
367 
368   addPass(createHexagonISelDag(TM, getOptLevel()));
369 
370   if (!NoOpt) {
371     if (EnableVExtractOpt)
372       addPass(createHexagonVExtract());
373     // Create logical operations on predicate registers.
374     if (EnableGenPred)
375       addPass(createHexagonGenPredicate());
376     // Rotate loops to expose bit-simplification opportunities.
377     if (EnableLoopResched)
378       addPass(createHexagonLoopRescheduling());
379     // Split double registers.
380     if (!DisableHSDR)
381       addPass(createHexagonSplitDoubleRegs());
382     // Bit simplification.
383     if (EnableBitSimplify)
384       addPass(createHexagonBitSimplify());
385     addPass(createHexagonPeephole());
386     // Constant propagation.
387     if (!DisableHCP) {
388       addPass(createHexagonConstPropagationPass());
389       addPass(&UnreachableMachineBlockElimID);
390     }
391     if (EnableGenInsert)
392       addPass(createHexagonGenInsert());
393     if (EnableEarlyIf)
394       addPass(createHexagonEarlyIfConversion());
395   }
396 
397   return false;
398 }
399 
400 void HexagonPassConfig::addPreRegAlloc() {
401   if (getOptLevel() != CodeGenOpt::None) {
402     if (EnableCExtOpt)
403       addPass(createHexagonConstExtenders());
404     if (EnableExpandCondsets)
405       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
406     if (!DisableStoreWidening)
407       addPass(createHexagonStoreWidening());
408     if (!DisableHardwareLoops)
409       addPass(createHexagonHardwareLoops());
410   }
411   if (TM->getOptLevel() >= CodeGenOpt::Default)
412     addPass(&MachinePipelinerID);
413 }
414 
415 void HexagonPassConfig::addPostRegAlloc() {
416   if (getOptLevel() != CodeGenOpt::None) {
417     if (EnableRDFOpt)
418       addPass(createHexagonRDFOpt());
419     if (!DisableHexagonCFGOpt)
420       addPass(createHexagonCFGOptimizer());
421     if (!DisableAModeOpt)
422       addPass(createHexagonOptAddrMode());
423   }
424 }
425 
426 void HexagonPassConfig::addPreSched2() {
427   addPass(createHexagonCopyToCombine());
428   if (getOptLevel() != CodeGenOpt::None)
429     addPass(&IfConverterID);
430   addPass(createHexagonSplitConst32AndConst64());
431 }
432 
433 void HexagonPassConfig::addPreEmitPass() {
434   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
435 
436   if (!NoOpt)
437     addPass(createHexagonNewValueJump());
438 
439   addPass(createHexagonBranchRelaxation());
440 
441   if (!NoOpt) {
442     if (!DisableHardwareLoops)
443       addPass(createHexagonFixupHwLoops());
444     // Generate MUX from pairs of conditional transfers.
445     if (EnableGenMux)
446       addPass(createHexagonGenMux());
447   }
448 
449   // Packetization is mandatory: it handles gather/scatter at all opt levels.
450   addPass(createHexagonPacketizer(NoOpt), false);
451 
452   if (EnableVectorPrint)
453     addPass(createHexagonVectorPrint(), false);
454 
455   // Add CFI instructions if necessary.
456   addPass(createHexagonCallFrameInformation(), false);
457 }
458