1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableTrapUnreachable("hexagon-trap-unreachable",
98   cl::Hidden, cl::ZeroOrMore, cl::init(false),
99   cl::desc("Enable generating trap for unreachable"));
100 
101 /// HexagonTargetMachineModule - Note that this is used on hosts that
102 /// cannot link in a library unless there are references into the
103 /// library.  In particular, it seems that it is not possible to get
104 /// things to work on Win32 without this.  Though it is unused, do not
105 /// remove it.
106 extern "C" int HexagonTargetMachineModule;
107 int HexagonTargetMachineModule = 0;
108 
109 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
110   ScheduleDAGMILive *DAG =
111     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
112   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
113   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
114   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
115   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
116   return DAG;
117 }
118 
119 static MachineSchedRegistry
120 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
121                     createVLIWMachineSched);
122 
123 namespace llvm {
124   extern char &HexagonExpandCondsetsID;
125   void initializeHexagonConstExtendersPass(PassRegistry&);
126   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
127   void initializeHexagonExpandCondsetsPass(PassRegistry&);
128   void initializeHexagonGenMuxPass(PassRegistry&);
129   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
130   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
131   void initializeHexagonNewValueJumpPass(PassRegistry&);
132   void initializeHexagonOptAddrModePass(PassRegistry&);
133   void initializeHexagonPacketizerPass(PassRegistry&);
134   Pass *createHexagonLoopIdiomPass();
135   Pass *createHexagonVectorLoopCarriedReusePass();
136 
137   FunctionPass *createHexagonBitSimplify();
138   FunctionPass *createHexagonBranchRelaxation();
139   FunctionPass *createHexagonCallFrameInformation();
140   FunctionPass *createHexagonCFGOptimizer();
141   FunctionPass *createHexagonCommonGEP();
142   FunctionPass *createHexagonConstExtenders();
143   FunctionPass *createHexagonConstPropagationPass();
144   FunctionPass *createHexagonCopyToCombine();
145   FunctionPass *createHexagonEarlyIfConversion();
146   FunctionPass *createHexagonFixupHwLoops();
147   FunctionPass *createHexagonGenExtract();
148   FunctionPass *createHexagonGenInsert();
149   FunctionPass *createHexagonGenMux();
150   FunctionPass *createHexagonGenPredicate();
151   FunctionPass *createHexagonHardwareLoops();
152   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
153                                      CodeGenOpt::Level OptLevel);
154   FunctionPass *createHexagonLoopRescheduling();
155   FunctionPass *createHexagonNewValueJump();
156   FunctionPass *createHexagonOptimizeSZextends();
157   FunctionPass *createHexagonOptAddrMode();
158   FunctionPass *createHexagonPacketizer();
159   FunctionPass *createHexagonPeephole();
160   FunctionPass *createHexagonRDFOpt();
161   FunctionPass *createHexagonSplitConst32AndConst64();
162   FunctionPass *createHexagonSplitDoubleRegs();
163   FunctionPass *createHexagonStoreWidening();
164   FunctionPass *createHexagonVectorPrint();
165 } // end namespace llvm;
166 
167 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
168   if (!RM.hasValue())
169     return Reloc::Static;
170   return *RM;
171 }
172 
173 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
174   if (CM)
175     return *CM;
176   return CodeModel::Small;
177 }
178 
179 extern "C" void LLVMInitializeHexagonTarget() {
180   // Register the target.
181   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
182 
183   PassRegistry &PR = *PassRegistry::getPassRegistry();
184   initializeHexagonConstExtendersPass(PR);
185   initializeHexagonEarlyIfConversionPass(PR);
186   initializeHexagonGenMuxPass(PR);
187   initializeHexagonLoopIdiomRecognizePass(PR);
188   initializeHexagonVectorLoopCarriedReusePass(PR);
189   initializeHexagonNewValueJumpPass(PR);
190   initializeHexagonOptAddrModePass(PR);
191   initializeHexagonPacketizerPass(PR);
192 }
193 
194 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
195                                            StringRef CPU, StringRef FS,
196                                            const TargetOptions &Options,
197                                            Optional<Reloc::Model> RM,
198                                            Optional<CodeModel::Model> CM,
199                                            CodeGenOpt::Level OL, bool JIT)
200     // Specify the vector alignment explicitly. For v512x1, the calculated
201     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
202     // the required minimum of 64 bytes.
203     : LLVMTargetMachine(
204           T,
205           "e-m:e-p:32:32:32-a:0-n16:32-"
206           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
207           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
208           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
209           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
210       TLOF(make_unique<HexagonTargetObjectFile>()) {
211   if (EnableTrapUnreachable)
212     this->Options.TrapUnreachable = true;
213   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
214   initAsmInfo();
215 }
216 
217 const HexagonSubtarget *
218 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
219   AttributeList FnAttrs = F.getAttributes();
220   Attribute CPUAttr =
221       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
222   Attribute FSAttr =
223       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
224 
225   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
226                         ? CPUAttr.getValueAsString().str()
227                         : TargetCPU;
228   std::string FS = !FSAttr.hasAttribute(Attribute::None)
229                        ? FSAttr.getValueAsString().str()
230                        : TargetFS;
231 
232   auto &I = SubtargetMap[CPU + FS];
233   if (!I) {
234     // This needs to be done before we create a new subtarget since any
235     // creation will depend on the TM and the code generation flags on the
236     // function that reside in TargetOptions.
237     resetTargetOptions(F);
238     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
239   }
240   return I.get();
241 }
242 
243 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
244   PMB.addExtension(
245     PassManagerBuilder::EP_LateLoopOptimizations,
246     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
247       PM.add(createHexagonLoopIdiomPass());
248     });
249   PMB.addExtension(
250     PassManagerBuilder::EP_LoopOptimizerEnd,
251     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
252       PM.add(createHexagonVectorLoopCarriedReusePass());
253     });
254 }
255 
256 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
257   return TargetIRAnalysis([this](const Function &F) {
258     return TargetTransformInfo(HexagonTTIImpl(this, F));
259   });
260 }
261 
262 
263 HexagonTargetMachine::~HexagonTargetMachine() {}
264 
265 namespace {
266 /// Hexagon Code Generator Pass Configuration Options.
267 class HexagonPassConfig : public TargetPassConfig {
268 public:
269   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
270     : TargetPassConfig(TM, PM) {}
271 
272   HexagonTargetMachine &getHexagonTargetMachine() const {
273     return getTM<HexagonTargetMachine>();
274   }
275 
276   ScheduleDAGInstrs *
277   createMachineScheduler(MachineSchedContext *C) const override {
278     return createVLIWMachineSched(C);
279   }
280 
281   void addIRPasses() override;
282   bool addInstSelector() override;
283   void addPreRegAlloc() override;
284   void addPostRegAlloc() override;
285   void addPreSched2() override;
286   void addPreEmitPass() override;
287 };
288 } // namespace
289 
290 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
291   return new HexagonPassConfig(*this, PM);
292 }
293 
294 void HexagonPassConfig::addIRPasses() {
295   TargetPassConfig::addIRPasses();
296   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
297 
298   addPass(createAtomicExpandPass());
299   if (!NoOpt) {
300     if (EnableLoopPrefetch)
301       addPass(createLoopDataPrefetchPass());
302     if (EnableCommGEP)
303       addPass(createHexagonCommonGEP());
304     // Replace certain combinations of shifts and ands with extracts.
305     if (EnableGenExtract)
306       addPass(createHexagonGenExtract());
307   }
308 }
309 
310 bool HexagonPassConfig::addInstSelector() {
311   HexagonTargetMachine &TM = getHexagonTargetMachine();
312   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
313 
314   if (!NoOpt)
315     addPass(createHexagonOptimizeSZextends());
316 
317   addPass(createHexagonISelDag(TM, getOptLevel()));
318 
319   if (!NoOpt) {
320     // Create logical operations on predicate registers.
321     if (EnableGenPred)
322       addPass(createHexagonGenPredicate());
323     // Rotate loops to expose bit-simplification opportunities.
324     if (EnableLoopResched)
325       addPass(createHexagonLoopRescheduling());
326     // Split double registers.
327     if (!DisableHSDR)
328       addPass(createHexagonSplitDoubleRegs());
329     // Bit simplification.
330     if (EnableBitSimplify)
331       addPass(createHexagonBitSimplify());
332     addPass(createHexagonPeephole());
333     // Constant propagation.
334     if (!DisableHCP) {
335       addPass(createHexagonConstPropagationPass());
336       addPass(&UnreachableMachineBlockElimID);
337     }
338     if (EnableGenInsert)
339       addPass(createHexagonGenInsert());
340     if (EnableEarlyIf)
341       addPass(createHexagonEarlyIfConversion());
342   }
343 
344   return false;
345 }
346 
347 void HexagonPassConfig::addPreRegAlloc() {
348   if (getOptLevel() != CodeGenOpt::None) {
349     if (EnableCExtOpt)
350       addPass(createHexagonConstExtenders());
351     if (EnableExpandCondsets)
352       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
353     if (!DisableStoreWidening)
354       addPass(createHexagonStoreWidening());
355     if (!DisableHardwareLoops)
356       addPass(createHexagonHardwareLoops());
357   }
358   if (TM->getOptLevel() >= CodeGenOpt::Default)
359     addPass(&MachinePipelinerID);
360 }
361 
362 void HexagonPassConfig::addPostRegAlloc() {
363   if (getOptLevel() != CodeGenOpt::None) {
364     if (EnableRDFOpt)
365       addPass(createHexagonRDFOpt());
366     if (!DisableHexagonCFGOpt)
367       addPass(createHexagonCFGOptimizer());
368     if (!DisableAModeOpt)
369       addPass(createHexagonOptAddrMode());
370   }
371 }
372 
373 void HexagonPassConfig::addPreSched2() {
374   addPass(createHexagonCopyToCombine());
375   if (getOptLevel() != CodeGenOpt::None)
376     addPass(&IfConverterID);
377   addPass(createHexagonSplitConst32AndConst64());
378 }
379 
380 void HexagonPassConfig::addPreEmitPass() {
381   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
382 
383   if (!NoOpt)
384     addPass(createHexagonNewValueJump());
385 
386   addPass(createHexagonBranchRelaxation());
387 
388   // Create Packets.
389   if (!NoOpt) {
390     if (!DisableHardwareLoops)
391       addPass(createHexagonFixupHwLoops());
392     // Generate MUX from pairs of conditional transfers.
393     if (EnableGenMux)
394       addPass(createHexagonGenMux());
395 
396     addPass(createHexagonPacketizer(), false);
397   }
398   if (EnableVectorPrint)
399     addPass(createHexagonVectorPrint(), false);
400 
401   // Add CFI instructions if necessary.
402   addPass(createHexagonCallFrameInformation(), false);
403 }
404