1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 /// HexagonTargetMachineModule - Note that this is used on hosts that
101 /// cannot link in a library unless there are references into the
102 /// library.  In particular, it seems that it is not possible to get
103 /// things to work on Win32 without this.  Though it is unused, do not
104 /// remove it.
105 extern "C" int HexagonTargetMachineModule;
106 int HexagonTargetMachineModule = 0;
107 
108 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
109   ScheduleDAGMILive *DAG =
110     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
111   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
112   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
113   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
114   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
115   return DAG;
116 }
117 
118 static MachineSchedRegistry
119 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
120                     createVLIWMachineSched);
121 
122 namespace llvm {
123   extern char &HexagonExpandCondsetsID;
124   void initializeHexagonBitSimplifyPass(PassRegistry&);
125   void initializeHexagonConstExtendersPass(PassRegistry&);
126   void initializeHexagonConstPropagationPass(PassRegistry&);
127   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
128   void initializeHexagonExpandCondsetsPass(PassRegistry&);
129   void initializeHexagonGenMuxPass(PassRegistry&);
130   void initializeHexagonHardwareLoopsPass(PassRegistry&);
131   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
132   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
133   void initializeHexagonNewValueJumpPass(PassRegistry&);
134   void initializeHexagonOptAddrModePass(PassRegistry&);
135   void initializeHexagonPacketizerPass(PassRegistry&);
136   void initializeHexagonRDFOptPass(PassRegistry&);
137   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
138   void initializeHexagonVExtractPass(PassRegistry&);
139   Pass *createHexagonLoopIdiomPass();
140   Pass *createHexagonVectorLoopCarriedReusePass();
141 
142   FunctionPass *createHexagonBitSimplify();
143   FunctionPass *createHexagonBranchRelaxation();
144   FunctionPass *createHexagonCallFrameInformation();
145   FunctionPass *createHexagonCFGOptimizer();
146   FunctionPass *createHexagonCommonGEP();
147   FunctionPass *createHexagonConstExtenders();
148   FunctionPass *createHexagonConstPropagationPass();
149   FunctionPass *createHexagonCopyToCombine();
150   FunctionPass *createHexagonEarlyIfConversion();
151   FunctionPass *createHexagonFixupHwLoops();
152   FunctionPass *createHexagonGatherPacketize();
153   FunctionPass *createHexagonGenExtract();
154   FunctionPass *createHexagonGenInsert();
155   FunctionPass *createHexagonGenMux();
156   FunctionPass *createHexagonGenPredicate();
157   FunctionPass *createHexagonHardwareLoops();
158   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
159                                      CodeGenOpt::Level OptLevel);
160   FunctionPass *createHexagonLoopRescheduling();
161   FunctionPass *createHexagonNewValueJump();
162   FunctionPass *createHexagonOptimizeSZextends();
163   FunctionPass *createHexagonOptAddrMode();
164   FunctionPass *createHexagonPacketizer();
165   FunctionPass *createHexagonPeephole();
166   FunctionPass *createHexagonRDFOpt();
167   FunctionPass *createHexagonSplitConst32AndConst64();
168   FunctionPass *createHexagonSplitDoubleRegs();
169   FunctionPass *createHexagonStoreWidening();
170   FunctionPass *createHexagonVectorPrint();
171   FunctionPass *createHexagonVExtract();
172 } // end namespace llvm;
173 
174 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
175   if (!RM.hasValue())
176     return Reloc::Static;
177   return *RM;
178 }
179 
180 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
181   if (CM)
182     return *CM;
183   return CodeModel::Small;
184 }
185 
186 extern "C" void LLVMInitializeHexagonTarget() {
187   // Register the target.
188   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
189 
190   PassRegistry &PR = *PassRegistry::getPassRegistry();
191   initializeHexagonBitSimplifyPass(PR);
192   initializeHexagonConstExtendersPass(PR);
193   initializeHexagonConstPropagationPass(PR);
194   initializeHexagonEarlyIfConversionPass(PR);
195   initializeHexagonGenMuxPass(PR);
196   initializeHexagonHardwareLoopsPass(PR);
197   initializeHexagonLoopIdiomRecognizePass(PR);
198   initializeHexagonVectorLoopCarriedReusePass(PR);
199   initializeHexagonNewValueJumpPass(PR);
200   initializeHexagonOptAddrModePass(PR);
201   initializeHexagonPacketizerPass(PR);
202   initializeHexagonRDFOptPass(PR);
203   initializeHexagonSplitDoubleRegsPass(PR);
204   initializeHexagonVExtractPass(PR);
205 }
206 
207 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
208                                            StringRef CPU, StringRef FS,
209                                            const TargetOptions &Options,
210                                            Optional<Reloc::Model> RM,
211                                            Optional<CodeModel::Model> CM,
212                                            CodeGenOpt::Level OL, bool JIT)
213     // Specify the vector alignment explicitly. For v512x1, the calculated
214     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
215     // the required minimum of 64 bytes.
216     : LLVMTargetMachine(
217           T,
218           "e-m:e-p:32:32:32-a:0-n16:32-"
219           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
220           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
221           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
222           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
223       TLOF(make_unique<HexagonTargetObjectFile>()) {
224   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
225   initAsmInfo();
226 }
227 
228 const HexagonSubtarget *
229 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
230   AttributeList FnAttrs = F.getAttributes();
231   Attribute CPUAttr =
232       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
233   Attribute FSAttr =
234       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
235 
236   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
237                         ? CPUAttr.getValueAsString().str()
238                         : TargetCPU;
239   std::string FS = !FSAttr.hasAttribute(Attribute::None)
240                        ? FSAttr.getValueAsString().str()
241                        : TargetFS;
242 
243   auto &I = SubtargetMap[CPU + FS];
244   if (!I) {
245     // This needs to be done before we create a new subtarget since any
246     // creation will depend on the TM and the code generation flags on the
247     // function that reside in TargetOptions.
248     resetTargetOptions(F);
249     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
250   }
251   return I.get();
252 }
253 
254 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
255   PMB.addExtension(
256     PassManagerBuilder::EP_LateLoopOptimizations,
257     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
258       PM.add(createHexagonLoopIdiomPass());
259     });
260   PMB.addExtension(
261     PassManagerBuilder::EP_LoopOptimizerEnd,
262     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
263       PM.add(createHexagonVectorLoopCarriedReusePass());
264     });
265 }
266 
267 TargetTransformInfo
268 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
269   return TargetTransformInfo(HexagonTTIImpl(this, F));
270 }
271 
272 
273 HexagonTargetMachine::~HexagonTargetMachine() {}
274 
275 namespace {
276 /// Hexagon Code Generator Pass Configuration Options.
277 class HexagonPassConfig : public TargetPassConfig {
278 public:
279   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
280     : TargetPassConfig(TM, PM) {}
281 
282   HexagonTargetMachine &getHexagonTargetMachine() const {
283     return getTM<HexagonTargetMachine>();
284   }
285 
286   ScheduleDAGInstrs *
287   createMachineScheduler(MachineSchedContext *C) const override {
288     return createVLIWMachineSched(C);
289   }
290 
291   void addIRPasses() override;
292   bool addInstSelector() override;
293   void addPreRegAlloc() override;
294   void addPostRegAlloc() override;
295   void addPreSched2() override;
296   void addPreEmitPass() override;
297 };
298 } // namespace
299 
300 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
301   return new HexagonPassConfig(*this, PM);
302 }
303 
304 void HexagonPassConfig::addIRPasses() {
305   TargetPassConfig::addIRPasses();
306   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
307 
308   if (!NoOpt) {
309     addPass(createConstantPropagationPass());
310     addPass(createDeadCodeEliminationPass());
311   }
312 
313   addPass(createAtomicExpandPass());
314   if (!NoOpt) {
315     if (EnableLoopPrefetch)
316       addPass(createLoopDataPrefetchPass());
317     if (EnableCommGEP)
318       addPass(createHexagonCommonGEP());
319     // Replace certain combinations of shifts and ands with extracts.
320     if (EnableGenExtract)
321       addPass(createHexagonGenExtract());
322   }
323 }
324 
325 bool HexagonPassConfig::addInstSelector() {
326   HexagonTargetMachine &TM = getHexagonTargetMachine();
327   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
328 
329   if (!NoOpt)
330     addPass(createHexagonOptimizeSZextends());
331 
332   addPass(createHexagonISelDag(TM, getOptLevel()));
333 
334   if (!NoOpt) {
335     if (EnableVExtractOpt)
336       addPass(createHexagonVExtract());
337     // Create logical operations on predicate registers.
338     if (EnableGenPred)
339       addPass(createHexagonGenPredicate());
340     // Rotate loops to expose bit-simplification opportunities.
341     if (EnableLoopResched)
342       addPass(createHexagonLoopRescheduling());
343     // Split double registers.
344     if (!DisableHSDR)
345       addPass(createHexagonSplitDoubleRegs());
346     // Bit simplification.
347     if (EnableBitSimplify)
348       addPass(createHexagonBitSimplify());
349     addPass(createHexagonPeephole());
350     // Constant propagation.
351     if (!DisableHCP) {
352       addPass(createHexagonConstPropagationPass());
353       addPass(&UnreachableMachineBlockElimID);
354     }
355     if (EnableGenInsert)
356       addPass(createHexagonGenInsert());
357     if (EnableEarlyIf)
358       addPass(createHexagonEarlyIfConversion());
359   }
360 
361   return false;
362 }
363 
364 void HexagonPassConfig::addPreRegAlloc() {
365   if (getOptLevel() != CodeGenOpt::None) {
366     if (EnableCExtOpt)
367       addPass(createHexagonConstExtenders());
368     if (EnableExpandCondsets)
369       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
370     if (!DisableStoreWidening)
371       addPass(createHexagonStoreWidening());
372     if (!DisableHardwareLoops)
373       addPass(createHexagonHardwareLoops());
374   }
375   if (TM->getOptLevel() >= CodeGenOpt::Default)
376     addPass(&MachinePipelinerID);
377 }
378 
379 void HexagonPassConfig::addPostRegAlloc() {
380   if (getOptLevel() != CodeGenOpt::None) {
381     if (EnableRDFOpt)
382       addPass(createHexagonRDFOpt());
383     if (!DisableHexagonCFGOpt)
384       addPass(createHexagonCFGOptimizer());
385     if (!DisableAModeOpt)
386       addPass(createHexagonOptAddrMode());
387   }
388 }
389 
390 void HexagonPassConfig::addPreSched2() {
391   addPass(createHexagonCopyToCombine());
392   if (getOptLevel() != CodeGenOpt::None)
393     addPass(&IfConverterID);
394   addPass(createHexagonSplitConst32AndConst64());
395 }
396 
397 void HexagonPassConfig::addPreEmitPass() {
398   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
399 
400   if (!NoOpt)
401     addPass(createHexagonNewValueJump());
402 
403   addPass(createHexagonBranchRelaxation());
404 
405   // Create Packets.
406   if (!NoOpt) {
407     if (!DisableHardwareLoops)
408       addPass(createHexagonFixupHwLoops());
409     // Generate MUX from pairs of conditional transfers.
410     if (EnableGenMux)
411       addPass(createHexagonGenMux());
412   }
413 
414   // Create packets for 2 instructions that consitute a gather instruction.
415   // Do this regardless of the opt level.
416   addPass(createHexagonGatherPacketize(), false);
417 
418   if (!NoOpt)
419     addPass(createHexagonPacketizer(), false);
420 
421   if (EnableVectorPrint)
422     addPass(createHexagonVectorPrint(), false);
423 
424   // Add CFI instructions if necessary.
425   addPass(createHexagonCallFrameInformation(), false);
426 }
427