1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/Scalar.h"
27 
28 using namespace llvm;
29 
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
46   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
47 
48 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
49   cl::init(true), cl::Hidden, cl::ZeroOrMore,
50   cl::desc("Early expansion of MUX"));
51 
52 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
53   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
54 
55 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
56   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
57 
58 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
59   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
60 
61 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
63 
64 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
65   cl::desc("Enable converting conditional transfers into MUX instructions"));
66 
67 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
68   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
69   "predicate instructions"));
70 
71 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
72   cl::init(false), cl::Hidden, cl::ZeroOrMore,
73   cl::desc("Enable loop data prefetch on Hexagon"));
74 
75 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
76   cl::desc("Disable splitting double registers"));
77 
78 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
79   cl::Hidden, cl::desc("Bit simplification"));
80 
81 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
82   cl::Hidden, cl::desc("Loop rescheduling"));
83 
84 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
85   cl::Hidden, cl::desc("Disable backend optimizations"));
86 
87 /// HexagonTargetMachineModule - Note that this is used on hosts that
88 /// cannot link in a library unless there are references into the
89 /// library.  In particular, it seems that it is not possible to get
90 /// things to work on Win32 without this.  Though it is unused, do not
91 /// remove it.
92 extern "C" int HexagonTargetMachineModule;
93 int HexagonTargetMachineModule = 0;
94 
95 extern "C" void LLVMInitializeHexagonTarget() {
96   // Register the target.
97   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
98 }
99 
100 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
101   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
102 }
103 
104 static MachineSchedRegistry
105 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
106                     createVLIWMachineSched);
107 
108 namespace llvm {
109   FunctionPass *createHexagonBitSimplify();
110   FunctionPass *createHexagonBranchRelaxation();
111   FunctionPass *createHexagonCallFrameInformation();
112   FunctionPass *createHexagonCFGOptimizer();
113   FunctionPass *createHexagonCommonGEP();
114   FunctionPass *createHexagonCopyToCombine();
115   FunctionPass *createHexagonEarlyIfConversion();
116   FunctionPass *createHexagonExpandCondsets();
117   FunctionPass *createHexagonFixupHwLoops();
118   FunctionPass *createHexagonGenExtract();
119   FunctionPass *createHexagonGenInsert();
120   FunctionPass *createHexagonGenMux();
121   FunctionPass *createHexagonGenPredicate();
122   FunctionPass *createHexagonHardwareLoops();
123   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
124                                      CodeGenOpt::Level OptLevel);
125   FunctionPass *createHexagonLoopRescheduling();
126   FunctionPass *createHexagonNewValueJump();
127   FunctionPass *createHexagonOptimizeSZextends();
128   FunctionPass *createHexagonOptAddrMode();
129   FunctionPass *createHexagonPacketizer();
130   FunctionPass *createHexagonPeephole();
131   FunctionPass *createHexagonRDFOpt();
132   FunctionPass *createHexagonSplitConst32AndConst64();
133   FunctionPass *createHexagonSplitDoubleRegs();
134   FunctionPass *createHexagonStoreWidening();
135 } // end namespace llvm;
136 
137 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
138   if (!RM.hasValue())
139     return Reloc::Static;
140   return *RM;
141 }
142 
143 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
144                                            StringRef CPU, StringRef FS,
145                                            const TargetOptions &Options,
146                                            Optional<Reloc::Model> RM,
147                                            CodeModel::Model CM,
148                                            CodeGenOpt::Level OL)
149     // Specify the vector alignment explicitly. For v512x1, the calculated
150     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
151     // the required minimum of 64 bytes.
152     : LLVMTargetMachine(
153           T, "e-m:e-p:32:32:32-a:0-n16:32-"
154              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
155              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
156           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
157           (HexagonNoOpt ? CodeGenOpt::None : OL)),
158       TLOF(make_unique<HexagonTargetObjectFile>()) {
159   initAsmInfo();
160 }
161 
162 const HexagonSubtarget *
163 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
164   AttributeSet FnAttrs = F.getAttributes();
165   Attribute CPUAttr =
166       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
167   Attribute FSAttr =
168       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
169 
170   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
171                         ? CPUAttr.getValueAsString().str()
172                         : TargetCPU;
173   std::string FS = !FSAttr.hasAttribute(Attribute::None)
174                        ? FSAttr.getValueAsString().str()
175                        : TargetFS;
176 
177   auto &I = SubtargetMap[CPU + FS];
178   if (!I) {
179     // This needs to be done before we create a new subtarget since any
180     // creation will depend on the TM and the code generation flags on the
181     // function that reside in TargetOptions.
182     resetTargetOptions(F);
183     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
184   }
185   return I.get();
186 }
187 
188 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
189   return TargetIRAnalysis([this](const Function &F) {
190     return TargetTransformInfo(HexagonTTIImpl(this, F));
191   });
192 }
193 
194 
195 HexagonTargetMachine::~HexagonTargetMachine() {}
196 
197 namespace {
198 /// Hexagon Code Generator Pass Configuration Options.
199 class HexagonPassConfig : public TargetPassConfig {
200 public:
201   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
202     : TargetPassConfig(TM, PM) {}
203 
204   HexagonTargetMachine &getHexagonTargetMachine() const {
205     return getTM<HexagonTargetMachine>();
206   }
207 
208   ScheduleDAGInstrs *
209   createMachineScheduler(MachineSchedContext *C) const override {
210     return createVLIWMachineSched(C);
211   }
212 
213   void addIRPasses() override;
214   bool addInstSelector() override;
215   void addPreRegAlloc() override;
216   void addPostRegAlloc() override;
217   void addPreSched2() override;
218   void addPreEmitPass() override;
219 };
220 } // namespace
221 
222 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
223   return new HexagonPassConfig(this, PM);
224 }
225 
226 void HexagonPassConfig::addIRPasses() {
227   TargetPassConfig::addIRPasses();
228   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
229 
230   addPass(createAtomicExpandPass(TM));
231   if (!NoOpt) {
232     if (EnableLoopPrefetch)
233       addPass(createLoopDataPrefetchPass());
234     if (EnableCommGEP)
235       addPass(createHexagonCommonGEP());
236     // Replace certain combinations of shifts and ands with extracts.
237     if (EnableGenExtract)
238       addPass(createHexagonGenExtract());
239   }
240 }
241 
242 bool HexagonPassConfig::addInstSelector() {
243   HexagonTargetMachine &TM = getHexagonTargetMachine();
244   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
245 
246   if (!NoOpt)
247     addPass(createHexagonOptimizeSZextends());
248 
249   addPass(createHexagonISelDag(TM, getOptLevel()));
250 
251   if (!NoOpt) {
252     // Create logical operations on predicate registers.
253     if (EnableGenPred)
254       addPass(createHexagonGenPredicate(), false);
255     // Rotate loops to expose bit-simplification opportunities.
256     if (EnableLoopResched)
257       addPass(createHexagonLoopRescheduling(), false);
258     // Split double registers.
259     if (!DisableHSDR)
260       addPass(createHexagonSplitDoubleRegs());
261     // Bit simplification.
262     if (EnableBitSimplify)
263       addPass(createHexagonBitSimplify(), false);
264     addPass(createHexagonPeephole());
265     printAndVerify("After hexagon peephole pass");
266     if (EnableGenInsert)
267       addPass(createHexagonGenInsert(), false);
268     if (EnableEarlyIf)
269       addPass(createHexagonEarlyIfConversion(), false);
270   }
271 
272   return false;
273 }
274 
275 void HexagonPassConfig::addPreRegAlloc() {
276   if (getOptLevel() != CodeGenOpt::None) {
277     if (EnableExpandCondsets) {
278       Pass *Exp = createHexagonExpandCondsets();
279       insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
280     }
281     if (!DisableStoreWidening)
282       addPass(createHexagonStoreWidening(), false);
283     if (!DisableHardwareLoops)
284       addPass(createHexagonHardwareLoops(), false);
285   }
286 }
287 
288 void HexagonPassConfig::addPostRegAlloc() {
289   if (getOptLevel() != CodeGenOpt::None) {
290     if (EnableRDFOpt)
291       addPass(createHexagonRDFOpt());
292     if (!DisableHexagonCFGOpt)
293       addPass(createHexagonCFGOptimizer(), false);
294     if (!DisableAModeOpt)
295       addPass(createHexagonOptAddrMode(), false);
296   }
297 }
298 
299 void HexagonPassConfig::addPreSched2() {
300   addPass(createHexagonCopyToCombine(), false);
301   if (getOptLevel() != CodeGenOpt::None)
302     addPass(&IfConverterID, false);
303   addPass(createHexagonSplitConst32AndConst64());
304 }
305 
306 void HexagonPassConfig::addPreEmitPass() {
307   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
308 
309   if (!NoOpt)
310     addPass(createHexagonNewValueJump(), false);
311 
312   addPass(createHexagonBranchRelaxation(), false);
313 
314   // Create Packets.
315   if (!NoOpt) {
316     if (!DisableHardwareLoops)
317       addPass(createHexagonFixupHwLoops(), false);
318     // Generate MUX from pairs of conditional transfers.
319     if (EnableGenMux)
320       addPass(createHexagonGenMux(), false);
321 
322     addPass(createHexagonPacketizer(), false);
323   }
324 
325   // Add CFI instructions if necessary.
326   addPass(createHexagonCallFrameInformation(), false);
327 }
328