1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineScheduler.h"
17 #include "HexagonTargetObjectFile.h"
18 #include "HexagonTargetTransformInfo.h"
19 #include "HexagonVectorLoopCarriedReuse.h"
20 #include "TargetInfo/HexagonTargetInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/IR/LegacyPassManager.h"
24 #include "llvm/IR/Module.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
28 #include "llvm/Transforms/Scalar.h"
29 
30 using namespace llvm;
31 
32 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
33   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
34 
35 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
36   cl::init(true), cl::desc("Enable RDF-based optimizations"));
37 
38 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
39   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
40 
41 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon Addressing Mode Optimization"));
44 
45 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
46   cl::Hidden, cl::ZeroOrMore, cl::init(false),
47   cl::desc("Disable Hexagon CFG Optimization"));
48 
49 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
50   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
51 
52 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
53   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
54 
55 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
56   cl::init(true), cl::Hidden, cl::ZeroOrMore,
57   cl::desc("Early expansion of MUX"));
58 
59 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
60   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
61 
62 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
63   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
64 
65 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
66   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
67 
68 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
69   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
70 
71 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
72   cl::desc("Enable converting conditional transfers into MUX instructions"));
73 
74 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
75   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
76   "predicate instructions"));
77 
78 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
79   cl::init(false), cl::Hidden, cl::ZeroOrMore,
80   cl::desc("Enable loop data prefetch on Hexagon"));
81 
82 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
83   cl::desc("Disable splitting double registers"));
84 
85 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
86   cl::Hidden, cl::desc("Bit simplification"));
87 
88 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
89   cl::Hidden, cl::desc("Loop rescheduling"));
90 
91 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
92   cl::Hidden, cl::desc("Disable backend optimizations"));
93 
94 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
95   cl::Hidden, cl::ZeroOrMore, cl::init(false),
96   cl::desc("Enable Hexagon Vector print instr pass"));
97 
98 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
99   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
100 
101 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
102   cl::Hidden, cl::ZeroOrMore, cl::init(true),
103   cl::desc("Simplify the CFG after atomic expansion pass"));
104 
105 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
106                                         cl::ZeroOrMore, cl::init(true),
107                                         cl::desc("Enable instsimplify"));
108 
109 /// HexagonTargetMachineModule - Note that this is used on hosts that
110 /// cannot link in a library unless there are references into the
111 /// library.  In particular, it seems that it is not possible to get
112 /// things to work on Win32 without this.  Though it is unused, do not
113 /// remove it.
114 extern "C" int HexagonTargetMachineModule;
115 int HexagonTargetMachineModule = 0;
116 
117 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
118   ScheduleDAGMILive *DAG =
119     new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
120   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
121   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
122   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
123   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
124   return DAG;
125 }
126 
127 static MachineSchedRegistry
128 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
129                     createVLIWMachineSched);
130 
131 namespace llvm {
132   extern char &HexagonExpandCondsetsID;
133   void initializeHexagonBitSimplifyPass(PassRegistry&);
134   void initializeHexagonConstExtendersPass(PassRegistry&);
135   void initializeHexagonConstPropagationPass(PassRegistry&);
136   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
137   void initializeHexagonExpandCondsetsPass(PassRegistry&);
138   void initializeHexagonGenMuxPass(PassRegistry&);
139   void initializeHexagonHardwareLoopsPass(PassRegistry&);
140   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
141   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
142   void initializeHexagonNewValueJumpPass(PassRegistry&);
143   void initializeHexagonOptAddrModePass(PassRegistry&);
144   void initializeHexagonPacketizerPass(PassRegistry&);
145   void initializeHexagonRDFOptPass(PassRegistry&);
146   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
147   void initializeHexagonVExtractPass(PassRegistry&);
148   Pass *createHexagonLoopIdiomPass();
149   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
150 
151   FunctionPass *createHexagonBitSimplify();
152   FunctionPass *createHexagonBranchRelaxation();
153   FunctionPass *createHexagonCallFrameInformation();
154   FunctionPass *createHexagonCFGOptimizer();
155   FunctionPass *createHexagonCommonGEP();
156   FunctionPass *createHexagonConstExtenders();
157   FunctionPass *createHexagonConstPropagationPass();
158   FunctionPass *createHexagonCopyToCombine();
159   FunctionPass *createHexagonEarlyIfConversion();
160   FunctionPass *createHexagonFixupHwLoops();
161   FunctionPass *createHexagonGenExtract();
162   FunctionPass *createHexagonGenInsert();
163   FunctionPass *createHexagonGenMux();
164   FunctionPass *createHexagonGenPredicate();
165   FunctionPass *createHexagonHardwareLoops();
166   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
167                                      CodeGenOpt::Level OptLevel);
168   FunctionPass *createHexagonLoopRescheduling();
169   FunctionPass *createHexagonNewValueJump();
170   FunctionPass *createHexagonOptimizeSZextends();
171   FunctionPass *createHexagonOptAddrMode();
172   FunctionPass *createHexagonPacketizer(bool Minimal);
173   FunctionPass *createHexagonPeephole();
174   FunctionPass *createHexagonRDFOpt();
175   FunctionPass *createHexagonSplitConst32AndConst64();
176   FunctionPass *createHexagonSplitDoubleRegs();
177   FunctionPass *createHexagonStoreWidening();
178   FunctionPass *createHexagonVectorPrint();
179   FunctionPass *createHexagonVExtract();
180 } // end namespace llvm;
181 
182 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
183   if (!RM.hasValue())
184     return Reloc::Static;
185   return *RM;
186 }
187 
188 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
189   // Register the target.
190   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
191 
192   PassRegistry &PR = *PassRegistry::getPassRegistry();
193   initializeHexagonBitSimplifyPass(PR);
194   initializeHexagonConstExtendersPass(PR);
195   initializeHexagonConstPropagationPass(PR);
196   initializeHexagonEarlyIfConversionPass(PR);
197   initializeHexagonGenMuxPass(PR);
198   initializeHexagonHardwareLoopsPass(PR);
199   initializeHexagonLoopIdiomRecognizePass(PR);
200   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
201   initializeHexagonNewValueJumpPass(PR);
202   initializeHexagonOptAddrModePass(PR);
203   initializeHexagonPacketizerPass(PR);
204   initializeHexagonRDFOptPass(PR);
205   initializeHexagonSplitDoubleRegsPass(PR);
206   initializeHexagonVExtractPass(PR);
207 }
208 
209 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
210                                            StringRef CPU, StringRef FS,
211                                            const TargetOptions &Options,
212                                            Optional<Reloc::Model> RM,
213                                            Optional<CodeModel::Model> CM,
214                                            CodeGenOpt::Level OL, bool JIT)
215     // Specify the vector alignment explicitly. For v512x1, the calculated
216     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
217     // the required minimum of 64 bytes.
218     : LLVMTargetMachine(
219           T,
220           "e-m:e-p:32:32:32-a:0-n16:32-"
221           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
222           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
223           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
224           getEffectiveCodeModel(CM, CodeModel::Small),
225           (HexagonNoOpt ? CodeGenOpt::None : OL)),
226       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
227   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
228   initAsmInfo();
229 }
230 
231 const HexagonSubtarget *
232 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
233   AttributeList FnAttrs = F.getAttributes();
234   Attribute CPUAttr =
235       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
236   Attribute FSAttr =
237       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
238 
239   std::string CPU =
240       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
241   std::string FS =
242       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
243   // Append the preexisting target features last, so that +mattr overrides
244   // the "unsafe-fp-math" function attribute.
245   // Creating a separate target feature is not strictly necessary, it only
246   // exists to make "unsafe-fp-math" force creating a new subtarget.
247 
248   if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
249       F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
250     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
251 
252   auto &I = SubtargetMap[CPU + FS];
253   if (!I) {
254     // This needs to be done before we create a new subtarget since any
255     // creation will depend on the TM and the code generation flags on the
256     // function that reside in TargetOptions.
257     resetTargetOptions(F);
258     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
259   }
260   return I.get();
261 }
262 
263 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
264   PMB.addExtension(
265     PassManagerBuilder::EP_LateLoopOptimizations,
266     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
267       PM.add(createHexagonLoopIdiomPass());
268     });
269   PMB.addExtension(
270       PassManagerBuilder::EP_LoopOptimizerEnd,
271       [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
272         PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
273       });
274 }
275 
276 TargetTransformInfo
277 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
278   return TargetTransformInfo(HexagonTTIImpl(this, F));
279 }
280 
281 
282 HexagonTargetMachine::~HexagonTargetMachine() {}
283 
284 namespace {
285 /// Hexagon Code Generator Pass Configuration Options.
286 class HexagonPassConfig : public TargetPassConfig {
287 public:
288   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
289     : TargetPassConfig(TM, PM) {}
290 
291   HexagonTargetMachine &getHexagonTargetMachine() const {
292     return getTM<HexagonTargetMachine>();
293   }
294 
295   ScheduleDAGInstrs *
296   createMachineScheduler(MachineSchedContext *C) const override {
297     return createVLIWMachineSched(C);
298   }
299 
300   void addIRPasses() override;
301   bool addInstSelector() override;
302   void addPreRegAlloc() override;
303   void addPostRegAlloc() override;
304   void addPreSched2() override;
305   void addPreEmitPass() override;
306 };
307 } // namespace
308 
309 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
310   return new HexagonPassConfig(*this, PM);
311 }
312 
313 void HexagonPassConfig::addIRPasses() {
314   TargetPassConfig::addIRPasses();
315   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
316 
317   if (!NoOpt) {
318     if (EnableInstSimplify)
319       addPass(createInstSimplifyLegacyPass());
320     addPass(createDeadCodeEliminationPass());
321   }
322 
323   addPass(createAtomicExpandPass());
324 
325   if (!NoOpt) {
326     if (EnableInitialCFGCleanup)
327       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
328                                               .forwardSwitchCondToPhi(true)
329                                               .convertSwitchToLookupTable(true)
330                                               .needCanonicalLoops(false)
331                                               .hoistCommonInsts(true)
332                                               .sinkCommonInsts(true)));
333     if (EnableLoopPrefetch)
334       addPass(createLoopDataPrefetchPass());
335     if (EnableCommGEP)
336       addPass(createHexagonCommonGEP());
337     // Replace certain combinations of shifts and ands with extracts.
338     if (EnableGenExtract)
339       addPass(createHexagonGenExtract());
340   }
341 }
342 
343 bool HexagonPassConfig::addInstSelector() {
344   HexagonTargetMachine &TM = getHexagonTargetMachine();
345   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
346 
347   if (!NoOpt)
348     addPass(createHexagonOptimizeSZextends());
349 
350   addPass(createHexagonISelDag(TM, getOptLevel()));
351 
352   if (!NoOpt) {
353     if (EnableVExtractOpt)
354       addPass(createHexagonVExtract());
355     // Create logical operations on predicate registers.
356     if (EnableGenPred)
357       addPass(createHexagonGenPredicate());
358     // Rotate loops to expose bit-simplification opportunities.
359     if (EnableLoopResched)
360       addPass(createHexagonLoopRescheduling());
361     // Split double registers.
362     if (!DisableHSDR)
363       addPass(createHexagonSplitDoubleRegs());
364     // Bit simplification.
365     if (EnableBitSimplify)
366       addPass(createHexagonBitSimplify());
367     addPass(createHexagonPeephole());
368     // Constant propagation.
369     if (!DisableHCP) {
370       addPass(createHexagonConstPropagationPass());
371       addPass(&UnreachableMachineBlockElimID);
372     }
373     if (EnableGenInsert)
374       addPass(createHexagonGenInsert());
375     if (EnableEarlyIf)
376       addPass(createHexagonEarlyIfConversion());
377   }
378 
379   return false;
380 }
381 
382 void HexagonPassConfig::addPreRegAlloc() {
383   if (getOptLevel() != CodeGenOpt::None) {
384     if (EnableCExtOpt)
385       addPass(createHexagonConstExtenders());
386     if (EnableExpandCondsets)
387       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
388     if (!DisableStoreWidening)
389       addPass(createHexagonStoreWidening());
390     if (!DisableHardwareLoops)
391       addPass(createHexagonHardwareLoops());
392   }
393   if (TM->getOptLevel() >= CodeGenOpt::Default)
394     addPass(&MachinePipelinerID);
395 }
396 
397 void HexagonPassConfig::addPostRegAlloc() {
398   if (getOptLevel() != CodeGenOpt::None) {
399     if (EnableRDFOpt)
400       addPass(createHexagonRDFOpt());
401     if (!DisableHexagonCFGOpt)
402       addPass(createHexagonCFGOptimizer());
403     if (!DisableAModeOpt)
404       addPass(createHexagonOptAddrMode());
405   }
406 }
407 
408 void HexagonPassConfig::addPreSched2() {
409   addPass(createHexagonCopyToCombine());
410   if (getOptLevel() != CodeGenOpt::None)
411     addPass(&IfConverterID);
412   addPass(createHexagonSplitConst32AndConst64());
413 }
414 
415 void HexagonPassConfig::addPreEmitPass() {
416   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
417 
418   if (!NoOpt)
419     addPass(createHexagonNewValueJump());
420 
421   addPass(createHexagonBranchRelaxation());
422 
423   if (!NoOpt) {
424     if (!DisableHardwareLoops)
425       addPass(createHexagonFixupHwLoops());
426     // Generate MUX from pairs of conditional transfers.
427     if (EnableGenMux)
428       addPass(createHexagonGenMux());
429   }
430 
431   // Packetization is mandatory: it handles gather/scatter at all opt levels.
432   addPass(createHexagonPacketizer(NoOpt), false);
433 
434   if (EnableVectorPrint)
435     addPass(createHexagonVectorPrint(), false);
436 
437   // Add CFI instructions if necessary.
438   addPass(createHexagonCallFrameInformation(), false);
439 }
440