1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
101   cl::Hidden, cl::ZeroOrMore, cl::init(true),
102   cl::desc("Simplify the CFG after atomic expansion pass"));
103 
104 /// HexagonTargetMachineModule - Note that this is used on hosts that
105 /// cannot link in a library unless there are references into the
106 /// library.  In particular, it seems that it is not possible to get
107 /// things to work on Win32 without this.  Though it is unused, do not
108 /// remove it.
109 extern "C" int HexagonTargetMachineModule;
110 int HexagonTargetMachineModule = 0;
111 
112 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
113   ScheduleDAGMILive *DAG =
114     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
115   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
116   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
117   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
118   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
119   return DAG;
120 }
121 
122 static MachineSchedRegistry
123 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
124                     createVLIWMachineSched);
125 
126 namespace llvm {
127   extern char &HexagonExpandCondsetsID;
128   void initializeHexagonBitSimplifyPass(PassRegistry&);
129   void initializeHexagonConstExtendersPass(PassRegistry&);
130   void initializeHexagonConstPropagationPass(PassRegistry&);
131   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
132   void initializeHexagonExpandCondsetsPass(PassRegistry&);
133   void initializeHexagonGenMuxPass(PassRegistry&);
134   void initializeHexagonHardwareLoopsPass(PassRegistry&);
135   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
136   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
137   void initializeHexagonNewValueJumpPass(PassRegistry&);
138   void initializeHexagonOptAddrModePass(PassRegistry&);
139   void initializeHexagonPacketizerPass(PassRegistry&);
140   void initializeHexagonRDFOptPass(PassRegistry&);
141   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
142   void initializeHexagonVExtractPass(PassRegistry&);
143   Pass *createHexagonLoopIdiomPass();
144   Pass *createHexagonVectorLoopCarriedReusePass();
145 
146   FunctionPass *createHexagonBitSimplify();
147   FunctionPass *createHexagonBranchRelaxation();
148   FunctionPass *createHexagonCallFrameInformation();
149   FunctionPass *createHexagonCFGOptimizer();
150   FunctionPass *createHexagonCommonGEP();
151   FunctionPass *createHexagonConstExtenders();
152   FunctionPass *createHexagonConstPropagationPass();
153   FunctionPass *createHexagonCopyToCombine();
154   FunctionPass *createHexagonEarlyIfConversion();
155   FunctionPass *createHexagonFixupHwLoops();
156   FunctionPass *createHexagonGatherPacketize();
157   FunctionPass *createHexagonGenExtract();
158   FunctionPass *createHexagonGenInsert();
159   FunctionPass *createHexagonGenMux();
160   FunctionPass *createHexagonGenPredicate();
161   FunctionPass *createHexagonHardwareLoops();
162   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
163                                      CodeGenOpt::Level OptLevel);
164   FunctionPass *createHexagonLoopRescheduling();
165   FunctionPass *createHexagonNewValueJump();
166   FunctionPass *createHexagonOptimizeSZextends();
167   FunctionPass *createHexagonOptAddrMode();
168   FunctionPass *createHexagonPacketizer();
169   FunctionPass *createHexagonPeephole();
170   FunctionPass *createHexagonRDFOpt();
171   FunctionPass *createHexagonSplitConst32AndConst64();
172   FunctionPass *createHexagonSplitDoubleRegs();
173   FunctionPass *createHexagonStoreWidening();
174   FunctionPass *createHexagonVectorPrint();
175   FunctionPass *createHexagonVExtract();
176 } // end namespace llvm;
177 
178 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
179   if (!RM.hasValue())
180     return Reloc::Static;
181   return *RM;
182 }
183 
184 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
185   if (CM)
186     return *CM;
187   return CodeModel::Small;
188 }
189 
190 extern "C" void LLVMInitializeHexagonTarget() {
191   // Register the target.
192   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
193 
194   PassRegistry &PR = *PassRegistry::getPassRegistry();
195   initializeHexagonBitSimplifyPass(PR);
196   initializeHexagonConstExtendersPass(PR);
197   initializeHexagonConstPropagationPass(PR);
198   initializeHexagonEarlyIfConversionPass(PR);
199   initializeHexagonGenMuxPass(PR);
200   initializeHexagonHardwareLoopsPass(PR);
201   initializeHexagonLoopIdiomRecognizePass(PR);
202   initializeHexagonVectorLoopCarriedReusePass(PR);
203   initializeHexagonNewValueJumpPass(PR);
204   initializeHexagonOptAddrModePass(PR);
205   initializeHexagonPacketizerPass(PR);
206   initializeHexagonRDFOptPass(PR);
207   initializeHexagonSplitDoubleRegsPass(PR);
208   initializeHexagonVExtractPass(PR);
209 }
210 
211 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
212                                            StringRef CPU, StringRef FS,
213                                            const TargetOptions &Options,
214                                            Optional<Reloc::Model> RM,
215                                            Optional<CodeModel::Model> CM,
216                                            CodeGenOpt::Level OL, bool JIT)
217     // Specify the vector alignment explicitly. For v512x1, the calculated
218     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
219     // the required minimum of 64 bytes.
220     : LLVMTargetMachine(
221           T,
222           "e-m:e-p:32:32:32-a:0-n16:32-"
223           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
224           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
225           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
226           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
227       TLOF(make_unique<HexagonTargetObjectFile>()) {
228   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
229   initAsmInfo();
230 }
231 
232 const HexagonSubtarget *
233 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
234   AttributeList FnAttrs = F.getAttributes();
235   Attribute CPUAttr =
236       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
237   Attribute FSAttr =
238       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
239 
240   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
241                         ? CPUAttr.getValueAsString().str()
242                         : TargetCPU;
243   std::string FS = !FSAttr.hasAttribute(Attribute::None)
244                        ? FSAttr.getValueAsString().str()
245                        : TargetFS;
246 
247   auto &I = SubtargetMap[CPU + FS];
248   if (!I) {
249     // This needs to be done before we create a new subtarget since any
250     // creation will depend on the TM and the code generation flags on the
251     // function that reside in TargetOptions.
252     resetTargetOptions(F);
253     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
254   }
255   return I.get();
256 }
257 
258 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
259   PMB.addExtension(
260     PassManagerBuilder::EP_LateLoopOptimizations,
261     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
262       PM.add(createHexagonLoopIdiomPass());
263     });
264   PMB.addExtension(
265     PassManagerBuilder::EP_LoopOptimizerEnd,
266     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
267       PM.add(createHexagonVectorLoopCarriedReusePass());
268     });
269 }
270 
271 TargetTransformInfo
272 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
273   return TargetTransformInfo(HexagonTTIImpl(this, F));
274 }
275 
276 
277 HexagonTargetMachine::~HexagonTargetMachine() {}
278 
279 namespace {
280 /// Hexagon Code Generator Pass Configuration Options.
281 class HexagonPassConfig : public TargetPassConfig {
282 public:
283   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
284     : TargetPassConfig(TM, PM) {}
285 
286   HexagonTargetMachine &getHexagonTargetMachine() const {
287     return getTM<HexagonTargetMachine>();
288   }
289 
290   ScheduleDAGInstrs *
291   createMachineScheduler(MachineSchedContext *C) const override {
292     return createVLIWMachineSched(C);
293   }
294 
295   void addIRPasses() override;
296   bool addInstSelector() override;
297   void addPreRegAlloc() override;
298   void addPostRegAlloc() override;
299   void addPreSched2() override;
300   void addPreEmitPass() override;
301 };
302 } // namespace
303 
304 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
305   return new HexagonPassConfig(*this, PM);
306 }
307 
308 void HexagonPassConfig::addIRPasses() {
309   TargetPassConfig::addIRPasses();
310   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
311 
312   if (!NoOpt) {
313     addPass(createConstantPropagationPass());
314     addPass(createDeadCodeEliminationPass());
315   }
316 
317   addPass(createAtomicExpandPass());
318 
319   if (!NoOpt) {
320     if (EnableInitialCFGCleanup)
321       addPass(createCFGSimplificationPass(1, true, true, false, true));
322     if (EnableLoopPrefetch)
323       addPass(createLoopDataPrefetchPass());
324     if (EnableCommGEP)
325       addPass(createHexagonCommonGEP());
326     // Replace certain combinations of shifts and ands with extracts.
327     if (EnableGenExtract)
328       addPass(createHexagonGenExtract());
329   }
330 }
331 
332 bool HexagonPassConfig::addInstSelector() {
333   HexagonTargetMachine &TM = getHexagonTargetMachine();
334   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
335 
336   if (!NoOpt)
337     addPass(createHexagonOptimizeSZextends());
338 
339   addPass(createHexagonISelDag(TM, getOptLevel()));
340 
341   if (!NoOpt) {
342     if (EnableVExtractOpt)
343       addPass(createHexagonVExtract());
344     // Create logical operations on predicate registers.
345     if (EnableGenPred)
346       addPass(createHexagonGenPredicate());
347     // Rotate loops to expose bit-simplification opportunities.
348     if (EnableLoopResched)
349       addPass(createHexagonLoopRescheduling());
350     // Split double registers.
351     if (!DisableHSDR)
352       addPass(createHexagonSplitDoubleRegs());
353     // Bit simplification.
354     if (EnableBitSimplify)
355       addPass(createHexagonBitSimplify());
356     addPass(createHexagonPeephole());
357     // Constant propagation.
358     if (!DisableHCP) {
359       addPass(createHexagonConstPropagationPass());
360       addPass(&UnreachableMachineBlockElimID);
361     }
362     if (EnableGenInsert)
363       addPass(createHexagonGenInsert());
364     if (EnableEarlyIf)
365       addPass(createHexagonEarlyIfConversion());
366   }
367 
368   return false;
369 }
370 
371 void HexagonPassConfig::addPreRegAlloc() {
372   if (getOptLevel() != CodeGenOpt::None) {
373     if (EnableCExtOpt)
374       addPass(createHexagonConstExtenders());
375     if (EnableExpandCondsets)
376       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
377     if (!DisableStoreWidening)
378       addPass(createHexagonStoreWidening());
379     if (!DisableHardwareLoops)
380       addPass(createHexagonHardwareLoops());
381   }
382   if (TM->getOptLevel() >= CodeGenOpt::Default)
383     addPass(&MachinePipelinerID);
384 }
385 
386 void HexagonPassConfig::addPostRegAlloc() {
387   if (getOptLevel() != CodeGenOpt::None) {
388     if (EnableRDFOpt)
389       addPass(createHexagonRDFOpt());
390     if (!DisableHexagonCFGOpt)
391       addPass(createHexagonCFGOptimizer());
392     if (!DisableAModeOpt)
393       addPass(createHexagonOptAddrMode());
394   }
395 }
396 
397 void HexagonPassConfig::addPreSched2() {
398   addPass(createHexagonCopyToCombine());
399   if (getOptLevel() != CodeGenOpt::None)
400     addPass(&IfConverterID);
401   addPass(createHexagonSplitConst32AndConst64());
402 }
403 
404 void HexagonPassConfig::addPreEmitPass() {
405   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
406 
407   if (!NoOpt)
408     addPass(createHexagonNewValueJump());
409 
410   addPass(createHexagonBranchRelaxation());
411 
412   // Create Packets.
413   if (!NoOpt) {
414     if (!DisableHardwareLoops)
415       addPass(createHexagonFixupHwLoops());
416     // Generate MUX from pairs of conditional transfers.
417     if (EnableGenMux)
418       addPass(createHexagonGenMux());
419   }
420 
421   // Create packets for 2 instructions that consitute a gather instruction.
422   // Do this regardless of the opt level.
423   addPass(createHexagonGatherPacketize(), false);
424 
425   if (!NoOpt)
426     addPass(createHexagonPacketizer(), false);
427 
428   if (EnableVectorPrint)
429     addPass(createHexagonVectorPrint(), false);
430 
431   // Add CFI instructions if necessary.
432   addPass(createHexagonCallFrameInformation(), false);
433 }
434