1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 static cl::opt<bool> EnableTrapUnreachable("hexagon-trap-unreachable",
95   cl::Hidden, cl::ZeroOrMore, cl::init(false),
96   cl::desc("Enable generating trap for unreachable"));
97 
98 /// HexagonTargetMachineModule - Note that this is used on hosts that
99 /// cannot link in a library unless there are references into the
100 /// library.  In particular, it seems that it is not possible to get
101 /// things to work on Win32 without this.  Though it is unused, do not
102 /// remove it.
103 extern "C" int HexagonTargetMachineModule;
104 int HexagonTargetMachineModule = 0;
105 
106 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
107   ScheduleDAGMILive *DAG =
108     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
109   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
110   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
111   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
112   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
113   return DAG;
114 }
115 
116 static MachineSchedRegistry
117 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
118                     createVLIWMachineSched);
119 
120 namespace llvm {
121   extern char &HexagonExpandCondsetsID;
122   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
123   void initializeHexagonExpandCondsetsPass(PassRegistry&);
124   void initializeHexagonGenMuxPass(PassRegistry&);
125   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
126   void initializeHexagonNewValueJumpPass(PassRegistry&);
127   void initializeHexagonOptAddrModePass(PassRegistry&);
128   void initializeHexagonPacketizerPass(PassRegistry&);
129   Pass *createHexagonLoopIdiomPass();
130 
131   FunctionPass *createHexagonBitSimplify();
132   FunctionPass *createHexagonBranchRelaxation();
133   FunctionPass *createHexagonCallFrameInformation();
134   FunctionPass *createHexagonCFGOptimizer();
135   FunctionPass *createHexagonCommonGEP();
136   FunctionPass *createHexagonConstPropagationPass();
137   FunctionPass *createHexagonCopyToCombine();
138   FunctionPass *createHexagonEarlyIfConversion();
139   FunctionPass *createHexagonFixupHwLoops();
140   FunctionPass *createHexagonGenExtract();
141   FunctionPass *createHexagonGenInsert();
142   FunctionPass *createHexagonGenMux();
143   FunctionPass *createHexagonGenPredicate();
144   FunctionPass *createHexagonHardwareLoops();
145   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
146                                      CodeGenOpt::Level OptLevel);
147   FunctionPass *createHexagonLoopRescheduling();
148   FunctionPass *createHexagonNewValueJump();
149   FunctionPass *createHexagonOptimizeSZextends();
150   FunctionPass *createHexagonOptAddrMode();
151   FunctionPass *createHexagonPacketizer();
152   FunctionPass *createHexagonPeephole();
153   FunctionPass *createHexagonRDFOpt();
154   FunctionPass *createHexagonSplitConst32AndConst64();
155   FunctionPass *createHexagonSplitDoubleRegs();
156   FunctionPass *createHexagonStoreWidening();
157   FunctionPass *createHexagonVectorPrint();
158 } // end namespace llvm;
159 
160 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
161   if (!RM.hasValue())
162     return Reloc::Static;
163   return *RM;
164 }
165 
166 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
167   if (CM)
168     return *CM;
169   return CodeModel::Small;
170 }
171 
172 extern "C" void LLVMInitializeHexagonTarget() {
173   // Register the target.
174   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
175 
176   PassRegistry &PR = *PassRegistry::getPassRegistry();
177   initializeHexagonEarlyIfConversionPass(PR);
178   initializeHexagonGenMuxPass(PR);
179   initializeHexagonLoopIdiomRecognizePass(PR);
180   initializeHexagonNewValueJumpPass(PR);
181   initializeHexagonOptAddrModePass(PR);
182   initializeHexagonPacketizerPass(PR);
183 }
184 
185 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
186                                            StringRef CPU, StringRef FS,
187                                            const TargetOptions &Options,
188                                            Optional<Reloc::Model> RM,
189                                            Optional<CodeModel::Model> CM,
190                                            CodeGenOpt::Level OL, bool JIT)
191     // Specify the vector alignment explicitly. For v512x1, the calculated
192     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
193     // the required minimum of 64 bytes.
194     : LLVMTargetMachine(
195           T,
196           "e-m:e-p:32:32:32-a:0-n16:32-"
197           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
198           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
199           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
200           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
201       TLOF(make_unique<HexagonTargetObjectFile>()) {
202   if (EnableTrapUnreachable)
203     this->Options.TrapUnreachable = true;
204   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
205   initAsmInfo();
206 }
207 
208 const HexagonSubtarget *
209 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
210   AttributeList FnAttrs = F.getAttributes();
211   Attribute CPUAttr =
212       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
213   Attribute FSAttr =
214       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
215 
216   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
217                         ? CPUAttr.getValueAsString().str()
218                         : TargetCPU;
219   std::string FS = !FSAttr.hasAttribute(Attribute::None)
220                        ? FSAttr.getValueAsString().str()
221                        : TargetFS;
222 
223   auto &I = SubtargetMap[CPU + FS];
224   if (!I) {
225     // This needs to be done before we create a new subtarget since any
226     // creation will depend on the TM and the code generation flags on the
227     // function that reside in TargetOptions.
228     resetTargetOptions(F);
229     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
230   }
231   return I.get();
232 }
233 
234 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
235   PMB.addExtension(
236     PassManagerBuilder::EP_LateLoopOptimizations,
237     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
238       PM.add(createHexagonLoopIdiomPass());
239     });
240 }
241 
242 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
243   return TargetIRAnalysis([this](const Function &F) {
244     return TargetTransformInfo(HexagonTTIImpl(this, F));
245   });
246 }
247 
248 
249 HexagonTargetMachine::~HexagonTargetMachine() {}
250 
251 namespace {
252 /// Hexagon Code Generator Pass Configuration Options.
253 class HexagonPassConfig : public TargetPassConfig {
254 public:
255   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
256     : TargetPassConfig(TM, PM) {}
257 
258   HexagonTargetMachine &getHexagonTargetMachine() const {
259     return getTM<HexagonTargetMachine>();
260   }
261 
262   ScheduleDAGInstrs *
263   createMachineScheduler(MachineSchedContext *C) const override {
264     return createVLIWMachineSched(C);
265   }
266 
267   void addIRPasses() override;
268   bool addInstSelector() override;
269   void addPreRegAlloc() override;
270   void addPostRegAlloc() override;
271   void addPreSched2() override;
272   void addPreEmitPass() override;
273 };
274 } // namespace
275 
276 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
277   return new HexagonPassConfig(*this, PM);
278 }
279 
280 void HexagonPassConfig::addIRPasses() {
281   TargetPassConfig::addIRPasses();
282   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
283 
284   addPass(createAtomicExpandPass());
285   if (!NoOpt) {
286     if (EnableLoopPrefetch)
287       addPass(createLoopDataPrefetchPass());
288     if (EnableCommGEP)
289       addPass(createHexagonCommonGEP());
290     // Replace certain combinations of shifts and ands with extracts.
291     if (EnableGenExtract)
292       addPass(createHexagonGenExtract());
293   }
294 }
295 
296 bool HexagonPassConfig::addInstSelector() {
297   HexagonTargetMachine &TM = getHexagonTargetMachine();
298   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
299 
300   if (!NoOpt)
301     addPass(createHexagonOptimizeSZextends());
302 
303   addPass(createHexagonISelDag(TM, getOptLevel()));
304 
305   if (!NoOpt) {
306     // Create logical operations on predicate registers.
307     if (EnableGenPred)
308       addPass(createHexagonGenPredicate());
309     // Rotate loops to expose bit-simplification opportunities.
310     if (EnableLoopResched)
311       addPass(createHexagonLoopRescheduling());
312     // Split double registers.
313     if (!DisableHSDR)
314       addPass(createHexagonSplitDoubleRegs());
315     // Bit simplification.
316     if (EnableBitSimplify)
317       addPass(createHexagonBitSimplify());
318     addPass(createHexagonPeephole());
319     // Constant propagation.
320     if (!DisableHCP) {
321       addPass(createHexagonConstPropagationPass());
322       addPass(&UnreachableMachineBlockElimID);
323     }
324     if (EnableGenInsert)
325       addPass(createHexagonGenInsert());
326     if (EnableEarlyIf)
327       addPass(createHexagonEarlyIfConversion());
328   }
329 
330   return false;
331 }
332 
333 void HexagonPassConfig::addPreRegAlloc() {
334   if (getOptLevel() != CodeGenOpt::None) {
335     if (EnableExpandCondsets)
336       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
337     if (!DisableStoreWidening)
338       addPass(createHexagonStoreWidening());
339     if (!DisableHardwareLoops)
340       addPass(createHexagonHardwareLoops());
341   }
342   if (TM->getOptLevel() >= CodeGenOpt::Default)
343     addPass(&MachinePipelinerID);
344 }
345 
346 void HexagonPassConfig::addPostRegAlloc() {
347   if (getOptLevel() != CodeGenOpt::None) {
348     if (EnableRDFOpt)
349       addPass(createHexagonRDFOpt());
350     if (!DisableHexagonCFGOpt)
351       addPass(createHexagonCFGOptimizer());
352     if (!DisableAModeOpt)
353       addPass(createHexagonOptAddrMode());
354   }
355 }
356 
357 void HexagonPassConfig::addPreSched2() {
358   addPass(createHexagonCopyToCombine());
359   if (getOptLevel() != CodeGenOpt::None)
360     addPass(&IfConverterID);
361   addPass(createHexagonSplitConst32AndConst64());
362 }
363 
364 void HexagonPassConfig::addPreEmitPass() {
365   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
366 
367   if (!NoOpt)
368     addPass(createHexagonNewValueJump());
369 
370   addPass(createHexagonBranchRelaxation());
371 
372   // Create Packets.
373   if (!NoOpt) {
374     if (!DisableHardwareLoops)
375       addPass(createHexagonFixupHwLoops());
376     // Generate MUX from pairs of conditional transfers.
377     if (EnableGenMux)
378       addPass(createHexagonGenMux());
379 
380     addPass(createHexagonPacketizer(), false);
381   }
382   if (EnableVectorPrint)
383     addPass(createHexagonVectorPrint(), false);
384 
385   // Add CFI instructions if necessary.
386   addPass(createHexagonCallFrameInformation(), false);
387 }
388