1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/Scalar.h"
27 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 /// HexagonTargetMachineModule - Note that this is used on hosts that
95 /// cannot link in a library unless there are references into the
96 /// library.  In particular, it seems that it is not possible to get
97 /// things to work on Win32 without this.  Though it is unused, do not
98 /// remove it.
99 extern "C" int HexagonTargetMachineModule;
100 int HexagonTargetMachineModule = 0;
101 
102 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
103   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
104 }
105 
106 static MachineSchedRegistry
107 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
108                     createVLIWMachineSched);
109 
110 namespace llvm {
111   extern char &HexagonExpandCondsetsID;
112   void initializeHexagonExpandCondsetsPass(PassRegistry&);
113   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
114   Pass *createHexagonLoopIdiomPass();
115 
116   FunctionPass *createHexagonBitSimplify();
117   FunctionPass *createHexagonBranchRelaxation();
118   FunctionPass *createHexagonCallFrameInformation();
119   FunctionPass *createHexagonCFGOptimizer();
120   FunctionPass *createHexagonCommonGEP();
121   FunctionPass *createHexagonConstPropagationPass();
122   FunctionPass *createHexagonCopyToCombine();
123   FunctionPass *createHexagonEarlyIfConversion();
124   FunctionPass *createHexagonFixupHwLoops();
125   FunctionPass *createHexagonGenExtract();
126   FunctionPass *createHexagonGenInsert();
127   FunctionPass *createHexagonGenMux();
128   FunctionPass *createHexagonGenPredicate();
129   FunctionPass *createHexagonHardwareLoops();
130   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
131                                      CodeGenOpt::Level OptLevel);
132   FunctionPass *createHexagonLoopRescheduling();
133   FunctionPass *createHexagonNewValueJump();
134   FunctionPass *createHexagonOptimizeSZextends();
135   FunctionPass *createHexagonOptAddrMode();
136   FunctionPass *createHexagonPacketizer();
137   FunctionPass *createHexagonPeephole();
138   FunctionPass *createHexagonRDFOpt();
139   FunctionPass *createHexagonSplitConst32AndConst64();
140   FunctionPass *createHexagonSplitDoubleRegs();
141   FunctionPass *createHexagonStoreWidening();
142   FunctionPass *createHexagonVectorPrint();
143 } // end namespace llvm;
144 
145 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
146   if (!RM.hasValue())
147     return Reloc::Static;
148   return *RM;
149 }
150 
151 extern "C" void LLVMInitializeHexagonTarget() {
152   // Register the target.
153   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
154   initializeHexagonLoopIdiomRecognizePass(*PassRegistry::getPassRegistry());
155 }
156 
157 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
158                                            StringRef CPU, StringRef FS,
159                                            const TargetOptions &Options,
160                                            Optional<Reloc::Model> RM,
161                                            CodeModel::Model CM,
162                                            CodeGenOpt::Level OL)
163     // Specify the vector alignment explicitly. For v512x1, the calculated
164     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
165     // the required minimum of 64 bytes.
166     : LLVMTargetMachine(
167           T, "e-m:e-p:32:32:32-a:0-n16:32-"
168              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
169              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
170           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
171           (HexagonNoOpt ? CodeGenOpt::None : OL)),
172       TLOF(make_unique<HexagonTargetObjectFile>()) {
173   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
174   initAsmInfo();
175 }
176 
177 const HexagonSubtarget *
178 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
179   AttributeSet FnAttrs = F.getAttributes();
180   Attribute CPUAttr =
181       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
182   Attribute FSAttr =
183       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
184 
185   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
186                         ? CPUAttr.getValueAsString().str()
187                         : TargetCPU;
188   std::string FS = !FSAttr.hasAttribute(Attribute::None)
189                        ? FSAttr.getValueAsString().str()
190                        : TargetFS;
191 
192   auto &I = SubtargetMap[CPU + FS];
193   if (!I) {
194     // This needs to be done before we create a new subtarget since any
195     // creation will depend on the TM and the code generation flags on the
196     // function that reside in TargetOptions.
197     resetTargetOptions(F);
198     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
199   }
200   return I.get();
201 }
202 
203 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
204   PMB.addExtension(
205     PassManagerBuilder::EP_LateLoopOptimizations,
206     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
207       PM.add(createHexagonLoopIdiomPass());
208     });
209 }
210 
211 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
212   return TargetIRAnalysis([this](const Function &F) {
213     return TargetTransformInfo(HexagonTTIImpl(this, F));
214   });
215 }
216 
217 
218 HexagonTargetMachine::~HexagonTargetMachine() {}
219 
220 namespace {
221 /// Hexagon Code Generator Pass Configuration Options.
222 class HexagonPassConfig : public TargetPassConfig {
223 public:
224   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
225     : TargetPassConfig(TM, PM) {}
226 
227   HexagonTargetMachine &getHexagonTargetMachine() const {
228     return getTM<HexagonTargetMachine>();
229   }
230 
231   ScheduleDAGInstrs *
232   createMachineScheduler(MachineSchedContext *C) const override {
233     return createVLIWMachineSched(C);
234   }
235 
236   void addIRPasses() override;
237   bool addInstSelector() override;
238   void addPreRegAlloc() override;
239   void addPostRegAlloc() override;
240   void addPreSched2() override;
241   void addPreEmitPass() override;
242 };
243 } // namespace
244 
245 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
246   return new HexagonPassConfig(this, PM);
247 }
248 
249 void HexagonPassConfig::addIRPasses() {
250   TargetPassConfig::addIRPasses();
251   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
252 
253   addPass(createAtomicExpandPass(TM));
254   if (!NoOpt) {
255     if (EnableLoopPrefetch)
256       addPass(createLoopDataPrefetchPass());
257     if (EnableCommGEP)
258       addPass(createHexagonCommonGEP());
259     // Replace certain combinations of shifts and ands with extracts.
260     if (EnableGenExtract)
261       addPass(createHexagonGenExtract());
262   }
263 }
264 
265 bool HexagonPassConfig::addInstSelector() {
266   HexagonTargetMachine &TM = getHexagonTargetMachine();
267   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
268 
269   if (!NoOpt)
270     addPass(createHexagonOptimizeSZextends());
271 
272   addPass(createHexagonISelDag(TM, getOptLevel()));
273 
274   if (!NoOpt) {
275     // Create logical operations on predicate registers.
276     if (EnableGenPred)
277       addPass(createHexagonGenPredicate(), false);
278     // Rotate loops to expose bit-simplification opportunities.
279     if (EnableLoopResched)
280       addPass(createHexagonLoopRescheduling(), false);
281     // Split double registers.
282     if (!DisableHSDR)
283       addPass(createHexagonSplitDoubleRegs());
284     // Bit simplification.
285     if (EnableBitSimplify)
286       addPass(createHexagonBitSimplify(), false);
287     addPass(createHexagonPeephole());
288     printAndVerify("After hexagon peephole pass");
289     // Constant propagation.
290     if (!DisableHCP) {
291       addPass(createHexagonConstPropagationPass(), false);
292       addPass(&UnreachableMachineBlockElimID, false);
293     }
294     if (EnableGenInsert)
295       addPass(createHexagonGenInsert(), false);
296     if (EnableEarlyIf)
297       addPass(createHexagonEarlyIfConversion(), false);
298   }
299 
300   return false;
301 }
302 
303 void HexagonPassConfig::addPreRegAlloc() {
304   if (getOptLevel() != CodeGenOpt::None) {
305     if (EnableExpandCondsets)
306       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
307     if (!DisableStoreWidening)
308       addPass(createHexagonStoreWidening(), false);
309     if (!DisableHardwareLoops)
310       addPass(createHexagonHardwareLoops(), false);
311   }
312   if (TM->getOptLevel() >= CodeGenOpt::Default)
313     addPass(&MachinePipelinerID);
314 }
315 
316 void HexagonPassConfig::addPostRegAlloc() {
317   if (getOptLevel() != CodeGenOpt::None) {
318     if (EnableRDFOpt)
319       addPass(createHexagonRDFOpt());
320     if (!DisableHexagonCFGOpt)
321       addPass(createHexagonCFGOptimizer(), false);
322     if (!DisableAModeOpt)
323       addPass(createHexagonOptAddrMode(), false);
324   }
325 }
326 
327 void HexagonPassConfig::addPreSched2() {
328   addPass(createHexagonCopyToCombine(), false);
329   if (getOptLevel() != CodeGenOpt::None)
330     addPass(&IfConverterID, false);
331   addPass(createHexagonSplitConst32AndConst64());
332 }
333 
334 void HexagonPassConfig::addPreEmitPass() {
335   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
336 
337   if (!NoOpt)
338     addPass(createHexagonNewValueJump(), false);
339 
340   addPass(createHexagonBranchRelaxation(), false);
341 
342   // Create Packets.
343   if (!NoOpt) {
344     if (!DisableHardwareLoops)
345       addPass(createHexagonFixupHwLoops(), false);
346     // Generate MUX from pairs of conditional transfers.
347     if (EnableGenMux)
348       addPass(createHexagonGenMux(), false);
349 
350     addPass(createHexagonPacketizer(), false);
351   }
352   if (EnableVectorPrint)
353     addPass(createHexagonVectorPrint(), false);
354 
355   // Add CFI instructions if necessary.
356   addPass(createHexagonCallFrameInformation(), false);
357 }
358